From 3b08801efb34a39d3a148538963d4747184db288 Mon Sep 17 00:00:00 2001 From: "Sergey \"Shnatsel\" Davidoff" Date: Sat, 25 Jul 2026 09:42:43 +0100 Subject: [PATCH] Optimize SSE4.2 as suggested by axnsan12, with an extra OR to preserve correctness for mask values 128-255. Changes the control sequence from vpcmpgtb + vpblendvb to vpaddb + vpor. 15% throughput improvement on Haswell, 20% improvement on skylake, zen1, zen3. For the 256-bit case, 38% improvement on haswell, 12% on skylake, zen1 and zen3 unchanged. Expand test coverage to cover byte values 128-255 which would misbehave without the OR. --- crates/core_simd/src/swizzle_dyn.rs | 7 ++++--- crates/core_simd/tests/swizzle_dyn.rs | 2 +- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/crates/core_simd/src/swizzle_dyn.rs b/crates/core_simd/src/swizzle_dyn.rs index db25783057e..f0253c284e3 100644 --- a/crates/core_simd/src/swizzle_dyn.rs +++ b/crates/core_simd/src/swizzle_dyn.rs @@ -338,7 +338,8 @@ unsafe fn transize( #[allow(unused)] #[inline(always)] fn zeroing_idxs(idxs: Simd) -> Simd { - use crate::simd::{Select, cmp::SimdPartialOrd}; - idxs.simd_lt(Simd::splat(N as u8)) - .select(idxs, Simd::splat(u8::MAX)) + // Adding this sets the high bit for indices N..=127, while PSHUFB ignores + // the other changed bits. The OR preserves the high bit for indices 128..=255. + let zeroing_bits = idxs + Simd::splat((127 - N + 1) as u8); + idxs | zeroing_bits } diff --git a/crates/core_simd/tests/swizzle_dyn.rs b/crates/core_simd/tests/swizzle_dyn.rs index 19ffe1417c8..4ab6c41c074 100644 --- a/crates/core_simd/tests/swizzle_dyn.rs +++ b/crates/core_simd/tests/swizzle_dyn.rs @@ -61,7 +61,7 @@ pub trait SwizzleStrategy { impl SwizzleStrategy for u8 { type Strategy = RangeInclusive; fn swizzled_strategy() -> Self::Strategy { - 0..=64 + 0..=u8::MAX } }