+
diff --git a/compiler/rustc_borrowck/src/type_check/liveness/trace.rs b/compiler/rustc_borrowck/src/type_check/liveness/trace.rs
index 61aa30aa3917c..90126866cd500 100644
--- a/compiler/rustc_borrowck/src/type_check/liveness/trace.rs
+++ b/compiler/rustc_borrowck/src/type_check/liveness/trace.rs
@@ -6,7 +6,7 @@ use rustc_infer::infer::canonical::QueryRegionConstraints;
use rustc_infer::traits::TraitErrors;
use rustc_middle::mir::{BasicBlock, Body, ConstraintCategory, Local, Location};
use rustc_middle::traits::query::DropckOutlivesResult;
-use rustc_middle::ty::{GenericArg, Ty, TypeVisitable, TypeVisitableExt};
+use rustc_middle::ty::{Ty, TyCtxt, TypeVisitable, TypeVisitableExt};
use rustc_mir_dataflow::impls::MaybeInitializedPlaces;
use rustc_mir_dataflow::move_paths::{HasMoveData, MoveData, MovePathIndex};
use rustc_mir_dataflow::points::{DenseLocationMap, PointIndex};
@@ -553,8 +553,17 @@ impl<'tcx> LivenessContext<'_, '_, 'tcx> {
/// points `live_at`.
fn add_use_live_facts_for(&mut self, value: Ty<'tcx>, live_at: &IntervalSet
) {
debug!("add_use_live_facts_for(value={:?})", value);
- Self::record_region_variance(self.typeck, value.into());
- Self::make_all_regions_live(self.location_map, self.typeck, value.into(), live_at);
+ Self::make_all_regions_live(self.location_map, self.typeck, value, live_at);
+
+ // When using `-Zpolonius=next`, we also record the variance of regions in this live type.
+ if let Some(polonius_context) = self.typeck.polonius_context.as_mut() {
+ record_live_region_variance(
+ self.typeck.infcx.tcx,
+ &mut polonius_context.live_region_variances,
+ self.typeck.universal_regions,
+ value,
+ );
+ }
}
/// Some variable with type `live_ty` is "drop live" at `location`
@@ -595,9 +604,6 @@ impl<'tcx> LivenessContext<'_, '_, 'tcx> {
}
}
- // Since the entire dropped local is live, record the variance of its regions.
- Self::record_region_variance(self.typeck, dropped_ty.into());
-
// All things in the `outlives` array may be touched by
// the destructor and must be live at this point.
for &kind in &drop_data.dropck_result.kinds {
@@ -610,19 +616,16 @@ impl<'tcx> LivenessContext<'_, '_, 'tcx> {
self.typeck.polonius_facts,
);
}
- }
- /// `live_kind` is the type of a (use- or drop-) live local.
- /// Record the variance of any region(s) appearing in it for Polonius. Does
- /// nothing if Polonius is not active.
- fn record_region_variance(typeck: &mut TypeChecker<'_, 'tcx>, live_kind: GenericArg<'tcx>) {
- // When using `-Zpolonius=next`, we record the variance of each live region.
- if let Some(polonius_context) = typeck.polonius_context.as_mut() {
+ // For polonius: since the local is drop live, record the variance of the regions in its
+ // type, not the ones in the type's live components seen in the dropck results above. See
+ // issue #160670.
+ if let Some(polonius_context) = self.typeck.polonius_context.as_mut() {
record_live_region_variance(
- typeck.infcx.tcx,
+ self.typeck.infcx.tcx,
&mut polonius_context.live_region_variances,
- typeck.universal_regions,
- live_kind,
+ self.typeck.universal_regions,
+ dropped_ty,
);
}
}
@@ -630,7 +633,7 @@ impl<'tcx> LivenessContext<'_, '_, 'tcx> {
fn make_all_regions_live(
location_map: &DenseLocationMap,
typeck: &mut TypeChecker<'_, 'tcx>,
- value: GenericArg<'tcx>,
+ value: impl TypeVisitable>,
live_at: &IntervalSet,
) {
debug!("make_all_regions_live(value={:?})", value);
@@ -647,7 +650,6 @@ impl<'tcx> LivenessContext<'_, '_, 'tcx> {
typeck.constraints.liveness_constraints.add_points(live_region_vid, live_at);
},
});
- Self::record_region_variance(typeck, value);
}
}
diff --git a/compiler/rustc_codegen_llvm/src/debuginfo/metadata.rs b/compiler/rustc_codegen_llvm/src/debuginfo/metadata.rs
index e0fc60e1a9b7a..735dd0fbaba10 100644
--- a/compiler/rustc_codegen_llvm/src/debuginfo/metadata.rs
+++ b/compiler/rustc_codegen_llvm/src/debuginfo/metadata.rs
@@ -5,7 +5,7 @@ use std::path::PathBuf;
use std::{assert_matches, iter, ptr};
use libc::{c_longlong, c_uint};
-use rustc_abi::{Align, Layout, NumScalableVectors, Size};
+use rustc_abi::{Align, Endian, Layout, NumScalableVectors, Size};
use rustc_codegen_ssa::debuginfo::type_names::{VTableNameKind, cpp_like_debuginfo};
use rustc_codegen_ssa::traits::*;
use rustc_hir::def::{CtorKind, DefKind};
@@ -21,7 +21,7 @@ use rustc_span::{
DUMMY_SP, FileName, RemapPathScopeComponents, SourceFile, Span, Symbol, bug, hygiene,
};
use rustc_symbol_mangling::typeid_for_trait_ref;
-use rustc_target::spec::{Arch, DebuginfoKind};
+use rustc_target::spec::{Arch, DebuginfoKind, HasTargetSpec};
use smallvec::smallvec;
use tracing::{debug, instrument};
@@ -693,33 +693,22 @@ impl MsvcBasicName for ty::UintTy {
}
}
-impl MsvcBasicName for ty::FloatTy {
- fn msvc_basic_name(self) -> &'static str {
- // FIXME(f128): `f128` has no MSVC representation. We could improve the debuginfo.
- // See:
- match self {
- ty::FloatTy::F16 => {
- bug!("`f16` should have been handled in `build_basic_type_di_node`")
- }
- ty::FloatTy::F32 => "float",
- ty::FloatTy::F64 => "double",
- ty::FloatTy::F128 => "fp128",
- }
- }
-}
-
-fn build_cpp_f16_di_node<'ll, 'tcx>(cx: &CodegenCx<'ll, 'tcx>) -> DINodeCreationResult<'ll> {
- // MSVC has no native support for `f16`. Instead, emit `struct f16 { bits: u16 }` to allow the
- // `f16`'s value to be displayed using a Natvis visualiser in `intrinsic.natvis`.
- let float_ty = cx.tcx.types.f16;
- let bits_ty = cx.tcx.types.u16;
- let def_location = if cx.sess().opts.unstable_opts.debug_info_type_line_numbers {
- match float_ty.kind() {
- ty::Adt(def, _) => Some(file_metadata_from_def_id(cx, Some(def.did()))),
- _ => None,
- }
+/// `float_ty` must be a [`ty::Float`] and `bits_ty` must be a [`ty::Uint`].
+/// `cx.size_of(bits_ty) * bits_names.len()` must equal `cx.size_of(float_ty)`.
+fn build_cpp_float_struct_di_node<'ll, 'tcx>(
+ cx: &CodegenCx<'ll, 'tcx>,
+ float_ty: Ty<'tcx>,
+ bits_ty: Ty<'tcx>,
+ bits_names: &[&str],
+) -> DINodeCreationResult<'ll> {
+ debug_assert!(matches!(bits_ty.kind(), ty::Uint(_)));
+ debug_assert_eq!(cx.size_of(bits_ty) * (bits_names.len() as u64), cx.size_of(float_ty));
+ // MSVC has no native support for `f16` or `f128`. Instead, emit a struct containing the bits as
+ // field(s) to allow the value to be displayed using a Natvis visualiser in `intrinsic.natvis`.
+ let name = if let ty::Float(f) = float_ty.kind() {
+ f.name_str()
} else {
- None
+ bug!("{float_ty:?} was not a float");
};
type_map::build_type_with_children(
cx,
@@ -727,32 +716,33 @@ fn build_cpp_f16_di_node<'ll, 'tcx>(cx: &CodegenCx<'ll, 'tcx>) -> DINodeCreation
cx,
Stub::Struct,
UniqueTypeId::for_ty(cx.tcx, float_ty),
- "f16",
- def_location,
+ name,
+ None,
cx.size_and_align_of(float_ty),
NO_SCOPE_METADATA,
DIFlags::FlagZero,
),
// Fields:
|cx, float_di_node| {
- let def_id = if cx.sess().opts.unstable_opts.debug_info_type_line_numbers {
- match bits_ty.kind() {
- ty::Adt(def, _) => Some(def.did()),
- _ => None,
- }
- } else {
- None
- };
- smallvec![build_field_di_node(
- cx,
- float_di_node,
- "bits",
- cx.layout_of(bits_ty),
- Size::ZERO,
- DIFlags::FlagZero,
- type_di_node(cx, bits_ty),
- def_id,
- )]
+ let bits_layout = cx.layout_of(bits_ty);
+ let bits_node = type_di_node(cx, bits_ty);
+ bits_names
+ .iter()
+ .copied()
+ .enumerate()
+ .map(|(i, field_name)| {
+ build_field_di_node(
+ cx,
+ float_di_node,
+ field_name,
+ bits_layout,
+ bits_layout.size * (i as u64),
+ DIFlags::FlagZero,
+ bits_node,
+ None,
+ )
+ })
+ .collect()
},
NO_GENERICS,
)
@@ -784,9 +774,20 @@ fn build_basic_type_di_node<'ll, 'tcx>(
ty::Int(int_ty) if cpp_like_debuginfo => (int_ty.msvc_basic_name(), DW_ATE_signed),
ty::Uint(uint_ty) if cpp_like_debuginfo => (uint_ty.msvc_basic_name(), DW_ATE_unsigned),
ty::Float(ty::FloatTy::F16) if cpp_like_debuginfo => {
- return build_cpp_f16_di_node(cx);
+ return build_cpp_float_struct_di_node(cx, t, cx.tcx.types.u16, &["bits"]);
+ }
+ ty::Float(ty::FloatTy::F128) if cpp_like_debuginfo => {
+ // All MSVC architectures are little endian.
+ assert_eq!(cx.target_spec().endian, Endian::Little);
+ return build_cpp_float_struct_di_node(
+ cx,
+ t,
+ cx.tcx.types.u64,
+ &["low_bits", "high_bits"],
+ );
}
- ty::Float(float_ty) if cpp_like_debuginfo => (float_ty.msvc_basic_name(), DW_ATE_float),
+ ty::Float(ty::FloatTy::F32) if cpp_like_debuginfo => ("float", DW_ATE_float),
+ ty::Float(ty::FloatTy::F64) if cpp_like_debuginfo => ("double", DW_ATE_float),
ty::Int(int_ty) => (int_ty.name_str(), DW_ATE_signed),
ty::Uint(uint_ty) => (uint_ty.name_str(), DW_ATE_unsigned),
ty::Float(float_ty) => (float_ty.name_str(), DW_ATE_float),
diff --git a/compiler/rustc_expand/src/expand.rs b/compiler/rustc_expand/src/expand.rs
index fc86bdfcf4f18..51c517ee24a66 100644
--- a/compiler/rustc_expand/src/expand.rs
+++ b/compiler/rustc_expand/src/expand.rs
@@ -1748,22 +1748,10 @@ impl InvocationCollectorNode for ast::GenericParam {
walk_flat_map_generic_param(collector, self)
}
fn as_target(&self) -> Target {
- let mut has_default = false;
- Target::GenericParam {
- kind: match &self.kind {
- rustc_ast::GenericParamKind::Lifetime => {
- rustc_attr_ir::target::GenericParamKind::Lifetime
- }
- rustc_ast::GenericParamKind::Type { default } => {
- has_default = default.is_some();
- rustc_attr_ir::target::GenericParamKind::Type
- }
- rustc_ast::GenericParamKind::Const { default, .. } => {
- has_default = default.is_some();
- rustc_attr_ir::target::GenericParamKind::Const
- }
- },
- has_default,
+ match self.kind {
+ rustc_ast::GenericParamKind::Lifetime => Target::LifetimeParam,
+ rustc_ast::GenericParamKind::Type { .. } => Target::TypeParam,
+ rustc_ast::GenericParamKind::Const { .. } => Target::ConstParam,
}
}
}
diff --git a/compiler/rustc_hir/src/target_impls.rs b/compiler/rustc_hir/src/target_impls.rs
index b71a046958b57..f98a6caaa5e66 100644
--- a/compiler/rustc_hir/src/target_impls.rs
+++ b/compiler/rustc_hir/src/target_impls.rs
@@ -1,6 +1,6 @@
//! Implements conversions from HIR types to Target.
-use rustc_attr_ir::target::{AssocCtxt, GenericParamKind, MethodKind, Target};
+use rustc_attr_ir::target::{AssocCtxt, MethodKind, Target};
use crate::def::DefKind;
use crate::{self as hir, ItemKind, TraitItemKind};
@@ -18,17 +18,9 @@ impl From<&hir::ForeignItem<'_>> for Target {
impl From<&hir::GenericParam<'_>> for Target {
fn from(generic_param: &hir::GenericParam<'_>) -> Target {
match generic_param.kind {
- hir::GenericParamKind::Type { default, .. } => Target::GenericParam {
- kind: GenericParamKind::Type,
- has_default: default.is_some(),
- },
- hir::GenericParamKind::Lifetime { .. } => {
- Target::GenericParam { kind: GenericParamKind::Lifetime, has_default: false }
- }
- hir::GenericParamKind::Const { default, .. } => Target::GenericParam {
- kind: GenericParamKind::Const,
- has_default: default.is_some(),
- },
+ hir::GenericParamKind::Type { .. } => Target::TypeParam,
+ hir::GenericParamKind::Lifetime { .. } => Target::LifetimeParam,
+ hir::GenericParamKind::Const { .. } => Target::ConstParam,
}
}
}
diff --git a/compiler/rustc_passes/src/check_attr.rs b/compiler/rustc_passes/src/check_attr.rs
index 79987b86385ef..f6bd780802401 100644
--- a/compiler/rustc_passes/src/check_attr.rs
+++ b/compiler/rustc_passes/src/check_attr.rs
@@ -844,7 +844,9 @@ impl<'tcx> CheckAttrVisitor<'tcx> {
| Target::ForeignFn
| Target::ForeignStatic
| Target::ForeignTy
- | Target::GenericParam { .. }
+ | Target::TypeParam
+ | Target::LifetimeParam
+ | Target::ConstParam
| Target::MacroDef
| Target::PatField
| Target::ExprField
diff --git a/compiler/rustc_passes/src/dead.rs b/compiler/rustc_passes/src/dead.rs
index de5442d83910c..1800d4fc6c25e 100644
--- a/compiler/rustc_passes/src/dead.rs
+++ b/compiler/rustc_passes/src/dead.rs
@@ -1163,6 +1163,57 @@ impl<'tcx> DeadVisitor<'tcx> {
(level_spec.level(), level_spec.lint_id())
}
+ fn fulfill_dead_code_expectations(&self, def_id: LocalDefId, include: bool) {
+ let fulfill_if_expected = |node: DefId| {
+ // Only consider local, dead symbols where lint level carries an expectation
+ if let Some(node) = node.as_local()
+ && !self.live_symbols.contains(&node)
+ && let (_, Some(expectation)) = self.def_lint_level_plus(node)
+ {
+ // Same mechanism as LintContext::fulfill_expectation.
+ self.tcx
+ .dcx()
+ .struct_expect(
+ "this is a dummy diagnostic, to submit and store an expectation",
+ expectation.into(),
+ )
+ .emit();
+ }
+ };
+
+ if include {
+ fulfill_if_expected(def_id.to_def_id());
+ }
+
+ match self.tcx.def_kind(def_id) {
+ DefKind::Struct | DefKind::Union | DefKind::Enum => {
+ let adt = self.tcx.adt_def(def_id);
+ for variant in adt.variants() {
+ if variant.def_id != def_id.to_def_id() {
+ fulfill_if_expected(variant.def_id);
+ }
+ for field in &variant.fields {
+ fulfill_if_expected(field.did);
+ }
+ }
+ }
+ DefKind::Variant => {
+ let parent_enum = self.tcx.local_parent(def_id);
+ let variant = self.tcx.adt_def(parent_enum).variant_with_id(def_id.to_def_id());
+ //Check to see if fields carry expectation
+ for field in &variant.fields {
+ fulfill_if_expected(field.did);
+ }
+ }
+ DefKind::Trait => {
+ for &assoc_def_id in self.tcx.associated_item_def_ids(def_id) {
+ fulfill_if_expected(assoc_def_id);
+ }
+ }
+ _ => {}
+ }
+ }
+
fn dead_code_pub_in_binary_note(&self) -> Option {
self.target_lint.name.eq(DEAD_CODE_PUB_IN_BINARY.name).then_some(DeadCodePubInBinaryNote)
}
@@ -1469,10 +1520,12 @@ fn lint_dead_codes<'tcx>(
if !live_symbols.contains(&item.owner_id.def_id) {
let parent = tcx.local_parent(item.owner_id.def_id);
if parent != module.to_local_def_id() && !live_symbols.contains(&parent) {
- // We already have diagnosed something.
+ // We already have diagnosed something, but check parent's field for #[expect]
+ visitor.fulfill_dead_code_expectations(item.owner_id.def_id, true);
continue;
}
visitor.check_definition(item.owner_id.def_id);
+ visitor.fulfill_dead_code_expectations(item.owner_id.def_id, false);
continue;
}
@@ -1486,6 +1539,7 @@ fn lint_dead_codes<'tcx>(
// Record to group diagnostics.
let level_plus = visitor.def_lint_level_plus(def_id);
dead_variants.push(DeadItem { def_id, name: variant.name, level_plus });
+ visitor.fulfill_dead_code_expectations(def_id, false);
continue;
}
diff --git a/compiler/rustc_target/src/callconv/sparc.rs b/compiler/rustc_target/src/callconv/sparc.rs
index 71af508915e59..dc4d4a7f51225 100644
--- a/compiler/rustc_target/src/callconv/sparc.rs
+++ b/compiler/rustc_target/src/callconv/sparc.rs
@@ -1,46 +1,35 @@
-use rustc_abi::{HasDataLayout, Size, TyAbiInterface};
+use rustc_abi::{BackendRepr, Float, HasDataLayout, Primitive, TyAbiInterface};
-use crate::callconv::{ArgAbi, FnAbi, Reg, Uniform};
+use crate::callconv::{ArgAbi, FnAbi};
-fn classify_ret(cx: &C, ret: &mut ArgAbi<'_, Ty>, offset: &mut Size)
-where
- C: HasDataLayout,
-{
- if !ret.layout.is_aggregate() {
- ret.extend_integer_width_to(32);
+fn classify<'a, Ty>(arg: &mut ArgAbi<'a, Ty>) {
+ if arg.layout.is_aggregate() {
+ arg.make_indirect();
+ } else if let BackendRepr::Scalar(scalar) = arg.layout.backend_repr
+ && scalar.primitive() == Primitive::Float(Float::F128)
+ {
+ // Always pass f128 indirectly.
+ arg.make_indirect();
} else {
- ret.make_indirect();
- *offset += cx.data_layout().pointer_size();
+ arg.extend_integer_width_to(32);
}
}
-fn classify_arg<'a, Ty, C>(cx: &C, arg: &mut ArgAbi<'a, Ty>, offset: &mut Size)
+fn classify_arg<'a, Ty, C>(cx: &C, arg: &mut ArgAbi<'a, Ty>)
where
Ty: TyAbiInterface<'a, C> + Copy,
C: HasDataLayout,
{
if !arg.layout.is_sized() {
- // FIXME: Update offset?
// Not touching this...
return;
}
- let dl = cx.data_layout();
if arg.layout.pass_indirectly_in_non_rustic_abis(cx) {
arg.make_indirect();
- *offset += dl.pointer_size();
return;
}
- let size = arg.layout.size;
- let align = arg.layout.align.abi.max(dl.i32_align).min(dl.i64_align);
-
- if arg.layout.is_aggregate() {
- let pad_i32 = u8::from(!offset.is_aligned(align));
- arg.cast_to_and_pad_i32(Uniform::new(Reg::i32(), size), pad_i32);
- } else {
- arg.extend_integer_width_to(32);
- }
- *offset = offset.align_to(align) + size.align_to(align);
+ classify(arg);
}
pub(crate) fn compute_abi_info<'a, Ty, C>(cx: &C, fn_abi: &mut FnAbi<'a, Ty>)
@@ -48,15 +37,17 @@ where
Ty: TyAbiInterface<'a, C> + Copy,
C: HasDataLayout,
{
- let mut offset = Size::ZERO;
if !fn_abi.ret.is_ignore() {
- classify_ret(cx, &mut fn_abi.ret, &mut offset);
+ classify(&mut fn_abi.ret);
}
for arg in fn_abi.args.iter_mut() {
if arg.is_ignore() {
+ if arg.layout.is_zst() {
+ arg.make_indirect_from_ignore();
+ }
continue;
}
- classify_arg(cx, arg, &mut offset);
+ classify_arg(cx, arg);
}
}
diff --git a/library/core/src/ffi/c_str.rs b/library/core/src/ffi/c_str.rs
index e5b1f8088a5bf..c851b56c20bc8 100644
--- a/library/core/src/ffi/c_str.rs
+++ b/library/core/src/ffi/c_str.rs
@@ -6,6 +6,7 @@ use crate::ffi::c_char;
use crate::intrinsics::const_eval_select;
use crate::iter::FusedIterator;
use crate::marker::PhantomData;
+use crate::num::niche_types::UsizeNoHighBitMinusOne;
use crate::ptr::NonNull;
use crate::slice::memchr;
use crate::{fmt, ops, range, slice, str};
@@ -262,7 +263,12 @@ impl CStr {
// means the call to `from_bytes_with_nul_unchecked` is correct.
//
// The cast from c_char to u8 is ok because a c_char is always one byte.
- unsafe { Self::from_bytes_with_nul_unchecked(slice::from_raw_parts(ptr.cast(), len + 1)) }
+ unsafe {
+ Self::from_bytes_with_nul_unchecked(slice::from_raw_parts(
+ ptr.cast(),
+ len.as_inner() + 1,
+ ))
+ }
}
/// Creates a C string wrapper from a byte slice with any number of nuls.
@@ -750,9 +756,9 @@ const impl AsRef for CStr {
#[inline]
#[unstable(feature = "cstr_internals", issue = "none")]
#[rustc_allow_const_fn_unstable(const_eval_select)]
-const unsafe fn strlen(ptr: *const c_char) -> usize {
+const unsafe fn strlen(ptr: *const c_char) -> UsizeNoHighBitMinusOne {
const_eval_select!(
- @capture { s: *const c_char = ptr } -> usize:
+ @capture { s: *const c_char = ptr } -> UsizeNoHighBitMinusOne:
if const {
let mut len = 0;
@@ -761,15 +767,16 @@ const unsafe fn strlen(ptr: *const c_char) -> usize {
len += 1;
}
- len
+ UsizeNoHighBitMinusOne::new(len).unwrap()
} else {
unsafe extern "C" {
/// Provided by libc or compiler_builtins.
fn strlen(s: *const c_char) -> usize;
}
- // SAFETY: Outer caller has provided a pointer to a valid C string.
- unsafe { strlen(s) }
+ // SAFETY: Outer caller has provided a pointer to a valid C string,
+ // and its length is within bounds.
+ unsafe { UsizeNoHighBitMinusOne::new_unchecked(strlen(s)) }
}
)
}
@@ -841,7 +848,7 @@ impl Iterator for Bytes<'_> {
#[inline]
fn count(self) -> usize {
// SAFETY: We always hold a valid pointer to a C string
- unsafe { strlen(self.ptr.as_ptr().cast()) }
+ unsafe { strlen(self.ptr.as_ptr().cast()) }.as_inner()
}
}
diff --git a/library/core/src/num/complex.rs b/library/core/src/num/complex.rs
index 66126c52fadad..c6a56285cdfb1 100644
--- a/library/core/src/num/complex.rs
+++ b/library/core/src/num/complex.rs
@@ -1,4 +1,5 @@
-use crate::ops::{Add, Neg, Sub};
+use crate::num::imp::libm::complex::*;
+use crate::ops::{Add, Div, Mul, Neg, Sub};
/// A complex number.
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
@@ -91,3 +92,54 @@ impl> Sub for Complex {
Complex::new(self.re - rhs, self.im)
}
}
+
+macro_rules! impl_complex_mul_div {
+ ($ty:ty, $mul:ident, $div:ident) => {
+ #[unstable(feature = "complex_numbers", issue = "154023")]
+ impl Mul for Complex<$ty> {
+ type Output = Self;
+
+ #[inline]
+ fn mul(self, rhs: Self) -> Self::Output {
+ let Complex { re: a, im: b } = self;
+ let Complex { re: c, im: d } = rhs;
+
+ let ac = a * c;
+ let bd = b * d;
+ let ad = a * d;
+ let bc = b * c;
+
+ let z = Complex::new(ac - bd, ad + bc);
+
+ // Only call the libcall when both components are NaN.
+ //
+ // The naive algorithm would return NaN + NaNi for an input like
+ // (1 + 0i) * (inf + infi). The libcall instead returns inf + infi.
+ //
+ // We duplicate the fast path here so that it can be inlined. We use a libcall
+ // for the NaN correction to reduce the size of `core`.
+ if z.re.is_nan() && z.im.is_nan() {
+ crate::hint::cold_path();
+ $mul(a, b, c, d)
+ } else {
+ z
+ }
+ }
+ }
+
+ #[unstable(feature = "complex_numbers", issue = "154023")]
+ impl Div for Complex<$ty> {
+ type Output = Self;
+
+ #[inline]
+ fn div(self, rhs: Self) -> Self::Output {
+ $div(self.re, self.im, rhs.re, rhs.im)
+ }
+ }
+ };
+}
+
+impl_complex_mul_div!(f16, __rust_mulhc3, __rust_divhc3);
+impl_complex_mul_div!(f32, __mulsc3, __divsc3);
+impl_complex_mul_div!(f64, __muldc3, __divdc3);
+impl_complex_mul_div!(f128, __rust_multc3, __rust_divtc3);
diff --git a/library/core/src/num/imp/libm.rs b/library/core/src/num/imp/libm.rs
index a8d6bdc0b5d7c..6ce02ad60a5df 100644
--- a/library/core/src/num/imp/libm.rs
+++ b/library/core/src/num/imp/libm.rs
@@ -76,6 +76,27 @@ unsafe extern "C" {
pub(crate) safe fn truncf16(x: f16) -> f16;
}
+/// These symbols are always provided by compiler-builtins.
+pub(crate) mod complex {
+ use crate::num::Complex;
+
+ unsafe extern "C" {
+ pub(crate) safe fn __mulsc3(a: f32, b: f32, c: f32, d: f32) -> Complex;
+ pub(crate) safe fn __muldc3(a: f64, b: f64, c: f64, d: f64) -> Complex;
+
+ pub(crate) safe fn __divsc3(a: f32, b: f32, c: f32, d: f32) -> Complex;
+ pub(crate) safe fn __divdc3(a: f64, b: f64, c: f64, d: f64) -> Complex;
+ }
+
+ unsafe extern "Rust" {
+ pub(crate) safe fn __rust_mulhc3(a: f16, b: f16, c: f16, d: f16) -> Complex;
+ pub(crate) safe fn __rust_multc3(a: f128, b: f128, c: f128, d: f128) -> Complex;
+
+ pub(crate) safe fn __rust_divhc3(a: f16, b: f16, c: f16, d: f16) -> Complex;
+ pub(crate) safe fn __rust_divtc3(a: f128, b: f128, c: f128, d: f128) -> Complex;
+ }
+}
+
/// These symbols will be available when `std` is available, and on many no-std platforms. However,
/// since this isn't a guarantee, we cannot rely on them for stable implementations.
pub(crate) mod likely_available {
diff --git a/library/core/src/num/niche_types.rs b/library/core/src/num/niche_types.rs
index df1cdf0e65fa1..37037d8145fb0 100644
--- a/library/core/src/num/niche_types.rs
+++ b/library/core/src/num/niche_types.rs
@@ -111,6 +111,7 @@ const impl Default for Nanoseconds {
}
const HALF_USIZE: usize = usize::MAX >> 1;
+const HALF_USIZE_MINUS_ONE: usize = HALF_USIZE - 1;
define_valid_range_type! {
pub struct NonZeroU8Inner(u8 is 1..);
@@ -126,6 +127,7 @@ define_valid_range_type! {
pub struct NonZeroI128Inner(i128 is ..0 | 1..);
pub struct UsizeNoHighBit(usize is 0..=HALF_USIZE);
+ pub struct UsizeNoHighBitMinusOne(usize is 0..=HALF_USIZE_MINUS_ONE);
pub struct NonZeroUsizeInner(usize is 1..);
pub struct NonZeroIsizeInner(isize is ..0 | 1..);
diff --git a/library/core/src/num/nonzero.rs b/library/core/src/num/nonzero.rs
index 5d8dee0b9378a..0563c225f7e0b 100644
--- a/library/core/src/num/nonzero.rs
+++ b/library/core/src/num/nonzero.rs
@@ -1414,6 +1414,40 @@ macro_rules! nonzero_integer {
#[stable(feature = "nonzero_parse", since = "1.35.0")]
impl FromStr for NonZero<$Int> {
type Err = ParseIntError;
+
+ /// Parses a non-zero integer from a string slice with decimal digits.
+ ///
+ /// The characters are expected to be an optional
+ #[doc = sign_dependent_expr!{
+ $signedness ?
+ if signed {
+ " `+` or `-` "
+ }
+ if unsigned {
+ " `+` "
+ }
+ }]
+ /// sign followed by only digits. Leading and trailing non-digit characters (including
+ /// whitespace) represent an error. Underscores (which are accepted in Rust literals)
+ /// also represent an error.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// use std::num::NonZero;
+ /// use std::str::FromStr;
+ ///
+ #[doc = concat!("assert_eq!(NonZero::<", stringify!($Int), ">::from_str(\"+10\"), Ok(NonZero::new(10).unwrap()));")]
+ /// ```
+ ///
+ /// Trailing space returns error:
+ ///
+ /// ```
+ /// use std::num::NonZero;
+ /// use std::str::FromStr;
+ ///
+ #[doc = concat!("assert!(NonZero::<", stringify!($Int), ">::from_str(\"1 \").is_err());")]
+ /// ```
fn from_str(src: &str) -> Result {
Self::from_str_radix(src, 10)
}
diff --git a/library/core/src/str/mod.rs b/library/core/src/str/mod.rs
index db52d3bada4c8..cc96e51d83393 100644
--- a/library/core/src/str/mod.rs
+++ b/library/core/src/str/mod.rs
@@ -2912,7 +2912,7 @@ impl str {
/// Converts this string to its ASCII upper case equivalent in-place.
///
/// ASCII letters 'a' to 'z' are mapped to 'A' to 'Z',
- /// but non-ASCII letters are unchanged.
+ /// but all other characters are unchanged.
///
/// To return a new uppercased value without modifying the existing one, use
/// [`to_ascii_uppercase()`].
@@ -2940,7 +2940,7 @@ impl str {
/// Converts this string to its ASCII lower case equivalent in-place.
///
/// ASCII letters 'A' to 'Z' are mapped to 'a' to 'z',
- /// but non-ASCII letters are unchanged.
+ /// but all other characters are unchanged.
///
/// To return a new lowercased value without modifying the existing one, use
/// [`to_ascii_lowercase()`].
diff --git a/library/coretests/tests/num/complex.rs b/library/coretests/tests/num/complex.rs
index c22c5b9575b3d..ea7bff0acc7de 100644
--- a/library/coretests/tests/num/complex.rs
+++ b/library/coretests/tests/num/complex.rs
@@ -73,3 +73,63 @@ fn complex_negation() {
assert_eq!(-Complex::new(1.0, -2.0), Complex::new(-1.0, 2.0));
assert_eq!(-Complex::new(1.0, f32::INFINITY), Complex::new(-1.0, f32::NEG_INFINITY),);
}
+
+#[test]
+fn complex_multiplication() {
+ #[cfg(target_has_reliable_f16)]
+ assert_eq!(Complex::new(1.0f16, 2.0) * Complex::new(3.0, 4.0), Complex::new(-5.0, 10.0));
+ assert_eq!(Complex::new(1.0f32, 2.0) * Complex::new(3.0, 4.0), Complex::new(-5.0, 10.0));
+ assert_eq!(Complex::new(1.0f64, 2.0) * Complex::new(3.0, 4.0), Complex::new(-5.0, 10.0));
+ #[cfg(target_has_reliable_f128)]
+ assert_eq!(Complex::new(1.0f128, 2.0) * Complex::new(3.0, 4.0), Complex::new(-5.0, 10.0));
+
+ // The naive algorithm would return NaN + NaNi for these inputs, but the libcall handles it.
+ #[cfg(target_has_reliable_f16)]
+ assert_eq!(
+ Complex::new(1.0, 0.0) * Complex::new(f16::INFINITY, f16::INFINITY),
+ Complex::new(f16::INFINITY, f16::INFINITY)
+ );
+ assert_eq!(
+ Complex::new(1.0, 0.0) * Complex::new(f32::INFINITY, f32::INFINITY),
+ Complex::new(f32::INFINITY, f32::INFINITY)
+ );
+ assert_eq!(
+ Complex::new(1.0, 0.0) * Complex::new(f64::INFINITY, f64::INFINITY),
+ Complex::new(f64::INFINITY, f64::INFINITY)
+ );
+ #[cfg(target_has_reliable_f128)]
+ assert_eq!(
+ Complex::new(1.0, 0.0) * Complex::new(f128::INFINITY, f128::INFINITY),
+ Complex::new(f128::INFINITY, f128::INFINITY)
+ );
+}
+
+#[test]
+fn div() {
+ #[cfg(target_has_reliable_f16)]
+ assert_eq!(Complex::new(2.0f16, 11.0) / Complex::new(2.0, 1.0), Complex::new(3.0, 4.0));
+ assert_eq!(Complex::new(2.0f32, 11.0) / Complex::new(2.0, 1.0), Complex::new(3.0, 4.0));
+ assert_eq!(Complex::new(2.0f64, 11.0) / Complex::new(2.0, 1.0), Complex::new(3.0, 4.0));
+ #[cfg(target_has_reliable_f128)]
+ assert_eq!(Complex::new(2.0f128, 11.0) / Complex::new(2.0, 1.0), Complex::new(3.0, 4.0));
+
+ // The naive algorithm would return NaN + NaNi for these inputs, but the libcall handles it.
+ #[cfg(target_has_reliable_f16)]
+ assert_eq!(
+ Complex::new(f16::INFINITY, 0.0) / Complex::new(1.0, 1.0),
+ Complex::new(f16::INFINITY, f16::NEG_INFINITY)
+ );
+ assert_eq!(
+ Complex::new(f32::INFINITY, 0.0) / Complex::new(1.0, 1.0),
+ Complex::new(f32::INFINITY, f32::NEG_INFINITY)
+ );
+ assert_eq!(
+ Complex::new(f64::INFINITY, 0.0) / Complex::new(1.0, 1.0),
+ Complex::new(f64::INFINITY, f64::NEG_INFINITY)
+ );
+ #[cfg(target_has_reliable_f128)]
+ assert_eq!(
+ Complex::new(f128::INFINITY, 0.0) / Complex::new(1.0, 1.0),
+ Complex::new(f128::INFINITY, f128::NEG_INFINITY)
+ );
+}
diff --git a/library/stdarch/Cargo.lock b/library/stdarch/Cargo.lock
index 9923b630cd5bb..9ec3227f49e7d 100644
--- a/library/stdarch/Cargo.lock
+++ b/library/stdarch/Cargo.lock
@@ -217,12 +217,6 @@ dependencies = [
"syn",
]
-[[package]]
-name = "diff"
-version = "0.1.13"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "56254986775e3233ffa9c4d7d3faaf6d36a2c09d30b20687e9f88bc8bafc16c8"
-
[[package]]
name = "either"
version = "1.15.0"
@@ -400,7 +394,6 @@ name = "intrinsic-test"
version = "0.1.0"
dependencies = [
"clap",
- "diff",
"itertools",
"log",
"pretty_env_logger",
@@ -408,7 +401,6 @@ dependencies = [
"rayon",
"regex",
"serde",
- "serde-xml-rs",
"serde_json",
]
@@ -726,18 +718,6 @@ dependencies = [
"serde_derive",
]
-[[package]]
-name = "serde-xml-rs"
-version = "0.8.2"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "cc2215ce3e6a77550b80a1c37251b7d294febaf42e36e21b7b411e0bf54d540d"
-dependencies = [
- "log",
- "serde",
- "thiserror",
- "xml",
-]
-
[[package]]
name = "serde_core"
version = "1.0.228"
@@ -935,26 +915,6 @@ dependencies = [
"winapi-util",
]
-[[package]]
-name = "thiserror"
-version = "2.0.18"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "4288b5bcbc7920c07a1149a35cf9590a2aa808e0bc1eafaade0b80947865fbc4"
-dependencies = [
- "thiserror-impl",
-]
-
-[[package]]
-name = "thiserror-impl"
-version = "2.0.18"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "ebc4ee7f67670e9b64d05fa4253e753e016c6c95ff35b89b7941d6b856dec1d5"
-dependencies = [
- "proc-macro2",
- "quote",
- "syn",
-]
-
[[package]]
name = "unicode-ident"
version = "1.0.24"
@@ -1169,12 +1129,6 @@ dependencies = [
"wasmparser 0.244.0",
]
-[[package]]
-name = "xml"
-version = "1.2.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "b8aa498d22c9bbaf482329839bc5620c46be275a19a812e9a22a2b07529a642a"
-
[[package]]
name = "yaml-rust"
version = "0.4.5"
diff --git a/library/stdarch/crates/core_arch/Cargo.toml b/library/stdarch/crates/core_arch/Cargo.toml
index 670447a2d5a8b..ab8b9bcd9fcef 100644
--- a/library/stdarch/crates/core_arch/Cargo.toml
+++ b/library/stdarch/crates/core_arch/Cargo.toml
@@ -7,9 +7,7 @@ authors = [
"Gonzalo Brito Gadeschi ",
]
description = "`core::arch` - Rust's core library architecture-specific intrinsics."
-homepage = "https://github.com/rust-lang/stdarch"
repository = "https://github.com/rust-lang/stdarch"
-readme = "README.md"
keywords = ["core", "simd", "arch", "intrinsics"]
categories = ["hardware-support", "no-std"]
license = "MIT OR Apache-2.0"
diff --git a/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs b/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs
index 4fc46a3ba39e8..094b13ca8023a 100644
--- a/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -70649,7 +70649,7 @@ pub fn vzip_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t {
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(zip1)
@@ -70679,7 +70679,7 @@ pub fn vzipq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t {
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(zip1)
@@ -70714,7 +70714,7 @@ pub fn vzipq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t {
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(zip1)
@@ -70752,7 +70752,7 @@ pub fn vzipq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t {
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(zip1)
@@ -70805,7 +70805,7 @@ pub fn vzipq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t {
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(zip1)
@@ -70835,7 +70835,7 @@ pub fn vzipq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t {
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(zip1)
@@ -70870,7 +70870,7 @@ pub fn vzipq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t {
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(zip1)
@@ -70900,7 +70900,7 @@ pub fn vzipq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t {
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(zip1)
@@ -70935,7 +70935,7 @@ pub fn vzipq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t {
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(zip1)
@@ -70973,7 +70973,7 @@ pub fn vzipq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t {
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(zip1)
@@ -71026,7 +71026,7 @@ pub fn vzipq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t {
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(zip1)
@@ -71056,7 +71056,7 @@ pub fn vzipq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t {
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(zip1)
@@ -71091,7 +71091,7 @@ pub fn vzipq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t {
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(zip1)
@@ -71121,7 +71121,7 @@ pub fn vzipq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t {
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(zip1)
@@ -71156,7 +71156,7 @@ pub fn vzipq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t {
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(zip1)
@@ -71194,7 +71194,7 @@ pub fn vzipq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t {
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(zip1)
@@ -71247,7 +71247,7 @@ pub fn vzipq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t {
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(zip1)
@@ -71277,7 +71277,7 @@ pub fn vzipq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t {
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(zip1)
diff --git a/library/stdarch/crates/core_arch/src/loongarch64/lasx/generated.rs b/library/stdarch/crates/core_arch/src/loongarch64/lasx/generated.rs
index 1e74f79153ea5..f481a159eb632 100644
--- a/library/stdarch/crates/core_arch/src/loongarch64/lasx/generated.rs
+++ b/library/stdarch/crates/core_arch/src/loongarch64/lasx/generated.rs
@@ -91,38 +91,6 @@ unsafe extern "llvm-intrinsic" {
fn __lasx_xvsat_wu(a: __v8u32, b: u32) -> __v8u32;
#[link_name = "llvm.loongarch.lasx.xvsat.du"]
fn __lasx_xvsat_du(a: __v4u64, b: u32) -> __v4u64;
- #[link_name = "llvm.loongarch.lasx.xvavg.b"]
- fn __lasx_xvavg_b(a: __v32i8, b: __v32i8) -> __v32i8;
- #[link_name = "llvm.loongarch.lasx.xvavg.h"]
- fn __lasx_xvavg_h(a: __v16i16, b: __v16i16) -> __v16i16;
- #[link_name = "llvm.loongarch.lasx.xvavg.w"]
- fn __lasx_xvavg_w(a: __v8i32, b: __v8i32) -> __v8i32;
- #[link_name = "llvm.loongarch.lasx.xvavg.d"]
- fn __lasx_xvavg_d(a: __v4i64, b: __v4i64) -> __v4i64;
- #[link_name = "llvm.loongarch.lasx.xvavg.bu"]
- fn __lasx_xvavg_bu(a: __v32u8, b: __v32u8) -> __v32u8;
- #[link_name = "llvm.loongarch.lasx.xvavg.hu"]
- fn __lasx_xvavg_hu(a: __v16u16, b: __v16u16) -> __v16u16;
- #[link_name = "llvm.loongarch.lasx.xvavg.wu"]
- fn __lasx_xvavg_wu(a: __v8u32, b: __v8u32) -> __v8u32;
- #[link_name = "llvm.loongarch.lasx.xvavg.du"]
- fn __lasx_xvavg_du(a: __v4u64, b: __v4u64) -> __v4u64;
- #[link_name = "llvm.loongarch.lasx.xvavgr.b"]
- fn __lasx_xvavgr_b(a: __v32i8, b: __v32i8) -> __v32i8;
- #[link_name = "llvm.loongarch.lasx.xvavgr.h"]
- fn __lasx_xvavgr_h(a: __v16i16, b: __v16i16) -> __v16i16;
- #[link_name = "llvm.loongarch.lasx.xvavgr.w"]
- fn __lasx_xvavgr_w(a: __v8i32, b: __v8i32) -> __v8i32;
- #[link_name = "llvm.loongarch.lasx.xvavgr.d"]
- fn __lasx_xvavgr_d(a: __v4i64, b: __v4i64) -> __v4i64;
- #[link_name = "llvm.loongarch.lasx.xvavgr.bu"]
- fn __lasx_xvavgr_bu(a: __v32u8, b: __v32u8) -> __v32u8;
- #[link_name = "llvm.loongarch.lasx.xvavgr.hu"]
- fn __lasx_xvavgr_hu(a: __v16u16, b: __v16u16) -> __v16u16;
- #[link_name = "llvm.loongarch.lasx.xvavgr.wu"]
- fn __lasx_xvavgr_wu(a: __v8u32, b: __v8u32) -> __v8u32;
- #[link_name = "llvm.loongarch.lasx.xvavgr.du"]
- fn __lasx_xvavgr_du(a: __v4u64, b: __v4u64) -> __v4u64;
#[link_name = "llvm.loongarch.lasx.xvhaddw.h.b"]
fn __lasx_xvhaddw_h_b(a: __v32i8, b: __v32i8) -> __v16i16;
#[link_name = "llvm.loongarch.lasx.xvhaddw.w.h"]
@@ -1283,118 +1251,6 @@ pub fn lasx_xvsat_du(a: m256i) -> m256i {
unsafe { transmute(__lasx_xvsat_du(transmute(a), IMM6)) }
}
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvavg_b(a: m256i, b: m256i) -> m256i {
- unsafe { transmute(__lasx_xvavg_b(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvavg_h(a: m256i, b: m256i) -> m256i {
- unsafe { transmute(__lasx_xvavg_h(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvavg_w(a: m256i, b: m256i) -> m256i {
- unsafe { transmute(__lasx_xvavg_w(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvavg_d(a: m256i, b: m256i) -> m256i {
- unsafe { transmute(__lasx_xvavg_d(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvavg_bu(a: m256i, b: m256i) -> m256i {
- unsafe { transmute(__lasx_xvavg_bu(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvavg_hu(a: m256i, b: m256i) -> m256i {
- unsafe { transmute(__lasx_xvavg_hu(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvavg_wu(a: m256i, b: m256i) -> m256i {
- unsafe { transmute(__lasx_xvavg_wu(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvavg_du(a: m256i, b: m256i) -> m256i {
- unsafe { transmute(__lasx_xvavg_du(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvavgr_b(a: m256i, b: m256i) -> m256i {
- unsafe { transmute(__lasx_xvavgr_b(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvavgr_h(a: m256i, b: m256i) -> m256i {
- unsafe { transmute(__lasx_xvavgr_h(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvavgr_w(a: m256i, b: m256i) -> m256i {
- unsafe { transmute(__lasx_xvavgr_w(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvavgr_d(a: m256i, b: m256i) -> m256i {
- unsafe { transmute(__lasx_xvavgr_d(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvavgr_bu(a: m256i, b: m256i) -> m256i {
- unsafe { transmute(__lasx_xvavgr_bu(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvavgr_hu(a: m256i, b: m256i) -> m256i {
- unsafe { transmute(__lasx_xvavgr_hu(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvavgr_wu(a: m256i, b: m256i) -> m256i {
- unsafe { transmute(__lasx_xvavgr_wu(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvavgr_du(a: m256i, b: m256i) -> m256i {
- unsafe { transmute(__lasx_xvavgr_du(transmute(a), transmute(b))) }
-}
-
#[inline]
#[target_feature(enable = "lasx")]
#[unstable(feature = "stdarch_loongarch", issue = "117427")]
diff --git a/library/stdarch/crates/core_arch/src/loongarch64/lasx/portable.rs b/library/stdarch/crates/core_arch/src/loongarch64/lasx/portable.rs
index 73ea74d9dc3bb..d53f21c792626 100644
--- a/library/stdarch/crates/core_arch/src/loongarch64/lasx/portable.rs
+++ b/library/stdarch/crates/core_arch/src/loongarch64/lasx/portable.rs
@@ -896,6 +896,24 @@ impl_vvvv!("lasx", lasx_xvfnmsub_d, simd_ext_fnmsub, m256d, f64x4);
impl_vugv!("lasx", lasx_xvinsgr2vr_w, simd_insert, m256i, i32x8, i32, 3);
impl_vugv!("lasx", lasx_xvinsgr2vr_d, simd_insert, m256i, i64x4, i64, 2);
+impl_vavg!("lasx", lasx_xvavg_b, m256i, i8x32, i16x32);
+impl_vavg!("lasx", lasx_xvavg_h, m256i, i16x16, i32x16);
+impl_vavg!("lasx", lasx_xvavg_w, m256i, i32x8, i64x8);
+impl_vavg!("lasx", lasx_xvavg_d, m256i, i64x4, i128x4);
+impl_vavg!("lasx", lasx_xvavg_bu, m256i, u8x32, u16x32);
+impl_vavg!("lasx", lasx_xvavg_hu, m256i, u16x16, u32x16);
+impl_vavg!("lasx", lasx_xvavg_wu, m256i, u32x8, u64x8);
+impl_vavg!("lasx", lasx_xvavg_du, m256i, u64x4, u128x4);
+
+impl_vavgr!("lasx", lasx_xvavgr_b, m256i, i8x32, i16x32);
+impl_vavgr!("lasx", lasx_xvavgr_h, m256i, i16x16, i32x16);
+impl_vavgr!("lasx", lasx_xvavgr_w, m256i, i32x8, i64x8);
+impl_vavgr!("lasx", lasx_xvavgr_d, m256i, i64x4, i128x4);
+impl_vavgr!("lasx", lasx_xvavgr_bu, m256i, u8x32, u16x32);
+impl_vavgr!("lasx", lasx_xvavgr_hu, m256i, u16x16, u32x16);
+impl_vavgr!("lasx", lasx_xvavgr_wu, m256i, u32x8, u64x8);
+impl_vavgr!("lasx", lasx_xvavgr_du, m256i, u64x4, u128x4);
+
#[cfg(test)]
mod tests {
use crate::{
diff --git a/library/stdarch/crates/core_arch/src/loongarch64/lsx/generated.rs b/library/stdarch/crates/core_arch/src/loongarch64/lsx/generated.rs
index 54de126e03e27..7915ef07d68e7 100644
--- a/library/stdarch/crates/core_arch/src/loongarch64/lsx/generated.rs
+++ b/library/stdarch/crates/core_arch/src/loongarch64/lsx/generated.rs
@@ -91,38 +91,6 @@ unsafe extern "llvm-intrinsic" {
fn __lsx_vsat_wu(a: __v4u32, b: u32) -> __v4u32;
#[link_name = "llvm.loongarch.lsx.vsat.du"]
fn __lsx_vsat_du(a: __v2u64, b: u32) -> __v2u64;
- #[link_name = "llvm.loongarch.lsx.vavg.b"]
- fn __lsx_vavg_b(a: __v16i8, b: __v16i8) -> __v16i8;
- #[link_name = "llvm.loongarch.lsx.vavg.h"]
- fn __lsx_vavg_h(a: __v8i16, b: __v8i16) -> __v8i16;
- #[link_name = "llvm.loongarch.lsx.vavg.w"]
- fn __lsx_vavg_w(a: __v4i32, b: __v4i32) -> __v4i32;
- #[link_name = "llvm.loongarch.lsx.vavg.d"]
- fn __lsx_vavg_d(a: __v2i64, b: __v2i64) -> __v2i64;
- #[link_name = "llvm.loongarch.lsx.vavg.bu"]
- fn __lsx_vavg_bu(a: __v16u8, b: __v16u8) -> __v16u8;
- #[link_name = "llvm.loongarch.lsx.vavg.hu"]
- fn __lsx_vavg_hu(a: __v8u16, b: __v8u16) -> __v8u16;
- #[link_name = "llvm.loongarch.lsx.vavg.wu"]
- fn __lsx_vavg_wu(a: __v4u32, b: __v4u32) -> __v4u32;
- #[link_name = "llvm.loongarch.lsx.vavg.du"]
- fn __lsx_vavg_du(a: __v2u64, b: __v2u64) -> __v2u64;
- #[link_name = "llvm.loongarch.lsx.vavgr.b"]
- fn __lsx_vavgr_b(a: __v16i8, b: __v16i8) -> __v16i8;
- #[link_name = "llvm.loongarch.lsx.vavgr.h"]
- fn __lsx_vavgr_h(a: __v8i16, b: __v8i16) -> __v8i16;
- #[link_name = "llvm.loongarch.lsx.vavgr.w"]
- fn __lsx_vavgr_w(a: __v4i32, b: __v4i32) -> __v4i32;
- #[link_name = "llvm.loongarch.lsx.vavgr.d"]
- fn __lsx_vavgr_d(a: __v2i64, b: __v2i64) -> __v2i64;
- #[link_name = "llvm.loongarch.lsx.vavgr.bu"]
- fn __lsx_vavgr_bu(a: __v16u8, b: __v16u8) -> __v16u8;
- #[link_name = "llvm.loongarch.lsx.vavgr.hu"]
- fn __lsx_vavgr_hu(a: __v8u16, b: __v8u16) -> __v8u16;
- #[link_name = "llvm.loongarch.lsx.vavgr.wu"]
- fn __lsx_vavgr_wu(a: __v4u32, b: __v4u32) -> __v4u32;
- #[link_name = "llvm.loongarch.lsx.vavgr.du"]
- fn __lsx_vavgr_du(a: __v2u64, b: __v2u64) -> __v2u64;
#[link_name = "llvm.loongarch.lsx.vhaddw.h.b"]
fn __lsx_vhaddw_h_b(a: __v16i8, b: __v16i8) -> __v8i16;
#[link_name = "llvm.loongarch.lsx.vhaddw.w.h"]
@@ -1203,118 +1171,6 @@ pub fn lsx_vsat_du(a: m128i) -> m128i {
unsafe { transmute(__lsx_vsat_du(transmute(a), IMM6)) }
}
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vavg_b(a: m128i, b: m128i) -> m128i {
- unsafe { transmute(__lsx_vavg_b(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vavg_h(a: m128i, b: m128i) -> m128i {
- unsafe { transmute(__lsx_vavg_h(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vavg_w(a: m128i, b: m128i) -> m128i {
- unsafe { transmute(__lsx_vavg_w(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vavg_d(a: m128i, b: m128i) -> m128i {
- unsafe { transmute(__lsx_vavg_d(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vavg_bu(a: m128i, b: m128i) -> m128i {
- unsafe { transmute(__lsx_vavg_bu(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vavg_hu(a: m128i, b: m128i) -> m128i {
- unsafe { transmute(__lsx_vavg_hu(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vavg_wu(a: m128i, b: m128i) -> m128i {
- unsafe { transmute(__lsx_vavg_wu(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vavg_du(a: m128i, b: m128i) -> m128i {
- unsafe { transmute(__lsx_vavg_du(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vavgr_b(a: m128i, b: m128i) -> m128i {
- unsafe { transmute(__lsx_vavgr_b(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vavgr_h(a: m128i, b: m128i) -> m128i {
- unsafe { transmute(__lsx_vavgr_h(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vavgr_w(a: m128i, b: m128i) -> m128i {
- unsafe { transmute(__lsx_vavgr_w(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vavgr_d(a: m128i, b: m128i) -> m128i {
- unsafe { transmute(__lsx_vavgr_d(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vavgr_bu(a: m128i, b: m128i) -> m128i {
- unsafe { transmute(__lsx_vavgr_bu(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vavgr_hu(a: m128i, b: m128i) -> m128i {
- unsafe { transmute(__lsx_vavgr_hu(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vavgr_wu(a: m128i, b: m128i) -> m128i {
- unsafe { transmute(__lsx_vavgr_wu(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vavgr_du(a: m128i, b: m128i) -> m128i {
- unsafe { transmute(__lsx_vavgr_du(transmute(a), transmute(b))) }
-}
-
#[inline]
#[target_feature(enable = "lsx")]
#[unstable(feature = "stdarch_loongarch", issue = "117427")]
diff --git a/library/stdarch/crates/core_arch/src/loongarch64/lsx/portable.rs b/library/stdarch/crates/core_arch/src/loongarch64/lsx/portable.rs
index 31467bf013e27..2b5bfe1ab4d2b 100644
--- a/library/stdarch/crates/core_arch/src/loongarch64/lsx/portable.rs
+++ b/library/stdarch/crates/core_arch/src/loongarch64/lsx/portable.rs
@@ -574,6 +574,24 @@ impl_vugv!("lsx", lsx_vinsgr2vr_h, simd_insert, m128i, i16x8, i32, 3);
impl_vugv!("lsx", lsx_vinsgr2vr_w, simd_insert, m128i, i32x4, i32, 2);
impl_vugv!("lsx", lsx_vinsgr2vr_d, simd_insert, m128i, i64x2, i64, 1);
+impl_vavg!("lsx", lsx_vavg_b, m128i, i8x16, i16x16);
+impl_vavg!("lsx", lsx_vavg_h, m128i, i16x8, i32x8);
+impl_vavg!("lsx", lsx_vavg_w, m128i, i32x4, i64x4);
+impl_vavg!("lsx", lsx_vavg_d, m128i, i64x2, i128x2);
+impl_vavg!("lsx", lsx_vavg_bu, m128i, u8x16, u16x16);
+impl_vavg!("lsx", lsx_vavg_hu, m128i, u16x8, u32x8);
+impl_vavg!("lsx", lsx_vavg_wu, m128i, u32x4, u64x4);
+impl_vavg!("lsx", lsx_vavg_du, m128i, u64x2, u128x2);
+
+impl_vavgr!("lsx", lsx_vavgr_b, m128i, i8x16, i16x16);
+impl_vavgr!("lsx", lsx_vavgr_h, m128i, i16x8, i32x8);
+impl_vavgr!("lsx", lsx_vavgr_w, m128i, i32x4, i64x4);
+impl_vavgr!("lsx", lsx_vavgr_d, m128i, i64x2, i128x2);
+impl_vavgr!("lsx", lsx_vavgr_bu, m128i, u8x16, u16x16);
+impl_vavgr!("lsx", lsx_vavgr_hu, m128i, u16x8, u32x8);
+impl_vavgr!("lsx", lsx_vavgr_wu, m128i, u32x4, u64x4);
+impl_vavgr!("lsx", lsx_vavgr_du, m128i, u64x2, u128x2);
+
#[cfg(test)]
mod tests {
use crate::{
diff --git a/library/stdarch/crates/core_arch/src/loongarch64/simd.rs b/library/stdarch/crates/core_arch/src/loongarch64/simd.rs
index 1d83333e2f532..7ce6071841460 100644
--- a/library/stdarch/crates/core_arch/src/loongarch64/simd.rs
+++ b/library/stdarch/crates/core_arch/src/loongarch64/simd.rs
@@ -304,6 +304,44 @@ pub(super) const unsafe fn simd_ext_stx(a: T, b: *mut i8, c: i64) {
core::ptr::write_unaligned(b, a);
}
+macro_rules! impl_vavg {
+ ($ft:literal, $name:ident, $oty:ty, $ity:ty, $wty:ty) => {
+ #[inline]
+ #[target_feature(enable = $ft)]
+ #[unstable(feature = "stdarch_loongarch", issue = "117427")]
+ pub fn $name(a: $oty, b: $oty) -> $oty {
+ unsafe {
+ let a: $wty = simd_cast(transmute::<_, $ity>(a));
+ let b: $wty = simd_cast(transmute::<_, $ity>(b));
+ let r: $ity = simd_cast(simd_shr(simd_add(a, b), <$wty>::splat(1)));
+ transmute(r)
+ }
+ }
+ };
+}
+
+macro_rules! impl_vavgr {
+ ($ft:literal, $name:ident, $oty:ty, $ity:ty, $wty:ty) => {
+ #[inline]
+ #[target_feature(enable = $ft)]
+ #[unstable(feature = "stdarch_loongarch", issue = "117427")]
+ pub fn $name(a: $oty, b: $oty) -> $oty {
+ unsafe {
+ let a: $wty = simd_cast(transmute::<_, $ity>(a));
+ let b: $wty = simd_cast(transmute::<_, $ity>(b));
+ let r: $ity = simd_cast(simd_shr(
+ simd_add(simd_add(a, b), <$wty>::splat(1)),
+ <$wty>::splat(1),
+ ));
+ transmute(r)
+ }
+ }
+ };
+}
+
+pub(super) use impl_vavg;
+pub(super) use impl_vavgr;
+
macro_rules! impl_vv {
($ft:literal, $name:ident, $op:ident, $oty:ty, $ity:ty) => {
#[inline]
diff --git a/library/stdarch/crates/core_arch/src/x86/avx2.rs b/library/stdarch/crates/core_arch/src/x86/avx2.rs
index eb636a4fa0397..333f38e5474cc 100644
--- a/library/stdarch/crates/core_arch/src/x86/avx2.rs
+++ b/library/stdarch/crates/core_arch/src/x86/avx2.rs
@@ -2871,14 +2871,8 @@ pub const fn _mm256_bslli_epi128(a: __m256i) -> __m256i {
#[target_feature(enable = "avx2")]
#[cfg_attr(test, assert_instr(vpsllvd))]
#[stable(feature = "simd_x86", since = "1.27.0")]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm_sllv_epi32(a: __m128i, count: __m128i) -> __m128i {
- unsafe {
- let count = count.as_u32x4();
- let no_overflow: u32x4 = simd_lt(count, u32x4::splat(u32::BITS));
- let count = simd_select(no_overflow, count, u32x4::ZERO);
- simd_select(no_overflow, simd_shl(a.as_u32x4(), count), u32x4::ZERO).as_m128i()
- }
+pub fn _mm_sllv_epi32(a: __m128i, count: __m128i) -> __m128i {
+ unsafe { transmute(psllvd(a.as_i32x4(), count.as_i32x4())) }
}
/// Shifts packed 32-bit integers in `a` left by the amount
@@ -2890,14 +2884,8 @@ pub const fn _mm_sllv_epi32(a: __m128i, count: __m128i) -> __m128i {
#[target_feature(enable = "avx2")]
#[cfg_attr(test, assert_instr(vpsllvd))]
#[stable(feature = "simd_x86", since = "1.27.0")]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm256_sllv_epi32(a: __m256i, count: __m256i) -> __m256i {
- unsafe {
- let count = count.as_u32x8();
- let no_overflow: u32x8 = simd_lt(count, u32x8::splat(u32::BITS));
- let count = simd_select(no_overflow, count, u32x8::ZERO);
- simd_select(no_overflow, simd_shl(a.as_u32x8(), count), u32x8::ZERO).as_m256i()
- }
+pub fn _mm256_sllv_epi32(a: __m256i, count: __m256i) -> __m256i {
+ unsafe { transmute(psllvd256(a.as_i32x8(), count.as_i32x8())) }
}
/// Shifts packed 64-bit integers in `a` left by the amount
@@ -2909,14 +2897,8 @@ pub const fn _mm256_sllv_epi32(a: __m256i, count: __m256i) -> __m256i {
#[target_feature(enable = "avx2")]
#[cfg_attr(test, assert_instr(vpsllvq))]
#[stable(feature = "simd_x86", since = "1.27.0")]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm_sllv_epi64(a: __m128i, count: __m128i) -> __m128i {
- unsafe {
- let count = count.as_u64x2();
- let no_overflow: u64x2 = simd_lt(count, u64x2::splat(u64::BITS as u64));
- let count = simd_select(no_overflow, count, u64x2::ZERO);
- simd_select(no_overflow, simd_shl(a.as_u64x2(), count), u64x2::ZERO).as_m128i()
- }
+pub fn _mm_sllv_epi64(a: __m128i, count: __m128i) -> __m128i {
+ unsafe { transmute(psllvq(a.as_i64x2(), count.as_i64x2())) }
}
/// Shifts packed 64-bit integers in `a` left by the amount
@@ -2928,14 +2910,8 @@ pub const fn _mm_sllv_epi64(a: __m128i, count: __m128i) -> __m128i {
#[target_feature(enable = "avx2")]
#[cfg_attr(test, assert_instr(vpsllvq))]
#[stable(feature = "simd_x86", since = "1.27.0")]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm256_sllv_epi64(a: __m256i, count: __m256i) -> __m256i {
- unsafe {
- let count = count.as_u64x4();
- let no_overflow: u64x4 = simd_lt(count, u64x4::splat(u64::BITS as u64));
- let count = simd_select(no_overflow, count, u64x4::ZERO);
- simd_select(no_overflow, simd_shl(a.as_u64x4(), count), u64x4::ZERO).as_m256i()
- }
+pub fn _mm256_sllv_epi64(a: __m256i, count: __m256i) -> __m256i {
+ unsafe { transmute(psllvq256(a.as_i64x4(), count.as_i64x4())) }
}
/// Shifts packed 16-bit integers in `a` right by `count` while
@@ -3000,14 +2976,8 @@ pub const fn _mm256_srai_epi32(a: __m256i) -> __m256i {
#[target_feature(enable = "avx2")]
#[cfg_attr(test, assert_instr(vpsravd))]
#[stable(feature = "simd_x86", since = "1.27.0")]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm_srav_epi32(a: __m128i, count: __m128i) -> __m128i {
- unsafe {
- let count = count.as_u32x4();
- let no_overflow: u32x4 = simd_lt(count, u32x4::splat(u32::BITS));
- let count = simd_select(no_overflow, transmute(count), i32x4::splat(31));
- simd_shr(a.as_i32x4(), count).as_m128i()
- }
+pub fn _mm_srav_epi32(a: __m128i, count: __m128i) -> __m128i {
+ unsafe { transmute(psravd(a.as_i32x4(), count.as_i32x4())) }
}
/// Shifts packed 32-bit integers in `a` right by the amount specified by the
@@ -3018,14 +2988,8 @@ pub const fn _mm_srav_epi32(a: __m128i, count: __m128i) -> __m128i {
#[target_feature(enable = "avx2")]
#[cfg_attr(test, assert_instr(vpsravd))]
#[stable(feature = "simd_x86", since = "1.27.0")]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm256_srav_epi32(a: __m256i, count: __m256i) -> __m256i {
- unsafe {
- let count = count.as_u32x8();
- let no_overflow: u32x8 = simd_lt(count, u32x8::splat(u32::BITS));
- let count = simd_select(no_overflow, transmute(count), i32x8::splat(31));
- simd_shr(a.as_i32x8(), count).as_m256i()
- }
+pub fn _mm256_srav_epi32(a: __m256i, count: __m256i) -> __m256i {
+ unsafe { transmute(psravd256(a.as_i32x8(), count.as_i32x8())) }
}
/// Shifts 128-bit lanes in `a` right by `imm8` bytes while shifting in zeros.
@@ -3212,14 +3176,8 @@ pub const fn _mm256_srli_epi64(a: __m256i) -> __m256i {
#[target_feature(enable = "avx2")]
#[cfg_attr(test, assert_instr(vpsrlvd))]
#[stable(feature = "simd_x86", since = "1.27.0")]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm_srlv_epi32(a: __m128i, count: __m128i) -> __m128i {
- unsafe {
- let count = count.as_u32x4();
- let no_overflow: u32x4 = simd_lt(count, u32x4::splat(u32::BITS));
- let count = simd_select(no_overflow, count, u32x4::ZERO);
- simd_select(no_overflow, simd_shr(a.as_u32x4(), count), u32x4::ZERO).as_m128i()
- }
+pub fn _mm_srlv_epi32(a: __m128i, count: __m128i) -> __m128i {
+ unsafe { transmute(psrlvd(a.as_i32x4(), count.as_i32x4())) }
}
/// Shifts packed 32-bit integers in `a` right by the amount specified by
@@ -3230,14 +3188,8 @@ pub const fn _mm_srlv_epi32(a: __m128i, count: __m128i) -> __m128i {
#[target_feature(enable = "avx2")]
#[cfg_attr(test, assert_instr(vpsrlvd))]
#[stable(feature = "simd_x86", since = "1.27.0")]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm256_srlv_epi32(a: __m256i, count: __m256i) -> __m256i {
- unsafe {
- let count = count.as_u32x8();
- let no_overflow: u32x8 = simd_lt(count, u32x8::splat(u32::BITS));
- let count = simd_select(no_overflow, count, u32x8::ZERO);
- simd_select(no_overflow, simd_shr(a.as_u32x8(), count), u32x8::ZERO).as_m256i()
- }
+pub fn _mm256_srlv_epi32(a: __m256i, count: __m256i) -> __m256i {
+ unsafe { transmute(psrlvd256(a.as_i32x8(), count.as_i32x8())) }
}
/// Shifts packed 64-bit integers in `a` right by the amount specified by
@@ -3248,14 +3200,8 @@ pub const fn _mm256_srlv_epi32(a: __m256i, count: __m256i) -> __m256i {
#[target_feature(enable = "avx2")]
#[cfg_attr(test, assert_instr(vpsrlvq))]
#[stable(feature = "simd_x86", since = "1.27.0")]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm_srlv_epi64(a: __m128i, count: __m128i) -> __m128i {
- unsafe {
- let count = count.as_u64x2();
- let no_overflow: u64x2 = simd_lt(count, u64x2::splat(u64::BITS as u64));
- let count = simd_select(no_overflow, count, u64x2::ZERO);
- simd_select(no_overflow, simd_shr(a.as_u64x2(), count), u64x2::ZERO).as_m128i()
- }
+pub fn _mm_srlv_epi64(a: __m128i, count: __m128i) -> __m128i {
+ unsafe { transmute(psrlvq(a.as_i64x2(), count.as_i64x2())) }
}
/// Shifts packed 64-bit integers in `a` right by the amount specified by
@@ -3266,14 +3212,8 @@ pub const fn _mm_srlv_epi64(a: __m128i, count: __m128i) -> __m128i {
#[target_feature(enable = "avx2")]
#[cfg_attr(test, assert_instr(vpsrlvq))]
#[stable(feature = "simd_x86", since = "1.27.0")]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm256_srlv_epi64(a: __m256i, count: __m256i) -> __m256i {
- unsafe {
- let count = count.as_u64x4();
- let no_overflow: u64x4 = simd_lt(count, u64x4::splat(u64::BITS as u64));
- let count = simd_select(no_overflow, count, u64x4::ZERO);
- simd_select(no_overflow, simd_shr(a.as_u64x4(), count), u64x4::ZERO).as_m256i()
- }
+pub fn _mm256_srlv_epi64(a: __m256i, count: __m256i) -> __m256i {
+ unsafe { transmute(psrlvq256(a.as_i64x4(), count.as_i64x4())) }
}
/// Load 256-bits of integer data from memory into dst using a non-temporal memory hint. mem_addr
@@ -3849,16 +3789,36 @@ unsafe extern "llvm-intrinsic" {
fn pslld(a: i32x8, count: i32x4) -> i32x8;
#[link_name = "llvm.x86.avx2.psll.q"]
fn psllq(a: i64x4, count: i64x2) -> i64x4;
+ #[link_name = "llvm.x86.avx2.psllv.d"]
+ fn psllvd(a: i32x4, count: i32x4) -> i32x4;
+ #[link_name = "llvm.x86.avx2.psllv.d.256"]
+ fn psllvd256(a: i32x8, count: i32x8) -> i32x8;
+ #[link_name = "llvm.x86.avx2.psllv.q"]
+ fn psllvq(a: i64x2, count: i64x2) -> i64x2;
+ #[link_name = "llvm.x86.avx2.psllv.q.256"]
+ fn psllvq256(a: i64x4, count: i64x4) -> i64x4;
#[link_name = "llvm.x86.avx2.psra.w"]
fn psraw(a: i16x16, count: i16x8) -> i16x16;
#[link_name = "llvm.x86.avx2.psra.d"]
fn psrad(a: i32x8, count: i32x4) -> i32x8;
+ #[link_name = "llvm.x86.avx2.psrav.d"]
+ fn psravd(a: i32x4, count: i32x4) -> i32x4;
+ #[link_name = "llvm.x86.avx2.psrav.d.256"]
+ fn psravd256(a: i32x8, count: i32x8) -> i32x8;
#[link_name = "llvm.x86.avx2.psrl.w"]
fn psrlw(a: i16x16, count: i16x8) -> i16x16;
#[link_name = "llvm.x86.avx2.psrl.d"]
fn psrld(a: i32x8, count: i32x4) -> i32x8;
#[link_name = "llvm.x86.avx2.psrl.q"]
fn psrlq(a: i64x4, count: i64x2) -> i64x4;
+ #[link_name = "llvm.x86.avx2.psrlv.d"]
+ fn psrlvd(a: i32x4, count: i32x4) -> i32x4;
+ #[link_name = "llvm.x86.avx2.psrlv.d.256"]
+ fn psrlvd256(a: i32x8, count: i32x8) -> i32x8;
+ #[link_name = "llvm.x86.avx2.psrlv.q"]
+ fn psrlvq(a: i64x2, count: i64x2) -> i64x2;
+ #[link_name = "llvm.x86.avx2.psrlv.q.256"]
+ fn psrlvq256(a: i64x4, count: i64x4) -> i64x4;
#[link_name = "llvm.x86.avx2.pshuf.b"]
fn pshufb(a: u8x32, b: u8x32) -> u8x32;
#[link_name = "llvm.x86.avx2.permd"]
@@ -5163,7 +5123,7 @@ mod tests {
}
#[simd_test(enable = "avx2")]
- const fn test_mm_sllv_epi32() {
+ fn test_mm_sllv_epi32() {
let a = _mm_set1_epi32(2);
let b = _mm_set1_epi32(1);
let r = _mm_sllv_epi32(a, b);
@@ -5172,7 +5132,7 @@ mod tests {
}
#[simd_test(enable = "avx2")]
- const fn test_mm256_sllv_epi32() {
+ fn test_mm256_sllv_epi32() {
let a = _mm256_set1_epi32(2);
let b = _mm256_set1_epi32(1);
let r = _mm256_sllv_epi32(a, b);
@@ -5181,7 +5141,7 @@ mod tests {
}
#[simd_test(enable = "avx2")]
- const fn test_mm_sllv_epi64() {
+ fn test_mm_sllv_epi64() {
let a = _mm_set1_epi64x(2);
let b = _mm_set1_epi64x(1);
let r = _mm_sllv_epi64(a, b);
@@ -5190,7 +5150,7 @@ mod tests {
}
#[simd_test(enable = "avx2")]
- const fn test_mm256_sllv_epi64() {
+ fn test_mm256_sllv_epi64() {
let a = _mm256_set1_epi64x(2);
let b = _mm256_set1_epi64x(1);
let r = _mm256_sllv_epi64(a, b);
@@ -5231,7 +5191,7 @@ mod tests {
}
#[simd_test(enable = "avx2")]
- const fn test_mm_srav_epi32() {
+ fn test_mm_srav_epi32() {
let a = _mm_set1_epi32(4);
let count = _mm_set1_epi32(1);
let r = _mm_srav_epi32(a, count);
@@ -5240,7 +5200,7 @@ mod tests {
}
#[simd_test(enable = "avx2")]
- const fn test_mm256_srav_epi32() {
+ fn test_mm256_srav_epi32() {
let a = _mm256_set1_epi32(4);
let count = _mm256_set1_epi32(1);
let r = _mm256_srav_epi32(a, count);
@@ -5317,7 +5277,7 @@ mod tests {
}
#[simd_test(enable = "avx2")]
- const fn test_mm_srlv_epi32() {
+ fn test_mm_srlv_epi32() {
let a = _mm_set1_epi32(2);
let count = _mm_set1_epi32(1);
let r = _mm_srlv_epi32(a, count);
@@ -5326,7 +5286,7 @@ mod tests {
}
#[simd_test(enable = "avx2")]
- const fn test_mm256_srlv_epi32() {
+ fn test_mm256_srlv_epi32() {
let a = _mm256_set1_epi32(2);
let count = _mm256_set1_epi32(1);
let r = _mm256_srlv_epi32(a, count);
@@ -5335,7 +5295,7 @@ mod tests {
}
#[simd_test(enable = "avx2")]
- const fn test_mm_srlv_epi64() {
+ fn test_mm_srlv_epi64() {
let a = _mm_set1_epi64x(2);
let count = _mm_set1_epi64x(1);
let r = _mm_srlv_epi64(a, count);
@@ -5344,7 +5304,7 @@ mod tests {
}
#[simd_test(enable = "avx2")]
- const fn test_mm256_srlv_epi64() {
+ fn test_mm256_srlv_epi64() {
let a = _mm256_set1_epi64x(2);
let count = _mm256_set1_epi64x(1);
let r = _mm256_srlv_epi64(a, count);
diff --git a/library/stdarch/crates/core_arch/src/x86/avx512bw.rs b/library/stdarch/crates/core_arch/src/x86/avx512bw.rs
index cda2fad4ef2de..e400453f627bc 100644
--- a/library/stdarch/crates/core_arch/src/x86/avx512bw.rs
+++ b/library/stdarch/crates/core_arch/src/x86/avx512bw.rs
@@ -7370,14 +7370,8 @@ pub const fn _mm_maskz_slli_epi16(k: __mmask8, a: __m128i) -> _
#[target_feature(enable = "avx512bw")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsllvw))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm512_sllv_epi16(a: __m512i, count: __m512i) -> __m512i {
- unsafe {
- let count = count.as_u16x32();
- let no_overflow: u16x32 = simd_lt(count, u16x32::splat(u16::BITS as u16));
- let count = simd_select(no_overflow, count, u16x32::ZERO);
- simd_select(no_overflow, simd_shl(a.as_u16x32(), count), u16x32::ZERO).as_m512i()
- }
+pub fn _mm512_sllv_epi16(a: __m512i, count: __m512i) -> __m512i {
+ unsafe { transmute(vpsllvw(a.as_i16x32(), count.as_i16x32())) }
}
/// Shift packed 16-bit integers in a left by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -7387,13 +7381,7 @@ pub const fn _mm512_sllv_epi16(a: __m512i, count: __m512i) -> __m512i {
#[target_feature(enable = "avx512bw")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsllvw))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm512_mask_sllv_epi16(
- src: __m512i,
- k: __mmask32,
- a: __m512i,
- count: __m512i,
-) -> __m512i {
+pub fn _mm512_mask_sllv_epi16(src: __m512i, k: __mmask32, a: __m512i, count: __m512i) -> __m512i {
unsafe {
let shf = _mm512_sllv_epi16(a, count).as_i16x32();
transmute(simd_select_bitmask(k, shf, src.as_i16x32()))
@@ -7407,8 +7395,7 @@ pub const fn _mm512_mask_sllv_epi16(
#[target_feature(enable = "avx512bw")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsllvw))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm512_maskz_sllv_epi16(k: __mmask32, a: __m512i, count: __m512i) -> __m512i {
+pub fn _mm512_maskz_sllv_epi16(k: __mmask32, a: __m512i, count: __m512i) -> __m512i {
unsafe {
let shf = _mm512_sllv_epi16(a, count).as_i16x32();
transmute(simd_select_bitmask(k, shf, i16x32::ZERO))
@@ -7422,14 +7409,8 @@ pub const fn _mm512_maskz_sllv_epi16(k: __mmask32, a: __m512i, count: __m512i) -
#[target_feature(enable = "avx512bw,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsllvw))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm256_sllv_epi16(a: __m256i, count: __m256i) -> __m256i {
- unsafe {
- let count = count.as_u16x16();
- let no_overflow: u16x16 = simd_lt(count, u16x16::splat(u16::BITS as u16));
- let count = simd_select(no_overflow, count, u16x16::ZERO);
- simd_select(no_overflow, simd_shl(a.as_u16x16(), count), u16x16::ZERO).as_m256i()
- }
+pub fn _mm256_sllv_epi16(a: __m256i, count: __m256i) -> __m256i {
+ unsafe { transmute(vpsllvw256(a.as_i16x16(), count.as_i16x16())) }
}
/// Shift packed 16-bit integers in a left by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -7439,13 +7420,7 @@ pub const fn _mm256_sllv_epi16(a: __m256i, count: __m256i) -> __m256i {
#[target_feature(enable = "avx512bw,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsllvw))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm256_mask_sllv_epi16(
- src: __m256i,
- k: __mmask16,
- a: __m256i,
- count: __m256i,
-) -> __m256i {
+pub fn _mm256_mask_sllv_epi16(src: __m256i, k: __mmask16, a: __m256i, count: __m256i) -> __m256i {
unsafe {
let shf = _mm256_sllv_epi16(a, count).as_i16x16();
transmute(simd_select_bitmask(k, shf, src.as_i16x16()))
@@ -7459,8 +7434,7 @@ pub const fn _mm256_mask_sllv_epi16(
#[target_feature(enable = "avx512bw,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsllvw))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm256_maskz_sllv_epi16(k: __mmask16, a: __m256i, count: __m256i) -> __m256i {
+pub fn _mm256_maskz_sllv_epi16(k: __mmask16, a: __m256i, count: __m256i) -> __m256i {
unsafe {
let shf = _mm256_sllv_epi16(a, count).as_i16x16();
transmute(simd_select_bitmask(k, shf, i16x16::ZERO))
@@ -7474,14 +7448,8 @@ pub const fn _mm256_maskz_sllv_epi16(k: __mmask16, a: __m256i, count: __m256i) -
#[target_feature(enable = "avx512bw,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsllvw))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm_sllv_epi16(a: __m128i, count: __m128i) -> __m128i {
- unsafe {
- let count = count.as_u16x8();
- let no_overflow: u16x8 = simd_lt(count, u16x8::splat(u16::BITS as u16));
- let count = simd_select(no_overflow, count, u16x8::ZERO);
- simd_select(no_overflow, simd_shl(a.as_u16x8(), count), u16x8::ZERO).as_m128i()
- }
+pub fn _mm_sllv_epi16(a: __m128i, count: __m128i) -> __m128i {
+ unsafe { transmute(vpsllvw128(a.as_i16x8(), count.as_i16x8())) }
}
/// Shift packed 16-bit integers in a left by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -7491,8 +7459,7 @@ pub const fn _mm_sllv_epi16(a: __m128i, count: __m128i) -> __m128i {
#[target_feature(enable = "avx512bw,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsllvw))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm_mask_sllv_epi16(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
+pub fn _mm_mask_sllv_epi16(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
unsafe {
let shf = _mm_sllv_epi16(a, count).as_i16x8();
transmute(simd_select_bitmask(k, shf, src.as_i16x8()))
@@ -7506,8 +7473,7 @@ pub const fn _mm_mask_sllv_epi16(src: __m128i, k: __mmask8, a: __m128i, count: _
#[target_feature(enable = "avx512bw,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsllvw))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm_maskz_sllv_epi16(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
+pub fn _mm_maskz_sllv_epi16(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
unsafe {
let shf = _mm_sllv_epi16(a, count).as_i16x8();
transmute(simd_select_bitmask(k, shf, i16x8::ZERO))
@@ -7759,14 +7725,8 @@ pub const fn _mm_maskz_srli_epi16(k: __mmask8, a: __m128i) -> _
#[target_feature(enable = "avx512bw")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsrlvw))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm512_srlv_epi16(a: __m512i, count: __m512i) -> __m512i {
- unsafe {
- let count = count.as_u16x32();
- let no_overflow: u16x32 = simd_lt(count, u16x32::splat(u16::BITS as u16));
- let count = simd_select(no_overflow, count, u16x32::ZERO);
- simd_select(no_overflow, simd_shr(a.as_u16x32(), count), u16x32::ZERO).as_m512i()
- }
+pub fn _mm512_srlv_epi16(a: __m512i, count: __m512i) -> __m512i {
+ unsafe { transmute(vpsrlvw(a.as_i16x32(), count.as_i16x32())) }
}
/// Shift packed 16-bit integers in a right by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -7776,13 +7736,7 @@ pub const fn _mm512_srlv_epi16(a: __m512i, count: __m512i) -> __m512i {
#[target_feature(enable = "avx512bw")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsrlvw))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm512_mask_srlv_epi16(
- src: __m512i,
- k: __mmask32,
- a: __m512i,
- count: __m512i,
-) -> __m512i {
+pub fn _mm512_mask_srlv_epi16(src: __m512i, k: __mmask32, a: __m512i, count: __m512i) -> __m512i {
unsafe {
let shf = _mm512_srlv_epi16(a, count).as_i16x32();
transmute(simd_select_bitmask(k, shf, src.as_i16x32()))
@@ -7796,8 +7750,7 @@ pub const fn _mm512_mask_srlv_epi16(
#[target_feature(enable = "avx512bw")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsrlvw))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm512_maskz_srlv_epi16(k: __mmask32, a: __m512i, count: __m512i) -> __m512i {
+pub fn _mm512_maskz_srlv_epi16(k: __mmask32, a: __m512i, count: __m512i) -> __m512i {
unsafe {
let shf = _mm512_srlv_epi16(a, count).as_i16x32();
transmute(simd_select_bitmask(k, shf, i16x32::ZERO))
@@ -7811,14 +7764,8 @@ pub const fn _mm512_maskz_srlv_epi16(k: __mmask32, a: __m512i, count: __m512i) -
#[target_feature(enable = "avx512bw,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsrlvw))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm256_srlv_epi16(a: __m256i, count: __m256i) -> __m256i {
- unsafe {
- let count = count.as_u16x16();
- let no_overflow: u16x16 = simd_lt(count, u16x16::splat(u16::BITS as u16));
- let count = simd_select(no_overflow, count, u16x16::ZERO);
- simd_select(no_overflow, simd_shr(a.as_u16x16(), count), u16x16::ZERO).as_m256i()
- }
+pub fn _mm256_srlv_epi16(a: __m256i, count: __m256i) -> __m256i {
+ unsafe { transmute(vpsrlvw256(a.as_i16x16(), count.as_i16x16())) }
}
/// Shift packed 16-bit integers in a right by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -7828,13 +7775,7 @@ pub const fn _mm256_srlv_epi16(a: __m256i, count: __m256i) -> __m256i {
#[target_feature(enable = "avx512bw,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsrlvw))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm256_mask_srlv_epi16(
- src: __m256i,
- k: __mmask16,
- a: __m256i,
- count: __m256i,
-) -> __m256i {
+pub fn _mm256_mask_srlv_epi16(src: __m256i, k: __mmask16, a: __m256i, count: __m256i) -> __m256i {
unsafe {
let shf = _mm256_srlv_epi16(a, count).as_i16x16();
transmute(simd_select_bitmask(k, shf, src.as_i16x16()))
@@ -7848,8 +7789,7 @@ pub const fn _mm256_mask_srlv_epi16(
#[target_feature(enable = "avx512bw,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsrlvw))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm256_maskz_srlv_epi16(k: __mmask16, a: __m256i, count: __m256i) -> __m256i {
+pub fn _mm256_maskz_srlv_epi16(k: __mmask16, a: __m256i, count: __m256i) -> __m256i {
unsafe {
let shf = _mm256_srlv_epi16(a, count).as_i16x16();
transmute(simd_select_bitmask(k, shf, i16x16::ZERO))
@@ -7863,14 +7803,8 @@ pub const fn _mm256_maskz_srlv_epi16(k: __mmask16, a: __m256i, count: __m256i) -
#[target_feature(enable = "avx512bw,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsrlvw))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm_srlv_epi16(a: __m128i, count: __m128i) -> __m128i {
- unsafe {
- let count = count.as_u16x8();
- let no_overflow: u16x8 = simd_lt(count, u16x8::splat(u16::BITS as u16));
- let count = simd_select(no_overflow, count, u16x8::ZERO);
- simd_select(no_overflow, simd_shr(a.as_u16x8(), count), u16x8::ZERO).as_m128i()
- }
+pub fn _mm_srlv_epi16(a: __m128i, count: __m128i) -> __m128i {
+ unsafe { transmute(vpsrlvw128(a.as_i16x8(), count.as_i16x8())) }
}
/// Shift packed 16-bit integers in a right by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -7880,8 +7814,7 @@ pub const fn _mm_srlv_epi16(a: __m128i, count: __m128i) -> __m128i {
#[target_feature(enable = "avx512bw,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsrlvw))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm_mask_srlv_epi16(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
+pub fn _mm_mask_srlv_epi16(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
unsafe {
let shf = _mm_srlv_epi16(a, count).as_i16x8();
transmute(simd_select_bitmask(k, shf, src.as_i16x8()))
@@ -7895,8 +7828,7 @@ pub const fn _mm_mask_srlv_epi16(src: __m128i, k: __mmask8, a: __m128i, count: _
#[target_feature(enable = "avx512bw,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsrlvw))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm_maskz_srlv_epi16(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
+pub fn _mm_maskz_srlv_epi16(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
unsafe {
let shf = _mm_srlv_epi16(a, count).as_i16x8();
transmute(simd_select_bitmask(k, shf, i16x8::ZERO))
@@ -8135,14 +8067,8 @@ pub const fn _mm_maskz_srai_epi16(k: __mmask8, a: __m128i) -> _
#[target_feature(enable = "avx512bw")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsravw))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm512_srav_epi16(a: __m512i, count: __m512i) -> __m512i {
- unsafe {
- let count = count.as_u16x32();
- let no_overflow: u16x32 = simd_lt(count, u16x32::splat(u16::BITS as u16));
- let count = simd_select(no_overflow, transmute(count), i16x32::splat(15));
- simd_shr(a.as_i16x32(), count).as_m512i()
- }
+pub fn _mm512_srav_epi16(a: __m512i, count: __m512i) -> __m512i {
+ unsafe { transmute(vpsravw(a.as_i16x32(), count.as_i16x32())) }
}
/// Shift packed 16-bit integers in a right by the amount specified by the corresponding element in count while shifting in sign bits, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -8152,13 +8078,7 @@ pub const fn _mm512_srav_epi16(a: __m512i, count: __m512i) -> __m512i {
#[target_feature(enable = "avx512bw")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsravw))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm512_mask_srav_epi16(
- src: __m512i,
- k: __mmask32,
- a: __m512i,
- count: __m512i,
-) -> __m512i {
+pub fn _mm512_mask_srav_epi16(src: __m512i, k: __mmask32, a: __m512i, count: __m512i) -> __m512i {
unsafe {
let shf = _mm512_srav_epi16(a, count).as_i16x32();
transmute(simd_select_bitmask(k, shf, src.as_i16x32()))
@@ -8172,8 +8092,7 @@ pub const fn _mm512_mask_srav_epi16(
#[target_feature(enable = "avx512bw")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsravw))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm512_maskz_srav_epi16(k: __mmask32, a: __m512i, count: __m512i) -> __m512i {
+pub fn _mm512_maskz_srav_epi16(k: __mmask32, a: __m512i, count: __m512i) -> __m512i {
unsafe {
let shf = _mm512_srav_epi16(a, count).as_i16x32();
transmute(simd_select_bitmask(k, shf, i16x32::ZERO))
@@ -8187,14 +8106,8 @@ pub const fn _mm512_maskz_srav_epi16(k: __mmask32, a: __m512i, count: __m512i) -
#[target_feature(enable = "avx512bw,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsravw))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm256_srav_epi16(a: __m256i, count: __m256i) -> __m256i {
- unsafe {
- let count = count.as_u16x16();
- let no_overflow: u16x16 = simd_lt(count, u16x16::splat(u16::BITS as u16));
- let count = simd_select(no_overflow, transmute(count), i16x16::splat(15));
- simd_shr(a.as_i16x16(), count).as_m256i()
- }
+pub fn _mm256_srav_epi16(a: __m256i, count: __m256i) -> __m256i {
+ unsafe { transmute(vpsravw256(a.as_i16x16(), count.as_i16x16())) }
}
/// Shift packed 16-bit integers in a right by the amount specified by the corresponding element in count while shifting in sign bits, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -8204,13 +8117,7 @@ pub const fn _mm256_srav_epi16(a: __m256i, count: __m256i) -> __m256i {
#[target_feature(enable = "avx512bw,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsravw))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm256_mask_srav_epi16(
- src: __m256i,
- k: __mmask16,
- a: __m256i,
- count: __m256i,
-) -> __m256i {
+pub fn _mm256_mask_srav_epi16(src: __m256i, k: __mmask16, a: __m256i, count: __m256i) -> __m256i {
unsafe {
let shf = _mm256_srav_epi16(a, count).as_i16x16();
transmute(simd_select_bitmask(k, shf, src.as_i16x16()))
@@ -8224,8 +8131,7 @@ pub const fn _mm256_mask_srav_epi16(
#[target_feature(enable = "avx512bw,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsravw))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm256_maskz_srav_epi16(k: __mmask16, a: __m256i, count: __m256i) -> __m256i {
+pub fn _mm256_maskz_srav_epi16(k: __mmask16, a: __m256i, count: __m256i) -> __m256i {
unsafe {
let shf = _mm256_srav_epi16(a, count).as_i16x16();
transmute(simd_select_bitmask(k, shf, i16x16::ZERO))
@@ -8239,14 +8145,8 @@ pub const fn _mm256_maskz_srav_epi16(k: __mmask16, a: __m256i, count: __m256i) -
#[target_feature(enable = "avx512bw,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsravw))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm_srav_epi16(a: __m128i, count: __m128i) -> __m128i {
- unsafe {
- let count = count.as_u16x8();
- let no_overflow: u16x8 = simd_lt(count, u16x8::splat(u16::BITS as u16));
- let count = simd_select(no_overflow, transmute(count), i16x8::splat(15));
- simd_shr(a.as_i16x8(), count).as_m128i()
- }
+pub fn _mm_srav_epi16(a: __m128i, count: __m128i) -> __m128i {
+ unsafe { transmute(vpsravw128(a.as_i16x8(), count.as_i16x8())) }
}
/// Shift packed 16-bit integers in a right by the amount specified by the corresponding element in count while shifting in sign bits, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -8256,8 +8156,7 @@ pub const fn _mm_srav_epi16(a: __m128i, count: __m128i) -> __m128i {
#[target_feature(enable = "avx512bw,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsravw))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm_mask_srav_epi16(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
+pub fn _mm_mask_srav_epi16(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
unsafe {
let shf = _mm_srav_epi16(a, count).as_i16x8();
transmute(simd_select_bitmask(k, shf, src.as_i16x8()))
@@ -8271,8 +8170,7 @@ pub const fn _mm_mask_srav_epi16(src: __m128i, k: __mmask8, a: __m128i, count: _
#[target_feature(enable = "avx512bw,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsravw))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm_maskz_srav_epi16(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
+pub fn _mm_maskz_srav_epi16(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
unsafe {
let shf = _mm_srav_epi16(a, count).as_i16x8();
transmute(simd_select_bitmask(k, shf, i16x8::ZERO))
@@ -12618,12 +12516,33 @@ unsafe extern "llvm-intrinsic" {
#[link_name = "llvm.x86.avx512.psll.w.512"]
fn vpsllw(a: i16x32, count: i16x8) -> i16x32;
+ #[link_name = "llvm.x86.avx512.psllv.w.512"]
+ fn vpsllvw(a: i16x32, b: i16x32) -> i16x32;
+ #[link_name = "llvm.x86.avx512.psllv.w.256"]
+ fn vpsllvw256(a: i16x16, b: i16x16) -> i16x16;
+ #[link_name = "llvm.x86.avx512.psllv.w.128"]
+ fn vpsllvw128(a: i16x8, b: i16x8) -> i16x8;
+
#[link_name = "llvm.x86.avx512.psrl.w.512"]
fn vpsrlw(a: i16x32, count: i16x8) -> i16x32;
+ #[link_name = "llvm.x86.avx512.psrlv.w.512"]
+ fn vpsrlvw(a: i16x32, b: i16x32) -> i16x32;
+ #[link_name = "llvm.x86.avx512.psrlv.w.256"]
+ fn vpsrlvw256(a: i16x16, b: i16x16) -> i16x16;
+ #[link_name = "llvm.x86.avx512.psrlv.w.128"]
+ fn vpsrlvw128(a: i16x8, b: i16x8) -> i16x8;
+
#[link_name = "llvm.x86.avx512.psra.w.512"]
fn vpsraw(a: i16x32, count: i16x8) -> i16x32;
+ #[link_name = "llvm.x86.avx512.psrav.w.512"]
+ fn vpsravw(a: i16x32, count: i16x32) -> i16x32;
+ #[link_name = "llvm.x86.avx512.psrav.w.256"]
+ fn vpsravw256(a: i16x16, count: i16x16) -> i16x16;
+ #[link_name = "llvm.x86.avx512.psrav.w.128"]
+ fn vpsravw128(a: i16x8, count: i16x8) -> i16x8;
+
#[link_name = "llvm.x86.avx512.vpermi2var.hi.512"]
fn vpermi2w(a: i16x32, idx: i16x32, b: i16x32) -> i16x32;
#[link_name = "llvm.x86.avx512.vpermi2var.hi.256"]
@@ -18386,7 +18305,7 @@ mod tests {
}
#[simd_test(enable = "avx512bw")]
- const fn test_mm512_sllv_epi16() {
+ fn test_mm512_sllv_epi16() {
let a = _mm512_set1_epi16(1 << 15);
let count = _mm512_set1_epi16(2);
let r = _mm512_sllv_epi16(a, count);
@@ -18395,7 +18314,7 @@ mod tests {
}
#[simd_test(enable = "avx512bw")]
- const fn test_mm512_mask_sllv_epi16() {
+ fn test_mm512_mask_sllv_epi16() {
let a = _mm512_set1_epi16(1 << 15);
let count = _mm512_set1_epi16(2);
let r = _mm512_mask_sllv_epi16(a, 0, a, count);
@@ -18406,7 +18325,7 @@ mod tests {
}
#[simd_test(enable = "avx512bw")]
- const fn test_mm512_maskz_sllv_epi16() {
+ fn test_mm512_maskz_sllv_epi16() {
let a = _mm512_set1_epi16(1 << 15);
let count = _mm512_set1_epi16(2);
let r = _mm512_maskz_sllv_epi16(0, a, count);
@@ -18417,7 +18336,7 @@ mod tests {
}
#[simd_test(enable = "avx512bw,avx512vl")]
- const fn test_mm256_sllv_epi16() {
+ fn test_mm256_sllv_epi16() {
let a = _mm256_set1_epi16(1 << 15);
let count = _mm256_set1_epi16(2);
let r = _mm256_sllv_epi16(a, count);
@@ -18426,7 +18345,7 @@ mod tests {
}
#[simd_test(enable = "avx512bw,avx512vl")]
- const fn test_mm256_mask_sllv_epi16() {
+ fn test_mm256_mask_sllv_epi16() {
let a = _mm256_set1_epi16(1 << 15);
let count = _mm256_set1_epi16(2);
let r = _mm256_mask_sllv_epi16(a, 0, a, count);
@@ -18437,7 +18356,7 @@ mod tests {
}
#[simd_test(enable = "avx512bw,avx512vl")]
- const fn test_mm256_maskz_sllv_epi16() {
+ fn test_mm256_maskz_sllv_epi16() {
let a = _mm256_set1_epi16(1 << 15);
let count = _mm256_set1_epi16(2);
let r = _mm256_maskz_sllv_epi16(0, a, count);
@@ -18448,7 +18367,7 @@ mod tests {
}
#[simd_test(enable = "avx512bw,avx512vl")]
- const fn test_mm_sllv_epi16() {
+ fn test_mm_sllv_epi16() {
let a = _mm_set1_epi16(1 << 15);
let count = _mm_set1_epi16(2);
let r = _mm_sllv_epi16(a, count);
@@ -18457,7 +18376,7 @@ mod tests {
}
#[simd_test(enable = "avx512bw,avx512vl")]
- const fn test_mm_mask_sllv_epi16() {
+ fn test_mm_mask_sllv_epi16() {
let a = _mm_set1_epi16(1 << 15);
let count = _mm_set1_epi16(2);
let r = _mm_mask_sllv_epi16(a, 0, a, count);
@@ -18468,7 +18387,7 @@ mod tests {
}
#[simd_test(enable = "avx512bw,avx512vl")]
- const fn test_mm_maskz_sllv_epi16() {
+ fn test_mm_maskz_sllv_epi16() {
let a = _mm_set1_epi16(1 << 15);
let count = _mm_set1_epi16(2);
let r = _mm_maskz_sllv_epi16(0, a, count);
@@ -18622,7 +18541,7 @@ mod tests {
}
#[simd_test(enable = "avx512bw")]
- const fn test_mm512_srlv_epi16() {
+ fn test_mm512_srlv_epi16() {
let a = _mm512_set1_epi16(1 << 1);
let count = _mm512_set1_epi16(2);
let r = _mm512_srlv_epi16(a, count);
@@ -18631,7 +18550,7 @@ mod tests {
}
#[simd_test(enable = "avx512bw")]
- const fn test_mm512_mask_srlv_epi16() {
+ fn test_mm512_mask_srlv_epi16() {
let a = _mm512_set1_epi16(1 << 1);
let count = _mm512_set1_epi16(2);
let r = _mm512_mask_srlv_epi16(a, 0, a, count);
@@ -18642,7 +18561,7 @@ mod tests {
}
#[simd_test(enable = "avx512bw")]
- const fn test_mm512_maskz_srlv_epi16() {
+ fn test_mm512_maskz_srlv_epi16() {
let a = _mm512_set1_epi16(1 << 1);
let count = _mm512_set1_epi16(2);
let r = _mm512_maskz_srlv_epi16(0, a, count);
@@ -18653,7 +18572,7 @@ mod tests {
}
#[simd_test(enable = "avx512bw,avx512vl")]
- const fn test_mm256_srlv_epi16() {
+ fn test_mm256_srlv_epi16() {
let a = _mm256_set1_epi16(1 << 1);
let count = _mm256_set1_epi16(2);
let r = _mm256_srlv_epi16(a, count);
@@ -18662,7 +18581,7 @@ mod tests {
}
#[simd_test(enable = "avx512bw,avx512vl")]
- const fn test_mm256_mask_srlv_epi16() {
+ fn test_mm256_mask_srlv_epi16() {
let a = _mm256_set1_epi16(1 << 1);
let count = _mm256_set1_epi16(2);
let r = _mm256_mask_srlv_epi16(a, 0, a, count);
@@ -18673,7 +18592,7 @@ mod tests {
}
#[simd_test(enable = "avx512bw,avx512vl")]
- const fn test_mm256_maskz_srlv_epi16() {
+ fn test_mm256_maskz_srlv_epi16() {
let a = _mm256_set1_epi16(1 << 1);
let count = _mm256_set1_epi16(2);
let r = _mm256_maskz_srlv_epi16(0, a, count);
@@ -18684,7 +18603,7 @@ mod tests {
}
#[simd_test(enable = "avx512bw,avx512vl")]
- const fn test_mm_srlv_epi16() {
+ fn test_mm_srlv_epi16() {
let a = _mm_set1_epi16(1 << 1);
let count = _mm_set1_epi16(2);
let r = _mm_srlv_epi16(a, count);
@@ -18693,7 +18612,7 @@ mod tests {
}
#[simd_test(enable = "avx512bw,avx512vl")]
- const fn test_mm_mask_srlv_epi16() {
+ fn test_mm_mask_srlv_epi16() {
let a = _mm_set1_epi16(1 << 1);
let count = _mm_set1_epi16(2);
let r = _mm_mask_srlv_epi16(a, 0, a, count);
@@ -18704,7 +18623,7 @@ mod tests {
}
#[simd_test(enable = "avx512bw,avx512vl")]
- const fn test_mm_maskz_srlv_epi16() {
+ fn test_mm_maskz_srlv_epi16() {
let a = _mm_set1_epi16(1 << 1);
let count = _mm_set1_epi16(2);
let r = _mm_maskz_srlv_epi16(0, a, count);
@@ -18858,7 +18777,7 @@ mod tests {
}
#[simd_test(enable = "avx512bw")]
- const fn test_mm512_srav_epi16() {
+ fn test_mm512_srav_epi16() {
let a = _mm512_set1_epi16(8);
let count = _mm512_set1_epi16(2);
let r = _mm512_srav_epi16(a, count);
@@ -18867,7 +18786,7 @@ mod tests {
}
#[simd_test(enable = "avx512bw")]
- const fn test_mm512_mask_srav_epi16() {
+ fn test_mm512_mask_srav_epi16() {
let a = _mm512_set1_epi16(8);
let count = _mm512_set1_epi16(2);
let r = _mm512_mask_srav_epi16(a, 0, a, count);
@@ -18878,7 +18797,7 @@ mod tests {
}
#[simd_test(enable = "avx512bw")]
- const fn test_mm512_maskz_srav_epi16() {
+ fn test_mm512_maskz_srav_epi16() {
let a = _mm512_set1_epi16(8);
let count = _mm512_set1_epi16(2);
let r = _mm512_maskz_srav_epi16(0, a, count);
@@ -18889,7 +18808,7 @@ mod tests {
}
#[simd_test(enable = "avx512bw,avx512vl")]
- const fn test_mm256_srav_epi16() {
+ fn test_mm256_srav_epi16() {
let a = _mm256_set1_epi16(8);
let count = _mm256_set1_epi16(2);
let r = _mm256_srav_epi16(a, count);
@@ -18898,7 +18817,7 @@ mod tests {
}
#[simd_test(enable = "avx512bw,avx512vl")]
- const fn test_mm256_mask_srav_epi16() {
+ fn test_mm256_mask_srav_epi16() {
let a = _mm256_set1_epi16(8);
let count = _mm256_set1_epi16(2);
let r = _mm256_mask_srav_epi16(a, 0, a, count);
@@ -18909,7 +18828,7 @@ mod tests {
}
#[simd_test(enable = "avx512bw,avx512vl")]
- const fn test_mm256_maskz_srav_epi16() {
+ fn test_mm256_maskz_srav_epi16() {
let a = _mm256_set1_epi16(8);
let count = _mm256_set1_epi16(2);
let r = _mm256_maskz_srav_epi16(0, a, count);
@@ -18920,7 +18839,7 @@ mod tests {
}
#[simd_test(enable = "avx512bw,avx512vl")]
- const fn test_mm_srav_epi16() {
+ fn test_mm_srav_epi16() {
let a = _mm_set1_epi16(8);
let count = _mm_set1_epi16(2);
let r = _mm_srav_epi16(a, count);
@@ -18929,7 +18848,7 @@ mod tests {
}
#[simd_test(enable = "avx512bw,avx512vl")]
- const fn test_mm_mask_srav_epi16() {
+ fn test_mm_mask_srav_epi16() {
let a = _mm_set1_epi16(8);
let count = _mm_set1_epi16(2);
let r = _mm_mask_srav_epi16(a, 0, a, count);
@@ -18940,7 +18859,7 @@ mod tests {
}
#[simd_test(enable = "avx512bw,avx512vl")]
- const fn test_mm_maskz_srav_epi16() {
+ fn test_mm_maskz_srav_epi16() {
let a = _mm_set1_epi16(8);
let count = _mm_set1_epi16(2);
let r = _mm_maskz_srav_epi16(0, a, count);
diff --git a/library/stdarch/crates/core_arch/src/x86/avx512f.rs b/library/stdarch/crates/core_arch/src/x86/avx512f.rs
index a9e498abf9b5a..5d9aecff64d84 100644
--- a/library/stdarch/crates/core_arch/src/x86/avx512f.rs
+++ b/library/stdarch/crates/core_arch/src/x86/avx512f.rs
@@ -13091,6 +13091,122 @@ pub const fn _mm512_maskz_cvtepu32_ps(k: __mmask16, a: __m512i) -> __m512 {
}
}
+/// Convert packed unsigned 32-bit integers in a to packed single-precision (32-bit) floating-point elements, and store the results in dst.
+///
+/// Due to an omission by Intel, these intrinsics are not documented in the Intrinsics Guide.
+/// Documentation on them can be found in the [Intel Software Development Manual](https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html).
+#[inline]
+#[target_feature(enable = "avx512f,avx512vl")]
+#[unstable(
+ feature = "stdarch_x86_avx512_vl_u32_to_f32_conversions",
+ issue = "161585"
+)]
+#[cfg_attr(test, assert_instr(vcvtudq2ps))]
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cvtepu32_ps(a: __m256i) -> __m256 {
+ unsafe {
+ let a = a.as_u32x8();
+ transmute::(simd_cast(a))
+ }
+}
+
+/// Convert packed unsigned 32-bit integers in a to packed single-precision (32-bit) floating-point elements, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+///
+/// Due to an omission by Intel, these intrinsics are not documented in the Intrinsics Guide.
+/// Documentation on them can be found in the [Intel Software Development Manual](https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html).
+#[inline]
+#[target_feature(enable = "avx512f,avx512vl")]
+#[unstable(
+ feature = "stdarch_x86_avx512_vl_u32_to_f32_conversions",
+ issue = "161585"
+)]
+#[cfg_attr(test, assert_instr(vcvtudq2ps))]
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cvtepu32_ps(src: __m256, k: __mmask8, a: __m256i) -> __m256 {
+ unsafe {
+ let convert = _mm256_cvtepu32_ps(a).as_f32x8();
+ transmute(simd_select_bitmask(k, convert, src.as_f32x8()))
+ }
+}
+
+/// Convert packed unsigned 32-bit integers in a to packed single-precision (32-bit) floating-point elements, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+///
+/// Due to an omission by Intel, these intrinsics are not documented in the Intrinsics Guide.
+/// Documentation on them can be found in the [Intel Software Development Manual](https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html).
+#[inline]
+#[target_feature(enable = "avx512f,avx512vl")]
+#[unstable(
+ feature = "stdarch_x86_avx512_vl_u32_to_f32_conversions",
+ issue = "161585"
+)]
+#[cfg_attr(test, assert_instr(vcvtudq2ps))]
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_cvtepu32_ps(k: __mmask8, a: __m256i) -> __m256 {
+ unsafe {
+ let convert = _mm256_cvtepu32_ps(a).as_f32x8();
+ transmute(simd_select_bitmask(k, convert, f32x8::ZERO))
+ }
+}
+
+/// Convert packed unsigned 32-bit integers in a to packed single-precision (32-bit) floating-point elements, and store the results in dst.
+///
+/// Due to an omission by Intel, these intrinsics are not documented in the Intrinsics Guide.
+/// Documentation on them can be found in the [Intel Software Development Manual](https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html).
+#[inline]
+#[target_feature(enable = "avx512f,avx512vl")]
+#[unstable(
+ feature = "stdarch_x86_avx512_vl_u32_to_f32_conversions",
+ issue = "161585"
+)]
+#[cfg_attr(test, assert_instr(vcvtudq2ps))]
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvtepu32_ps(a: __m128i) -> __m128 {
+ unsafe {
+ let a = a.as_u32x4();
+ transmute::(simd_cast(a))
+ }
+}
+
+/// Convert packed unsigned 32-bit integers in a to packed single-precision (32-bit) floating-point elements, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+/// Bits 4 through 7 of k are ignored.
+///
+/// Due to an omission by Intel, these intrinsics are not documented in the Intrinsics Guide.
+/// Documentation on them can be found in the [Intel Software Development Manual](https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html).
+#[inline]
+#[target_feature(enable = "avx512f,avx512vl")]
+#[unstable(
+ feature = "stdarch_x86_avx512_vl_u32_to_f32_conversions",
+ issue = "161585"
+)]
+#[cfg_attr(test, assert_instr(vcvtudq2ps))]
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cvtepu32_ps(src: __m128, k: __mmask8, a: __m128i) -> __m128 {
+ unsafe {
+ let convert = _mm_cvtepu32_ps(a).as_f32x4();
+ transmute(simd_select_bitmask(k, convert, src.as_f32x4()))
+ }
+}
+
+/// Convert packed unsigned 32-bit integers in a to packed single-precision (32-bit) floating-point elements, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+/// Bits 4 through 7 of k are ignored.
+///
+/// Due to an omission by Intel, these intrinsics are not documented in the Intrinsics Guide.
+/// Documentation on them can be found in the [Intel Software Development Manual](https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html).
+#[inline]
+#[target_feature(enable = "avx512f,avx512vl")]
+#[unstable(
+ feature = "stdarch_x86_avx512_vl_u32_to_f32_conversions",
+ issue = "161585"
+)]
+#[cfg_attr(test, assert_instr(vcvtudq2ps))]
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_cvtepu32_ps(k: __mmask8, a: __m128i) -> __m128 {
+ unsafe {
+ let convert = _mm_cvtepu32_ps(a).as_f32x4();
+ transmute(simd_select_bitmask(k, convert, f32x4::ZERO))
+ }
+}
+
/// Convert packed unsigned 32-bit integers in a to packed double-precision (64-bit) floating-point elements, and store the results in dst.
///
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtepu32_pd&expand=1580)
@@ -21532,14 +21648,8 @@ pub const fn _mm_maskz_srai_epi64(k: __mmask8, a: __m128i) -> _
#[target_feature(enable = "avx512f")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsravd))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm512_srav_epi32(a: __m512i, count: __m512i) -> __m512i {
- unsafe {
- let count = count.as_u32x16();
- let no_overflow: u32x16 = simd_lt(count, u32x16::splat(u32::BITS));
- let count = simd_select(no_overflow, transmute(count), i32x16::splat(31));
- simd_shr(a.as_i32x16(), count).as_m512i()
- }
+pub fn _mm512_srav_epi32(a: __m512i, count: __m512i) -> __m512i {
+ unsafe { transmute(vpsravd(a.as_i32x16(), count.as_i32x16())) }
}
/// Shift packed 32-bit integers in a right by the amount specified by the corresponding element in count while shifting in sign bits, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -21549,13 +21659,7 @@ pub const fn _mm512_srav_epi32(a: __m512i, count: __m512i) -> __m512i {
#[target_feature(enable = "avx512f")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsravd))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm512_mask_srav_epi32(
- src: __m512i,
- k: __mmask16,
- a: __m512i,
- count: __m512i,
-) -> __m512i {
+pub fn _mm512_mask_srav_epi32(src: __m512i, k: __mmask16, a: __m512i, count: __m512i) -> __m512i {
unsafe {
let shf = _mm512_srav_epi32(a, count).as_i32x16();
transmute(simd_select_bitmask(k, shf, src.as_i32x16()))
@@ -21569,8 +21673,7 @@ pub const fn _mm512_mask_srav_epi32(
#[target_feature(enable = "avx512f")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsravd))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm512_maskz_srav_epi32(k: __mmask16, a: __m512i, count: __m512i) -> __m512i {
+pub fn _mm512_maskz_srav_epi32(k: __mmask16, a: __m512i, count: __m512i) -> __m512i {
unsafe {
let shf = _mm512_srav_epi32(a, count).as_i32x16();
transmute(simd_select_bitmask(k, shf, i32x16::ZERO))
@@ -21584,13 +21687,7 @@ pub const fn _mm512_maskz_srav_epi32(k: __mmask16, a: __m512i, count: __m512i) -
#[target_feature(enable = "avx512f,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsravd))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm256_mask_srav_epi32(
- src: __m256i,
- k: __mmask8,
- a: __m256i,
- count: __m256i,
-) -> __m256i {
+pub fn _mm256_mask_srav_epi32(src: __m256i, k: __mmask8, a: __m256i, count: __m256i) -> __m256i {
unsafe {
let shf = _mm256_srav_epi32(a, count).as_i32x8();
transmute(simd_select_bitmask(k, shf, src.as_i32x8()))
@@ -21604,8 +21701,7 @@ pub const fn _mm256_mask_srav_epi32(
#[target_feature(enable = "avx512f,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsravd))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm256_maskz_srav_epi32(k: __mmask8, a: __m256i, count: __m256i) -> __m256i {
+pub fn _mm256_maskz_srav_epi32(k: __mmask8, a: __m256i, count: __m256i) -> __m256i {
unsafe {
let shf = _mm256_srav_epi32(a, count).as_i32x8();
transmute(simd_select_bitmask(k, shf, i32x8::ZERO))
@@ -21619,8 +21715,7 @@ pub const fn _mm256_maskz_srav_epi32(k: __mmask8, a: __m256i, count: __m256i) ->
#[target_feature(enable = "avx512f,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsravd))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm_mask_srav_epi32(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
+pub fn _mm_mask_srav_epi32(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
unsafe {
let shf = _mm_srav_epi32(a, count).as_i32x4();
transmute(simd_select_bitmask(k, shf, src.as_i32x4()))
@@ -21634,8 +21729,7 @@ pub const fn _mm_mask_srav_epi32(src: __m128i, k: __mmask8, a: __m128i, count: _
#[target_feature(enable = "avx512f,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsravd))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm_maskz_srav_epi32(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
+pub fn _mm_maskz_srav_epi32(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
unsafe {
let shf = _mm_srav_epi32(a, count).as_i32x4();
transmute(simd_select_bitmask(k, shf, i32x4::ZERO))
@@ -21649,14 +21743,8 @@ pub const fn _mm_maskz_srav_epi32(k: __mmask8, a: __m128i, count: __m128i) -> __
#[target_feature(enable = "avx512f")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsravq))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm512_srav_epi64(a: __m512i, count: __m512i) -> __m512i {
- unsafe {
- let count = count.as_u64x8();
- let no_overflow: u64x8 = simd_lt(count, u64x8::splat(u64::BITS as u64));
- let count = simd_select(no_overflow, transmute(count), i64x8::splat(63));
- simd_shr(a.as_i64x8(), count).as_m512i()
- }
+pub fn _mm512_srav_epi64(a: __m512i, count: __m512i) -> __m512i {
+ unsafe { transmute(vpsravq(a.as_i64x8(), count.as_i64x8())) }
}
/// Shift packed 64-bit integers in a right by the amount specified by the corresponding element in count while shifting in sign bits, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -21666,13 +21754,7 @@ pub const fn _mm512_srav_epi64(a: __m512i, count: __m512i) -> __m512i {
#[target_feature(enable = "avx512f")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsravq))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm512_mask_srav_epi64(
- src: __m512i,
- k: __mmask8,
- a: __m512i,
- count: __m512i,
-) -> __m512i {
+pub fn _mm512_mask_srav_epi64(src: __m512i, k: __mmask8, a: __m512i, count: __m512i) -> __m512i {
unsafe {
let shf = _mm512_srav_epi64(a, count).as_i64x8();
transmute(simd_select_bitmask(k, shf, src.as_i64x8()))
@@ -21686,8 +21768,7 @@ pub const fn _mm512_mask_srav_epi64(
#[target_feature(enable = "avx512f")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsravq))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm512_maskz_srav_epi64(k: __mmask8, a: __m512i, count: __m512i) -> __m512i {
+pub fn _mm512_maskz_srav_epi64(k: __mmask8, a: __m512i, count: __m512i) -> __m512i {
unsafe {
let shf = _mm512_srav_epi64(a, count).as_i64x8();
transmute(simd_select_bitmask(k, shf, i64x8::ZERO))
@@ -21701,14 +21782,8 @@ pub const fn _mm512_maskz_srav_epi64(k: __mmask8, a: __m512i, count: __m512i) ->
#[target_feature(enable = "avx512f,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsravq))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm256_srav_epi64(a: __m256i, count: __m256i) -> __m256i {
- unsafe {
- let count = count.as_u64x4();
- let no_overflow: u64x4 = simd_lt(count, u64x4::splat(u64::BITS as u64));
- let count = simd_select(no_overflow, transmute(count), i64x4::splat(63));
- simd_shr(a.as_i64x4(), count).as_m256i()
- }
+pub fn _mm256_srav_epi64(a: __m256i, count: __m256i) -> __m256i {
+ unsafe { transmute(vpsravq256(a.as_i64x4(), count.as_i64x4())) }
}
/// Shift packed 64-bit integers in a right by the amount specified by the corresponding element in count while shifting in sign bits, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -21718,13 +21793,7 @@ pub const fn _mm256_srav_epi64(a: __m256i, count: __m256i) -> __m256i {
#[target_feature(enable = "avx512f,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsravq))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm256_mask_srav_epi64(
- src: __m256i,
- k: __mmask8,
- a: __m256i,
- count: __m256i,
-) -> __m256i {
+pub fn _mm256_mask_srav_epi64(src: __m256i, k: __mmask8, a: __m256i, count: __m256i) -> __m256i {
unsafe {
let shf = _mm256_srav_epi64(a, count).as_i64x4();
transmute(simd_select_bitmask(k, shf, src.as_i64x4()))
@@ -21738,8 +21807,7 @@ pub const fn _mm256_mask_srav_epi64(
#[target_feature(enable = "avx512f,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsravq))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm256_maskz_srav_epi64(k: __mmask8, a: __m256i, count: __m256i) -> __m256i {
+pub fn _mm256_maskz_srav_epi64(k: __mmask8, a: __m256i, count: __m256i) -> __m256i {
unsafe {
let shf = _mm256_srav_epi64(a, count).as_i64x4();
transmute(simd_select_bitmask(k, shf, i64x4::ZERO))
@@ -21753,14 +21821,8 @@ pub const fn _mm256_maskz_srav_epi64(k: __mmask8, a: __m256i, count: __m256i) ->
#[target_feature(enable = "avx512f,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsravq))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm_srav_epi64(a: __m128i, count: __m128i) -> __m128i {
- unsafe {
- let count = count.as_u64x2();
- let no_overflow: u64x2 = simd_lt(count, u64x2::splat(u64::BITS as u64));
- let count = simd_select(no_overflow, transmute(count), i64x2::splat(63));
- simd_shr(a.as_i64x2(), count).as_m128i()
- }
+pub fn _mm_srav_epi64(a: __m128i, count: __m128i) -> __m128i {
+ unsafe { transmute(vpsravq128(a.as_i64x2(), count.as_i64x2())) }
}
/// Shift packed 64-bit integers in a right by the amount specified by the corresponding element in count while shifting in sign bits, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -21770,8 +21832,7 @@ pub const fn _mm_srav_epi64(a: __m128i, count: __m128i) -> __m128i {
#[target_feature(enable = "avx512f,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsravq))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm_mask_srav_epi64(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
+pub fn _mm_mask_srav_epi64(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
unsafe {
let shf = _mm_srav_epi64(a, count).as_i64x2();
transmute(simd_select_bitmask(k, shf, src.as_i64x2()))
@@ -21785,8 +21846,7 @@ pub const fn _mm_mask_srav_epi64(src: __m128i, k: __mmask8, a: __m128i, count: _
#[target_feature(enable = "avx512f,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsravq))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm_maskz_srav_epi64(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
+pub fn _mm_maskz_srav_epi64(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
unsafe {
let shf = _mm_srav_epi64(a, count).as_i64x2();
transmute(simd_select_bitmask(k, shf, i64x2::ZERO))
@@ -22376,14 +22436,8 @@ pub const fn _mm_maskz_rorv_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128
#[target_feature(enable = "avx512f")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsllvd))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm512_sllv_epi32(a: __m512i, count: __m512i) -> __m512i {
- unsafe {
- let count = count.as_u32x16();
- let no_overflow: u32x16 = simd_lt(count, u32x16::splat(u32::BITS));
- let count = simd_select(no_overflow, count, u32x16::ZERO);
- simd_select(no_overflow, simd_shl(a.as_u32x16(), count), u32x16::ZERO).as_m512i()
- }
+pub fn _mm512_sllv_epi32(a: __m512i, count: __m512i) -> __m512i {
+ unsafe { transmute(vpsllvd(a.as_i32x16(), count.as_i32x16())) }
}
/// Shift packed 32-bit integers in a left by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -22393,13 +22447,7 @@ pub const fn _mm512_sllv_epi32(a: __m512i, count: __m512i) -> __m512i {
#[target_feature(enable = "avx512f")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsllvd))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm512_mask_sllv_epi32(
- src: __m512i,
- k: __mmask16,
- a: __m512i,
- count: __m512i,
-) -> __m512i {
+pub fn _mm512_mask_sllv_epi32(src: __m512i, k: __mmask16, a: __m512i, count: __m512i) -> __m512i {
unsafe {
let shf = _mm512_sllv_epi32(a, count).as_i32x16();
transmute(simd_select_bitmask(k, shf, src.as_i32x16()))
@@ -22413,8 +22461,7 @@ pub const fn _mm512_mask_sllv_epi32(
#[target_feature(enable = "avx512f")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsllvd))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm512_maskz_sllv_epi32(k: __mmask16, a: __m512i, count: __m512i) -> __m512i {
+pub fn _mm512_maskz_sllv_epi32(k: __mmask16, a: __m512i, count: __m512i) -> __m512i {
unsafe {
let shf = _mm512_sllv_epi32(a, count).as_i32x16();
transmute(simd_select_bitmask(k, shf, i32x16::ZERO))
@@ -22428,13 +22475,7 @@ pub const fn _mm512_maskz_sllv_epi32(k: __mmask16, a: __m512i, count: __m512i) -
#[target_feature(enable = "avx512f,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsllvd))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm256_mask_sllv_epi32(
- src: __m256i,
- k: __mmask8,
- a: __m256i,
- count: __m256i,
-) -> __m256i {
+pub fn _mm256_mask_sllv_epi32(src: __m256i, k: __mmask8, a: __m256i, count: __m256i) -> __m256i {
unsafe {
let shf = _mm256_sllv_epi32(a, count).as_i32x8();
transmute(simd_select_bitmask(k, shf, src.as_i32x8()))
@@ -22448,8 +22489,7 @@ pub const fn _mm256_mask_sllv_epi32(
#[target_feature(enable = "avx512f,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsllvd))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm256_maskz_sllv_epi32(k: __mmask8, a: __m256i, count: __m256i) -> __m256i {
+pub fn _mm256_maskz_sllv_epi32(k: __mmask8, a: __m256i, count: __m256i) -> __m256i {
unsafe {
let shf = _mm256_sllv_epi32(a, count).as_i32x8();
transmute(simd_select_bitmask(k, shf, i32x8::ZERO))
@@ -22463,8 +22503,7 @@ pub const fn _mm256_maskz_sllv_epi32(k: __mmask8, a: __m256i, count: __m256i) ->
#[target_feature(enable = "avx512f,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsllvd))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm_mask_sllv_epi32(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
+pub fn _mm_mask_sllv_epi32(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
unsafe {
let shf = _mm_sllv_epi32(a, count).as_i32x4();
transmute(simd_select_bitmask(k, shf, src.as_i32x4()))
@@ -22478,8 +22517,7 @@ pub const fn _mm_mask_sllv_epi32(src: __m128i, k: __mmask8, a: __m128i, count: _
#[target_feature(enable = "avx512f,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsllvd))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm_maskz_sllv_epi32(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
+pub fn _mm_maskz_sllv_epi32(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
unsafe {
let shf = _mm_sllv_epi32(a, count).as_i32x4();
transmute(simd_select_bitmask(k, shf, i32x4::ZERO))
@@ -22493,14 +22531,8 @@ pub const fn _mm_maskz_sllv_epi32(k: __mmask8, a: __m128i, count: __m128i) -> __
#[target_feature(enable = "avx512f")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsrlvd))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm512_srlv_epi32(a: __m512i, count: __m512i) -> __m512i {
- unsafe {
- let count = count.as_u32x16();
- let no_overflow: u32x16 = simd_lt(count, u32x16::splat(u32::BITS));
- let count = simd_select(no_overflow, count, u32x16::ZERO);
- simd_select(no_overflow, simd_shr(a.as_u32x16(), count), u32x16::ZERO).as_m512i()
- }
+pub fn _mm512_srlv_epi32(a: __m512i, count: __m512i) -> __m512i {
+ unsafe { transmute(vpsrlvd(a.as_i32x16(), count.as_i32x16())) }
}
/// Shift packed 32-bit integers in a right by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -22510,13 +22542,7 @@ pub const fn _mm512_srlv_epi32(a: __m512i, count: __m512i) -> __m512i {
#[target_feature(enable = "avx512f")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsrlvd))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm512_mask_srlv_epi32(
- src: __m512i,
- k: __mmask16,
- a: __m512i,
- count: __m512i,
-) -> __m512i {
+pub fn _mm512_mask_srlv_epi32(src: __m512i, k: __mmask16, a: __m512i, count: __m512i) -> __m512i {
unsafe {
let shf = _mm512_srlv_epi32(a, count).as_i32x16();
transmute(simd_select_bitmask(k, shf, src.as_i32x16()))
@@ -22530,8 +22556,7 @@ pub const fn _mm512_mask_srlv_epi32(
#[target_feature(enable = "avx512f")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsrlvd))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm512_maskz_srlv_epi32(k: __mmask16, a: __m512i, count: __m512i) -> __m512i {
+pub fn _mm512_maskz_srlv_epi32(k: __mmask16, a: __m512i, count: __m512i) -> __m512i {
unsafe {
let shf = _mm512_srlv_epi32(a, count).as_i32x16();
transmute(simd_select_bitmask(k, shf, i32x16::ZERO))
@@ -22545,13 +22570,7 @@ pub const fn _mm512_maskz_srlv_epi32(k: __mmask16, a: __m512i, count: __m512i) -
#[target_feature(enable = "avx512f,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsrlvd))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm256_mask_srlv_epi32(
- src: __m256i,
- k: __mmask8,
- a: __m256i,
- count: __m256i,
-) -> __m256i {
+pub fn _mm256_mask_srlv_epi32(src: __m256i, k: __mmask8, a: __m256i, count: __m256i) -> __m256i {
unsafe {
let shf = _mm256_srlv_epi32(a, count).as_i32x8();
transmute(simd_select_bitmask(k, shf, src.as_i32x8()))
@@ -22565,8 +22584,7 @@ pub const fn _mm256_mask_srlv_epi32(
#[target_feature(enable = "avx512f,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsrlvd))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm256_maskz_srlv_epi32(k: __mmask8, a: __m256i, count: __m256i) -> __m256i {
+pub fn _mm256_maskz_srlv_epi32(k: __mmask8, a: __m256i, count: __m256i) -> __m256i {
unsafe {
let shf = _mm256_srlv_epi32(a, count).as_i32x8();
transmute(simd_select_bitmask(k, shf, i32x8::ZERO))
@@ -22580,8 +22598,7 @@ pub const fn _mm256_maskz_srlv_epi32(k: __mmask8, a: __m256i, count: __m256i) ->
#[target_feature(enable = "avx512f,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsrlvd))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm_mask_srlv_epi32(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
+pub fn _mm_mask_srlv_epi32(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
unsafe {
let shf = _mm_srlv_epi32(a, count).as_i32x4();
transmute(simd_select_bitmask(k, shf, src.as_i32x4()))
@@ -22595,8 +22612,7 @@ pub const fn _mm_mask_srlv_epi32(src: __m128i, k: __mmask8, a: __m128i, count: _
#[target_feature(enable = "avx512f,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsrlvd))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm_maskz_srlv_epi32(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
+pub fn _mm_maskz_srlv_epi32(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
unsafe {
let shf = _mm_srlv_epi32(a, count).as_i32x4();
transmute(simd_select_bitmask(k, shf, i32x4::ZERO))
@@ -22610,14 +22626,8 @@ pub const fn _mm_maskz_srlv_epi32(k: __mmask8, a: __m128i, count: __m128i) -> __
#[target_feature(enable = "avx512f")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsllvq))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm512_sllv_epi64(a: __m512i, count: __m512i) -> __m512i {
- unsafe {
- let count = count.as_u64x8();
- let no_overflow: u64x8 = simd_lt(count, u64x8::splat(u64::BITS as u64));
- let count = simd_select(no_overflow, count, u64x8::ZERO);
- simd_select(no_overflow, simd_shl(a.as_u64x8(), count), u64x8::ZERO).as_m512i()
- }
+pub fn _mm512_sllv_epi64(a: __m512i, count: __m512i) -> __m512i {
+ unsafe { transmute(vpsllvq(a.as_i64x8(), count.as_i64x8())) }
}
/// Shift packed 64-bit integers in a left by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -22627,13 +22637,7 @@ pub const fn _mm512_sllv_epi64(a: __m512i, count: __m512i) -> __m512i {
#[target_feature(enable = "avx512f")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsllvq))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm512_mask_sllv_epi64(
- src: __m512i,
- k: __mmask8,
- a: __m512i,
- count: __m512i,
-) -> __m512i {
+pub fn _mm512_mask_sllv_epi64(src: __m512i, k: __mmask8, a: __m512i, count: __m512i) -> __m512i {
unsafe {
let shf = _mm512_sllv_epi64(a, count).as_i64x8();
transmute(simd_select_bitmask(k, shf, src.as_i64x8()))
@@ -22647,8 +22651,7 @@ pub const fn _mm512_mask_sllv_epi64(
#[target_feature(enable = "avx512f")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsllvq))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm512_maskz_sllv_epi64(k: __mmask8, a: __m512i, count: __m512i) -> __m512i {
+pub fn _mm512_maskz_sllv_epi64(k: __mmask8, a: __m512i, count: __m512i) -> __m512i {
unsafe {
let shf = _mm512_sllv_epi64(a, count).as_i64x8();
transmute(simd_select_bitmask(k, shf, i64x8::ZERO))
@@ -22662,13 +22665,7 @@ pub const fn _mm512_maskz_sllv_epi64(k: __mmask8, a: __m512i, count: __m512i) ->
#[target_feature(enable = "avx512f,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsllvq))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm256_mask_sllv_epi64(
- src: __m256i,
- k: __mmask8,
- a: __m256i,
- count: __m256i,
-) -> __m256i {
+pub fn _mm256_mask_sllv_epi64(src: __m256i, k: __mmask8, a: __m256i, count: __m256i) -> __m256i {
unsafe {
let shf = _mm256_sllv_epi64(a, count).as_i64x4();
transmute(simd_select_bitmask(k, shf, src.as_i64x4()))
@@ -22682,8 +22679,7 @@ pub const fn _mm256_mask_sllv_epi64(
#[target_feature(enable = "avx512f,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsllvq))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm256_maskz_sllv_epi64(k: __mmask8, a: __m256i, count: __m256i) -> __m256i {
+pub fn _mm256_maskz_sllv_epi64(k: __mmask8, a: __m256i, count: __m256i) -> __m256i {
unsafe {
let shf = _mm256_sllv_epi64(a, count).as_i64x4();
transmute(simd_select_bitmask(k, shf, i64x4::ZERO))
@@ -22697,8 +22693,7 @@ pub const fn _mm256_maskz_sllv_epi64(k: __mmask8, a: __m256i, count: __m256i) ->
#[target_feature(enable = "avx512f,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsllvq))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm_mask_sllv_epi64(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
+pub fn _mm_mask_sllv_epi64(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
unsafe {
let shf = _mm_sllv_epi64(a, count).as_i64x2();
transmute(simd_select_bitmask(k, shf, src.as_i64x2()))
@@ -22712,8 +22707,7 @@ pub const fn _mm_mask_sllv_epi64(src: __m128i, k: __mmask8, a: __m128i, count: _
#[target_feature(enable = "avx512f,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsllvq))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm_maskz_sllv_epi64(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
+pub fn _mm_maskz_sllv_epi64(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
unsafe {
let shf = _mm_sllv_epi64(a, count).as_i64x2();
transmute(simd_select_bitmask(k, shf, i64x2::ZERO))
@@ -22727,14 +22721,8 @@ pub const fn _mm_maskz_sllv_epi64(k: __mmask8, a: __m128i, count: __m128i) -> __
#[target_feature(enable = "avx512f")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsrlvq))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm512_srlv_epi64(a: __m512i, count: __m512i) -> __m512i {
- unsafe {
- let count = count.as_u64x8();
- let no_overflow: u64x8 = simd_lt(count, u64x8::splat(u64::BITS as u64));
- let count = simd_select(no_overflow, count, u64x8::ZERO);
- simd_select(no_overflow, simd_shr(a.as_u64x8(), count), u64x8::ZERO).as_m512i()
- }
+pub fn _mm512_srlv_epi64(a: __m512i, count: __m512i) -> __m512i {
+ unsafe { transmute(vpsrlvq(a.as_i64x8(), count.as_i64x8())) }
}
/// Shift packed 64-bit integers in a right by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -22744,13 +22732,7 @@ pub const fn _mm512_srlv_epi64(a: __m512i, count: __m512i) -> __m512i {
#[target_feature(enable = "avx512f")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsrlvq))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm512_mask_srlv_epi64(
- src: __m512i,
- k: __mmask8,
- a: __m512i,
- count: __m512i,
-) -> __m512i {
+pub fn _mm512_mask_srlv_epi64(src: __m512i, k: __mmask8, a: __m512i, count: __m512i) -> __m512i {
unsafe {
let shf = _mm512_srlv_epi64(a, count).as_i64x8();
transmute(simd_select_bitmask(k, shf, src.as_i64x8()))
@@ -22764,8 +22746,7 @@ pub const fn _mm512_mask_srlv_epi64(
#[target_feature(enable = "avx512f")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsrlvq))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm512_maskz_srlv_epi64(k: __mmask8, a: __m512i, count: __m512i) -> __m512i {
+pub fn _mm512_maskz_srlv_epi64(k: __mmask8, a: __m512i, count: __m512i) -> __m512i {
unsafe {
let shf = _mm512_srlv_epi64(a, count).as_i64x8();
transmute(simd_select_bitmask(k, shf, i64x8::ZERO))
@@ -22779,13 +22760,7 @@ pub const fn _mm512_maskz_srlv_epi64(k: __mmask8, a: __m512i, count: __m512i) ->
#[target_feature(enable = "avx512f,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsrlvq))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm256_mask_srlv_epi64(
- src: __m256i,
- k: __mmask8,
- a: __m256i,
- count: __m256i,
-) -> __m256i {
+pub fn _mm256_mask_srlv_epi64(src: __m256i, k: __mmask8, a: __m256i, count: __m256i) -> __m256i {
unsafe {
let shf = _mm256_srlv_epi64(a, count).as_i64x4();
transmute(simd_select_bitmask(k, shf, src.as_i64x4()))
@@ -22799,8 +22774,7 @@ pub const fn _mm256_mask_srlv_epi64(
#[target_feature(enable = "avx512f,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsrlvq))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm256_maskz_srlv_epi64(k: __mmask8, a: __m256i, count: __m256i) -> __m256i {
+pub fn _mm256_maskz_srlv_epi64(k: __mmask8, a: __m256i, count: __m256i) -> __m256i {
unsafe {
let shf = _mm256_srlv_epi64(a, count).as_i64x4();
transmute(simd_select_bitmask(k, shf, i64x4::ZERO))
@@ -22814,8 +22788,7 @@ pub const fn _mm256_maskz_srlv_epi64(k: __mmask8, a: __m256i, count: __m256i) ->
#[target_feature(enable = "avx512f,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsrlvq))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm_mask_srlv_epi64(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
+pub fn _mm_mask_srlv_epi64(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
unsafe {
let shf = _mm_srlv_epi64(a, count).as_i64x2();
transmute(simd_select_bitmask(k, shf, src.as_i64x2()))
@@ -22829,8 +22802,7 @@ pub const fn _mm_mask_srlv_epi64(src: __m128i, k: __mmask8, a: __m128i, count: _
#[target_feature(enable = "avx512f,avx512vl")]
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
#[cfg_attr(test, assert_instr(vpsrlvq))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm_maskz_srlv_epi64(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
+pub fn _mm_maskz_srlv_epi64(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
unsafe {
let shf = _mm_srlv_epi64(a, count).as_i64x2();
transmute(simd_select_bitmask(k, shf, i64x2::ZERO))
@@ -44768,6 +44740,15 @@ unsafe extern "llvm-intrinsic" {
#[link_name = "llvm.x86.avx512.mask.cmp.pd.128"]
fn vcmppd128(a: f64x2, b: f64x2, op: i32, m: i8) -> i8;
+ #[link_name = "llvm.x86.avx512.psllv.d.512"]
+ fn vpsllvd(a: i32x16, b: i32x16) -> i32x16;
+ #[link_name = "llvm.x86.avx512.psrlv.d.512"]
+ fn vpsrlvd(a: i32x16, b: i32x16) -> i32x16;
+ #[link_name = "llvm.x86.avx512.psllv.q.512"]
+ fn vpsllvq(a: i64x8, b: i64x8) -> i64x8;
+ #[link_name = "llvm.x86.avx512.psrlv.q.512"]
+ fn vpsrlvq(a: i64x8, b: i64x8) -> i64x8;
+
#[link_name = "llvm.x86.avx512.psll.d.512"]
fn vpslld(a: i32x16, count: i32x4) -> i32x16;
#[link_name = "llvm.x86.avx512.psrl.d.512"]
@@ -44787,6 +44768,16 @@ unsafe extern "llvm-intrinsic" {
#[link_name = "llvm.x86.avx512.psra.q.128"]
fn vpsraq128(a: i64x2, count: i64x2) -> i64x2;
+ #[link_name = "llvm.x86.avx512.psrav.d.512"]
+ fn vpsravd(a: i32x16, count: i32x16) -> i32x16;
+
+ #[link_name = "llvm.x86.avx512.psrav.q.512"]
+ fn vpsravq(a: i64x8, count: i64x8) -> i64x8;
+ #[link_name = "llvm.x86.avx512.psrav.q.256"]
+ fn vpsravq256(a: i64x4, count: i64x4) -> i64x4;
+ #[link_name = "llvm.x86.avx512.psrav.q.128"]
+ fn vpsravq128(a: i64x2, count: i64x2) -> i64x2;
+
#[link_name = "llvm.x86.avx512.vpermilvar.ps.512"]
fn vpermilps(a: f32x16, b: i32x16) -> f32x16;
#[link_name = "llvm.x86.avx512.vpermilvar.pd.512"]
@@ -50036,6 +50027,65 @@ mod tests {
assert_eq_m512(r, e);
}
+ #[simd_test(enable = "avx512f,avx512vl")]
+ const fn test_mm256_cvtepu32_ps() {
+ let a = _mm256_set_epi32(-1, i32::MIN, 16_777_217, 16_777_216, 4, 3, 2, 1);
+ let r = _mm256_cvtepu32_ps(a);
+ let e = _mm256_set_ps(
+ 4_294_967_296.,
+ 2_147_483_648.,
+ 16_777_216.,
+ 16_777_216.,
+ 4.,
+ 3.,
+ 2.,
+ 1.,
+ );
+ assert_eq_m256(r, e);
+ }
+
+ #[simd_test(enable = "avx512f,avx512vl")]
+ const fn test_mm256_mask_cvtepu32_ps() {
+ let a = _mm256_set_epi32(-1, i32::MIN, 6, 5, 4, 3, 2, 1);
+ let src = _mm256_set1_ps(-1.);
+ let r = _mm256_mask_cvtepu32_ps(src, 0b10101010, a);
+ let e = _mm256_set_ps(4_294_967_296., -1., 6., -1., 4., -1., 2., -1.);
+ assert_eq_m256(r, e);
+ }
+
+ #[simd_test(enable = "avx512f,avx512vl")]
+ const fn test_mm256_maskz_cvtepu32_ps() {
+ let a = _mm256_set_epi32(-1, i32::MIN, 6, 5, 4, 3, 2, 1);
+ let r = _mm256_maskz_cvtepu32_ps(0b01010101, a);
+ let e = _mm256_set_ps(0., 2_147_483_648., 0., 5., 0., 3., 0., 1.);
+ assert_eq_m256(r, e);
+ }
+
+ #[simd_test(enable = "avx512f,avx512vl")]
+ const fn test_mm_cvtepu32_ps() {
+ let a = _mm_set_epi32(-1, i32::MIN, 1, 0);
+ let r = _mm_cvtepu32_ps(a);
+ let e = _mm_set_ps(4_294_967_296., 2_147_483_648., 1., 0.);
+ assert_eq_m128(r, e);
+ }
+
+ #[simd_test(enable = "avx512f,avx512vl")]
+ const fn test_mm_mask_cvtepu32_ps() {
+ let a = _mm_set_epi32(-1, i32::MIN, 2, 1);
+ let src = _mm_set1_ps(-1.);
+ let r = _mm_mask_cvtepu32_ps(src, 0b11110101, a);
+ let e = _mm_set_ps(-1., 2_147_483_648., -1., 1.);
+ assert_eq_m128(r, e);
+ }
+
+ #[simd_test(enable = "avx512f,avx512vl")]
+ const fn test_mm_maskz_cvtepu32_ps() {
+ let a = _mm_set_epi32(-1, i32::MIN, 2, 1);
+ let r = _mm_maskz_cvtepu32_ps(0b11111010, a);
+ let e = _mm_set_ps(4_294_967_296., 0., 2., 0.);
+ assert_eq_m128(r, e);
+ }
+
#[simd_test(enable = "avx512f")]
const fn test_mm512_cvtepi32_epi16() {
let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -54493,7 +54543,7 @@ mod tests {
}
#[simd_test(enable = "avx512f")]
- const fn test_mm512_sllv_epi32() {
+ fn test_mm512_sllv_epi32() {
let a = _mm512_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
let count = _mm512_set1_epi32(1);
let r = _mm512_sllv_epi32(a, count);
@@ -54502,7 +54552,7 @@ mod tests {
}
#[simd_test(enable = "avx512f")]
- const fn test_mm512_mask_sllv_epi32() {
+ fn test_mm512_mask_sllv_epi32() {
let a = _mm512_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
let count = _mm512_set1_epi32(1);
let r = _mm512_mask_sllv_epi32(a, 0, a, count);
@@ -54513,7 +54563,7 @@ mod tests {
}
#[simd_test(enable = "avx512f")]
- const fn test_mm512_maskz_sllv_epi32() {
+ fn test_mm512_maskz_sllv_epi32() {
let a = _mm512_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 << 31);
let count = _mm512_set_epi32(0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
let r = _mm512_maskz_sllv_epi32(0, a, count);
@@ -54524,7 +54574,7 @@ mod tests {
}
#[simd_test(enable = "avx512f,avx512vl")]
- const fn test_mm256_mask_sllv_epi32() {
+ fn test_mm256_mask_sllv_epi32() {
let a = _mm256_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1);
let count = _mm256_set1_epi32(1);
let r = _mm256_mask_sllv_epi32(a, 0, a, count);
@@ -54535,7 +54585,7 @@ mod tests {
}
#[simd_test(enable = "avx512f,avx512vl")]
- const fn test_mm256_maskz_sllv_epi32() {
+ fn test_mm256_maskz_sllv_epi32() {
let a = _mm256_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1);
let count = _mm256_set1_epi32(1);
let r = _mm256_maskz_sllv_epi32(0, a, count);
@@ -54546,7 +54596,7 @@ mod tests {
}
#[simd_test(enable = "avx512f,avx512vl")]
- const fn test_mm_mask_sllv_epi32() {
+ fn test_mm_mask_sllv_epi32() {
let a = _mm_set_epi32(1 << 31, 1, 1, 1);
let count = _mm_set1_epi32(1);
let r = _mm_mask_sllv_epi32(a, 0, a, count);
@@ -54557,7 +54607,7 @@ mod tests {
}
#[simd_test(enable = "avx512f,avx512vl")]
- const fn test_mm_maskz_sllv_epi32() {
+ fn test_mm_maskz_sllv_epi32() {
let a = _mm_set_epi32(1 << 31, 1, 1, 1);
let count = _mm_set1_epi32(1);
let r = _mm_maskz_sllv_epi32(0, a, count);
@@ -54568,7 +54618,7 @@ mod tests {
}
#[simd_test(enable = "avx512f")]
- const fn test_mm512_srlv_epi32() {
+ fn test_mm512_srlv_epi32() {
let a = _mm512_set_epi32(0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
let count = _mm512_set1_epi32(1);
let r = _mm512_srlv_epi32(a, count);
@@ -54577,7 +54627,7 @@ mod tests {
}
#[simd_test(enable = "avx512f")]
- const fn test_mm512_mask_srlv_epi32() {
+ fn test_mm512_mask_srlv_epi32() {
let a = _mm512_set_epi32(0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
let count = _mm512_set1_epi32(1);
let r = _mm512_mask_srlv_epi32(a, 0, a, count);
@@ -54588,7 +54638,7 @@ mod tests {
}
#[simd_test(enable = "avx512f")]
- const fn test_mm512_maskz_srlv_epi32() {
+ fn test_mm512_maskz_srlv_epi32() {
let a = _mm512_set_epi32(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 0);
let count = _mm512_set_epi32(0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
let r = _mm512_maskz_srlv_epi32(0, a, count);
@@ -54599,7 +54649,7 @@ mod tests {
}
#[simd_test(enable = "avx512f,avx512vl")]
- const fn test_mm256_mask_srlv_epi32() {
+ fn test_mm256_mask_srlv_epi32() {
let a = _mm256_set_epi32(1 << 5, 0, 0, 0, 0, 0, 0, 0);
let count = _mm256_set1_epi32(1);
let r = _mm256_mask_srlv_epi32(a, 0, a, count);
@@ -54610,7 +54660,7 @@ mod tests {
}
#[simd_test(enable = "avx512f,avx512vl")]
- const fn test_mm256_maskz_srlv_epi32() {
+ fn test_mm256_maskz_srlv_epi32() {
let a = _mm256_set_epi32(1 << 5, 0, 0, 0, 0, 0, 0, 0);
let count = _mm256_set1_epi32(1);
let r = _mm256_maskz_srlv_epi32(0, a, count);
@@ -54621,7 +54671,7 @@ mod tests {
}
#[simd_test(enable = "avx512f,avx512vl")]
- const fn test_mm_mask_srlv_epi32() {
+ fn test_mm_mask_srlv_epi32() {
let a = _mm_set_epi32(1 << 5, 0, 0, 0);
let count = _mm_set1_epi32(1);
let r = _mm_mask_srlv_epi32(a, 0, a, count);
@@ -54632,7 +54682,7 @@ mod tests {
}
#[simd_test(enable = "avx512f,avx512vl")]
- const fn test_mm_maskz_srlv_epi32() {
+ fn test_mm_maskz_srlv_epi32() {
let a = _mm_set_epi32(1 << 5, 0, 0, 0);
let count = _mm_set1_epi32(1);
let r = _mm_maskz_srlv_epi32(0, a, count);
@@ -54916,7 +54966,7 @@ mod tests {
}
#[simd_test(enable = "avx512f")]
- const fn test_mm512_srav_epi32() {
+ fn test_mm512_srav_epi32() {
let a = _mm512_set_epi32(8, -8, 16, -15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1);
let count = _mm512_set_epi32(2, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
let r = _mm512_srav_epi32(a, count);
@@ -54925,7 +54975,7 @@ mod tests {
}
#[simd_test(enable = "avx512f")]
- const fn test_mm512_mask_srav_epi32() {
+ fn test_mm512_mask_srav_epi32() {
let a = _mm512_set_epi32(8, -8, 16, -15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 16);
let count = _mm512_set_epi32(2, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1);
let r = _mm512_mask_srav_epi32(a, 0, a, count);
@@ -54936,7 +54986,7 @@ mod tests {
}
#[simd_test(enable = "avx512f")]
- const fn test_mm512_maskz_srav_epi32() {
+ fn test_mm512_maskz_srav_epi32() {
let a = _mm512_set_epi32(8, -8, 16, -15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -15, -14);
let count = _mm512_set_epi32(2, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2);
let r = _mm512_maskz_srav_epi32(0, a, count);
@@ -54947,7 +54997,7 @@ mod tests {
}
#[simd_test(enable = "avx512f,avx512vl")]
- const fn test_mm256_mask_srav_epi32() {
+ fn test_mm256_mask_srav_epi32() {
let a = _mm256_set_epi32(1 << 5, 0, 0, 0, 0, 0, 0, 0);
let count = _mm256_set1_epi32(1);
let r = _mm256_mask_srav_epi32(a, 0, a, count);
@@ -54958,7 +55008,7 @@ mod tests {
}
#[simd_test(enable = "avx512f,avx512vl")]
- const fn test_mm256_maskz_srav_epi32() {
+ fn test_mm256_maskz_srav_epi32() {
let a = _mm256_set_epi32(1 << 5, 0, 0, 0, 0, 0, 0, 0);
let count = _mm256_set1_epi32(1);
let r = _mm256_maskz_srav_epi32(0, a, count);
@@ -54969,7 +55019,7 @@ mod tests {
}
#[simd_test(enable = "avx512f,avx512vl")]
- const fn test_mm_mask_srav_epi32() {
+ fn test_mm_mask_srav_epi32() {
let a = _mm_set_epi32(1 << 5, 0, 0, 0);
let count = _mm_set1_epi32(1);
let r = _mm_mask_srav_epi32(a, 0, a, count);
@@ -54980,7 +55030,7 @@ mod tests {
}
#[simd_test(enable = "avx512f,avx512vl")]
- const fn test_mm_maskz_srav_epi32() {
+ fn test_mm_maskz_srav_epi32() {
let a = _mm_set_epi32(1 << 5, 0, 0, 0);
let count = _mm_set1_epi32(1);
let r = _mm_maskz_srav_epi32(0, a, count);
diff --git a/library/stdarch/crates/core_arch/src/x86_64/avx512f.rs b/library/stdarch/crates/core_arch/src/x86_64/avx512f.rs
index 28e68d798b1c5..832384b11e68b 100644
--- a/library/stdarch/crates/core_arch/src/x86_64/avx512f.rs
+++ b/library/stdarch/crates/core_arch/src/x86_64/avx512f.rs
@@ -9035,7 +9035,7 @@ mod tests {
}
#[simd_test(enable = "avx512f")]
- const fn test_mm512_sllv_epi64() {
+ fn test_mm512_sllv_epi64() {
#[rustfmt::skip]
let a = _mm512_set_epi64(
1 << 32, 1 << 63, 1 << 32, 1 << 32,
@@ -9052,7 +9052,7 @@ mod tests {
}
#[simd_test(enable = "avx512f")]
- const fn test_mm512_mask_sllv_epi64() {
+ fn test_mm512_mask_sllv_epi64() {
#[rustfmt::skip]
let a = _mm512_set_epi64(
1 << 32, 1 << 32, 1 << 63, 1 << 32,
@@ -9071,7 +9071,7 @@ mod tests {
}
#[simd_test(enable = "avx512f")]
- const fn test_mm512_maskz_sllv_epi64() {
+ fn test_mm512_maskz_sllv_epi64() {
#[rustfmt::skip]
let a = _mm512_set_epi64(
1 << 32, 1 << 32, 1 << 32, 1 << 32,
@@ -9086,7 +9086,7 @@ mod tests {
}
#[simd_test(enable = "avx512f,avx512vl")]
- const fn test_mm256_mask_sllv_epi64() {
+ fn test_mm256_mask_sllv_epi64() {
let a = _mm256_set_epi64x(1 << 32, 1 << 32, 1 << 63, 1 << 32);
let count = _mm256_set_epi64x(0, 1, 2, 3);
let r = _mm256_mask_sllv_epi64(a, 0, a, count);
@@ -9097,7 +9097,7 @@ mod tests {
}
#[simd_test(enable = "avx512f,avx512vl")]
- const fn test_mm256_maskz_sllv_epi64() {
+ fn test_mm256_maskz_sllv_epi64() {
let a = _mm256_set_epi64x(1 << 32, 1 << 32, 1 << 63, 1 << 32);
let count = _mm256_set_epi64x(0, 1, 2, 3);
let r = _mm256_maskz_sllv_epi64(0, a, count);
@@ -9108,7 +9108,7 @@ mod tests {
}
#[simd_test(enable = "avx512f,avx512vl")]
- const fn test_mm_mask_sllv_epi64() {
+ fn test_mm_mask_sllv_epi64() {
let a = _mm_set_epi64x(1 << 63, 1 << 32);
let count = _mm_set_epi64x(2, 3);
let r = _mm_mask_sllv_epi64(a, 0, a, count);
@@ -9119,7 +9119,7 @@ mod tests {
}
#[simd_test(enable = "avx512f,avx512vl")]
- const fn test_mm_maskz_sllv_epi64() {
+ fn test_mm_maskz_sllv_epi64() {
let a = _mm_set_epi64x(1 << 63, 1 << 32);
let count = _mm_set_epi64x(2, 3);
let r = _mm_maskz_sllv_epi64(0, a, count);
@@ -9130,7 +9130,7 @@ mod tests {
}
#[simd_test(enable = "avx512f")]
- const fn test_mm512_srlv_epi64() {
+ fn test_mm512_srlv_epi64() {
#[rustfmt::skip]
let a = _mm512_set_epi64(
1 << 32, 1 << 0, 1 << 32, 1 << 32,
@@ -9147,7 +9147,7 @@ mod tests {
}
#[simd_test(enable = "avx512f")]
- const fn test_mm512_mask_srlv_epi64() {
+ fn test_mm512_mask_srlv_epi64() {
#[rustfmt::skip]
let a = _mm512_set_epi64(
1 << 32, 1 << 0, 1 << 32, 1 << 32,
@@ -9166,7 +9166,7 @@ mod tests {
}
#[simd_test(enable = "avx512f")]
- const fn test_mm512_maskz_srlv_epi64() {
+ fn test_mm512_maskz_srlv_epi64() {
#[rustfmt::skip]
let a = _mm512_set_epi64(
1 << 32, 1 << 32, 1 << 32, 1 << 32,
@@ -9181,7 +9181,7 @@ mod tests {
}
#[simd_test(enable = "avx512f,avx512vl")]
- const fn test_mm256_mask_srlv_epi64() {
+ fn test_mm256_mask_srlv_epi64() {
let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
let count = _mm256_set1_epi64x(1);
let r = _mm256_mask_srlv_epi64(a, 0, a, count);
@@ -9192,7 +9192,7 @@ mod tests {
}
#[simd_test(enable = "avx512f,avx512vl")]
- const fn test_mm256_maskz_srlv_epi64() {
+ fn test_mm256_maskz_srlv_epi64() {
let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
let count = _mm256_set1_epi64x(1);
let r = _mm256_maskz_srlv_epi64(0, a, count);
@@ -9203,7 +9203,7 @@ mod tests {
}
#[simd_test(enable = "avx512f,avx512vl")]
- const fn test_mm_mask_srlv_epi64() {
+ fn test_mm_mask_srlv_epi64() {
let a = _mm_set_epi64x(1 << 5, 0);
let count = _mm_set1_epi64x(1);
let r = _mm_mask_srlv_epi64(a, 0, a, count);
@@ -9214,7 +9214,7 @@ mod tests {
}
#[simd_test(enable = "avx512f,avx512vl")]
- const fn test_mm_maskz_srlv_epi64() {
+ fn test_mm_maskz_srlv_epi64() {
let a = _mm_set_epi64x(1 << 5, 0);
let count = _mm_set1_epi64x(1);
let r = _mm_maskz_srlv_epi64(0, a, count);
@@ -9511,7 +9511,7 @@ mod tests {
}
#[simd_test(enable = "avx512f")]
- const fn test_mm512_srav_epi64() {
+ fn test_mm512_srav_epi64() {
let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
let count = _mm512_set_epi64(2, 2, 0, 0, 0, 0, 2, 1);
let r = _mm512_srav_epi64(a, count);
@@ -9520,7 +9520,7 @@ mod tests {
}
#[simd_test(enable = "avx512f")]
- const fn test_mm512_mask_srav_epi64() {
+ fn test_mm512_mask_srav_epi64() {
let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
let count = _mm512_set_epi64(2, 2, 0, 0, 0, 0, 2, 1);
let r = _mm512_mask_srav_epi64(a, 0, a, count);
@@ -9531,7 +9531,7 @@ mod tests {
}
#[simd_test(enable = "avx512f")]
- const fn test_mm512_maskz_srav_epi64() {
+ fn test_mm512_maskz_srav_epi64() {
let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
let count = _mm512_set_epi64(2, 2, 0, 0, 0, 0, 2, 1);
let r = _mm512_maskz_srav_epi64(0, a, count);
@@ -9542,7 +9542,7 @@ mod tests {
}
#[simd_test(enable = "avx512f,avx512vl")]
- const fn test_mm256_srav_epi64() {
+ fn test_mm256_srav_epi64() {
let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
let count = _mm256_set1_epi64x(1);
let r = _mm256_srav_epi64(a, count);
@@ -9551,7 +9551,7 @@ mod tests {
}
#[simd_test(enable = "avx512f,avx512vl")]
- const fn test_mm256_mask_srav_epi64() {
+ fn test_mm256_mask_srav_epi64() {
let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
let count = _mm256_set1_epi64x(1);
let r = _mm256_mask_srav_epi64(a, 0, a, count);
@@ -9562,7 +9562,7 @@ mod tests {
}
#[simd_test(enable = "avx512f,avx512vl")]
- const fn test_mm256_maskz_srav_epi64() {
+ fn test_mm256_maskz_srav_epi64() {
let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
let count = _mm256_set1_epi64x(1);
let r = _mm256_maskz_srav_epi64(0, a, count);
@@ -9573,16 +9573,24 @@ mod tests {
}
#[simd_test(enable = "avx512f,avx512vl")]
- const fn test_mm_srav_epi64() {
+ fn test_mm_srav_epi64() {
let a = _mm_set_epi64x(1 << 5, 0);
let count = _mm_set1_epi64x(1);
let r = _mm_srav_epi64(a, count);
let e = _mm_set_epi64x(1 << 4, 0);
assert_eq_m128i(r, e);
+
+ let a = _mm_set_epi64x(-1, -2);
+ let b = _mm_set_epi64x(64, 65);
+ let r = _mm_srav_epi64(a, b);
+ let e = _mm_set_epi64x((-1i64).unbounded_shl(64), (-2i64).unbounded_shl(65));
+ assert_eq_m128i(r, e);
+ let e = _mm_set_epi64x(-1, -1);
+ assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
- const fn test_mm_mask_srav_epi64() {
+ fn test_mm_mask_srav_epi64() {
let a = _mm_set_epi64x(1 << 5, 0);
let count = _mm_set1_epi64x(1);
let r = _mm_mask_srav_epi64(a, 0, a, count);
@@ -9593,7 +9601,7 @@ mod tests {
}
#[simd_test(enable = "avx512f,avx512vl")]
- const fn test_mm_maskz_srav_epi64() {
+ fn test_mm_maskz_srav_epi64() {
let a = _mm_set_epi64x(1 << 5, 0);
let count = _mm_set1_epi64x(1);
let r = _mm_maskz_srav_epi64(0, a, count);
diff --git a/library/stdarch/crates/intrinsic-test/Cargo.toml b/library/stdarch/crates/intrinsic-test/Cargo.toml
index e5c9e44e6d32a..2e11591fe7153 100644
--- a/library/stdarch/crates/intrinsic-test/Cargo.toml
+++ b/library/stdarch/crates/intrinsic-test/Cargo.toml
@@ -17,8 +17,6 @@ clap = { version = "4.4", features = ["derive"] }
log = "0.4.11"
pretty_env_logger = "0.5.0"
rayon = "1.5.0"
-diff = "0.1.12"
itertools = "0.15.0"
quick-xml = { version = "0.37.5", features = ["serialize", "overlapped-lists"] }
-serde-xml-rs = "0.8.0"
regex = "1.11.1"
diff --git a/library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index 195243ac65d3a..a4ade26e45c37 100644
--- a/library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -9824,7 +9824,7 @@ intrinsics:
return_type: "{neon_type[1]}"
attr:
- *neon-v7
- - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vorr]]}]]
+ - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vzip]]}]]
- FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [zip1]]}]]
- FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [zip2]]}]]
- *neon-not-arm-stable
diff --git a/library/stdarch/crates/stdarch-gen-hexagon/src/hvx.rs b/library/stdarch/crates/stdarch-gen-hexagon/src/hvx.rs
index e5722a2d9f49f..537c59bbce861 100644
--- a/library/stdarch/crates/stdarch-gen-hexagon/src/hvx.rs
+++ b/library/stdarch/crates/stdarch-gen-hexagon/src/hvx.rs
@@ -213,7 +213,7 @@ fn parse_compound_expr(expr: &str) -> Option {
if let Some(paren_pos) = after_prefix.find(')') {
let builtin_name = &after_prefix[..paren_pos];
let rest = &after_prefix[paren_pos + 1..]; // Skip the closing ) of the WRAP
- // rest should now be "(args)"
+ // rest should now be "(args)"
if rest.starts_with('(') && rest.ends_with(')') {
let args_str = &rest[1..rest.len() - 1];
let args = parse_compound_args(args_str)?;
diff --git a/library/stdarch/crates/stdarch-gen-loongarch/lasx.spec b/library/stdarch/crates/stdarch-gen-loongarch/lasx.spec
index 9eff3d01fa1f3..eb3ff074a3978 100644
--- a/library/stdarch/crates/stdarch-gen-loongarch/lasx.spec
+++ b/library/stdarch/crates/stdarch-gen-loongarch/lasx.spec
@@ -996,81 +996,97 @@ asm-fmts = xd, xj, xk
data-types = UV4DI, UV4DI, UV4DI
/// lasx_xvavg_b
+impl = portable
name = lasx_xvavg_b
asm-fmts = xd, xj, xk
data-types = V32QI, V32QI, V32QI
/// lasx_xvavg_h
+impl = portable
name = lasx_xvavg_h
asm-fmts = xd, xj, xk
data-types = V16HI, V16HI, V16HI
/// lasx_xvavg_w
+impl = portable
name = lasx_xvavg_w
asm-fmts = xd, xj, xk
data-types = V8SI, V8SI, V8SI
/// lasx_xvavg_d
+impl = portable
name = lasx_xvavg_d
asm-fmts = xd, xj, xk
data-types = V4DI, V4DI, V4DI
/// lasx_xvavg_bu
+impl = portable
name = lasx_xvavg_bu
asm-fmts = xd, xj, xk
data-types = UV32QI, UV32QI, UV32QI
/// lasx_xvavg_hu
+impl = portable
name = lasx_xvavg_hu
asm-fmts = xd, xj, xk
data-types = UV16HI, UV16HI, UV16HI
/// lasx_xvavg_wu
+impl = portable
name = lasx_xvavg_wu
asm-fmts = xd, xj, xk
data-types = UV8SI, UV8SI, UV8SI
/// lasx_xvavg_du
+impl = portable
name = lasx_xvavg_du
asm-fmts = xd, xj, xk
data-types = UV4DI, UV4DI, UV4DI
/// lasx_xvavgr_b
+impl = portable
name = lasx_xvavgr_b
asm-fmts = xd, xj, xk
data-types = V32QI, V32QI, V32QI
/// lasx_xvavgr_h
+impl = portable
name = lasx_xvavgr_h
asm-fmts = xd, xj, xk
data-types = V16HI, V16HI, V16HI
/// lasx_xvavgr_w
+impl = portable
name = lasx_xvavgr_w
asm-fmts = xd, xj, xk
data-types = V8SI, V8SI, V8SI
/// lasx_xvavgr_d
+impl = portable
name = lasx_xvavgr_d
asm-fmts = xd, xj, xk
data-types = V4DI, V4DI, V4DI
/// lasx_xvavgr_bu
+impl = portable
name = lasx_xvavgr_bu
asm-fmts = xd, xj, xk
data-types = UV32QI, UV32QI, UV32QI
/// lasx_xvavgr_hu
+impl = portable
name = lasx_xvavgr_hu
asm-fmts = xd, xj, xk
data-types = UV16HI, UV16HI, UV16HI
/// lasx_xvavgr_wu
+impl = portable
name = lasx_xvavgr_wu
asm-fmts = xd, xj, xk
data-types = UV8SI, UV8SI, UV8SI
/// lasx_xvavgr_du
+impl = portable
name = lasx_xvavgr_du
asm-fmts = xd, xj, xk
data-types = UV4DI, UV4DI, UV4DI
diff --git a/library/stdarch/crates/stdarch-gen-loongarch/lsx.spec b/library/stdarch/crates/stdarch-gen-loongarch/lsx.spec
index ba2554b0cf9ff..89970c3657048 100644
--- a/library/stdarch/crates/stdarch-gen-loongarch/lsx.spec
+++ b/library/stdarch/crates/stdarch-gen-loongarch/lsx.spec
@@ -996,81 +996,97 @@ asm-fmts = vd, vj, vk
data-types = UV2DI, UV2DI, UV2DI
/// lsx_vavg_b
+impl = portable
name = lsx_vavg_b
asm-fmts = vd, vj, vk
data-types = V16QI, V16QI, V16QI
/// lsx_vavg_h
+impl = portable
name = lsx_vavg_h
asm-fmts = vd, vj, vk
data-types = V8HI, V8HI, V8HI
/// lsx_vavg_w
+impl = portable
name = lsx_vavg_w
asm-fmts = vd, vj, vk
data-types = V4SI, V4SI, V4SI
/// lsx_vavg_d
+impl = portable
name = lsx_vavg_d
asm-fmts = vd, vj, vk
data-types = V2DI, V2DI, V2DI
/// lsx_vavg_bu
+impl = portable
name = lsx_vavg_bu
asm-fmts = vd, vj, vk
data-types = UV16QI, UV16QI, UV16QI
/// lsx_vavg_hu
+impl = portable
name = lsx_vavg_hu
asm-fmts = vd, vj, vk
data-types = UV8HI, UV8HI, UV8HI
/// lsx_vavg_wu
+impl = portable
name = lsx_vavg_wu
asm-fmts = vd, vj, vk
data-types = UV4SI, UV4SI, UV4SI
/// lsx_vavg_du
+impl = portable
name = lsx_vavg_du
asm-fmts = vd, vj, vk
data-types = UV2DI, UV2DI, UV2DI
/// lsx_vavgr_b
+impl = portable
name = lsx_vavgr_b
asm-fmts = vd, vj, vk
data-types = V16QI, V16QI, V16QI
/// lsx_vavgr_h
+impl = portable
name = lsx_vavgr_h
asm-fmts = vd, vj, vk
data-types = V8HI, V8HI, V8HI
/// lsx_vavgr_w
+impl = portable
name = lsx_vavgr_w
asm-fmts = vd, vj, vk
data-types = V4SI, V4SI, V4SI
/// lsx_vavgr_d
+impl = portable
name = lsx_vavgr_d
asm-fmts = vd, vj, vk
data-types = V2DI, V2DI, V2DI
/// lsx_vavgr_bu
+impl = portable
name = lsx_vavgr_bu
asm-fmts = vd, vj, vk
data-types = UV16QI, UV16QI, UV16QI
/// lsx_vavgr_hu
+impl = portable
name = lsx_vavgr_hu
asm-fmts = vd, vj, vk
data-types = UV8HI, UV8HI, UV8HI
/// lsx_vavgr_wu
+impl = portable
name = lsx_vavgr_wu
asm-fmts = vd, vj, vk
data-types = UV4SI, UV4SI, UV4SI
/// lsx_vavgr_du
+impl = portable
name = lsx_vavgr_du
asm-fmts = vd, vj, vk
data-types = UV2DI, UV2DI, UV2DI
diff --git a/library/stdarch/crates/stdarch-gen-loongarch/src/portable-intrinsics.txt b/library/stdarch/crates/stdarch-gen-loongarch/src/portable-intrinsics.txt
index 8b8c82b3bb247..f47c17b23adea 100644
--- a/library/stdarch/crates/stdarch-gen-loongarch/src/portable-intrinsics.txt
+++ b/library/stdarch/crates/stdarch-gen-loongarch/src/portable-intrinsics.txt
@@ -219,6 +219,22 @@ lsx_vssub_bu
lsx_vssub_hu
lsx_vssub_wu
lsx_vssub_du
+lsx_vavg_b
+lsx_vavg_h
+lsx_vavg_w
+lsx_vavg_d
+lsx_vavg_bu
+lsx_vavg_hu
+lsx_vavg_wu
+lsx_vavg_du
+lsx_vavgr_b
+lsx_vavgr_h
+lsx_vavgr_w
+lsx_vavgr_d
+lsx_vavgr_bu
+lsx_vavgr_hu
+lsx_vavgr_wu
+lsx_vavgr_du
lsx_vadda_b
lsx_vadda_h
lsx_vadda_w
@@ -512,6 +528,22 @@ lasx_xvssub_bu
lasx_xvssub_hu
lasx_xvssub_wu
lasx_xvssub_du
+lasx_xvavg_b
+lasx_xvavg_h
+lasx_xvavg_w
+lasx_xvavg_d
+lasx_xvavg_bu
+lasx_xvavg_hu
+lasx_xvavg_wu
+lasx_xvavg_du
+lasx_xvavgr_b
+lasx_xvavgr_h
+lasx_xvavgr_w
+lasx_xvavgr_d
+lasx_xvavgr_bu
+lasx_xvavgr_hu
+lasx_xvavgr_wu
+lasx_xvavgr_du
lasx_xvadda_b
lasx_xvadda_h
lasx_xvadda_w
diff --git a/library/stdarch/crates/stdarch-verify/tests/x86-intel.rs b/library/stdarch/crates/stdarch-verify/tests/x86-intel.rs
index be948df541b79..d2839bb300c2d 100644
--- a/library/stdarch/crates/stdarch-verify/tests/x86-intel.rs
+++ b/library/stdarch/crates/stdarch-verify/tests/x86-intel.rs
@@ -293,7 +293,16 @@ fn verify_all_signatures() {
"_MM_SHUFFLE" |
"_xabort_code" |
// Not listed with intel, but manually verified
- "cmpxchg16b"
+ "cmpxchg16b" |
+ // Apparently forgotten in the Intel Intrinsics Guide
+ // but present in other Intel documentation and clang,
+ // see https://github.com/rust-lang/rust/issues/158196
+ "_mm_cvtepu32_ps" |
+ "_mm_mask_cvtepu32_ps" |
+ "_mm_maskz_cvtepu32_ps" |
+ "_mm256_cvtepu32_ps" |
+ "_mm256_mask_cvtepu32_ps" |
+ "_mm256_maskz_cvtepu32_ps"
=> continue,
_ => {}
}
diff --git a/library/stdarch/examples/Cargo.toml b/library/stdarch/examples/Cargo.toml
index 8752f206526c7..677407cf25206 100644
--- a/library/stdarch/examples/Cargo.toml
+++ b/library/stdarch/examples/Cargo.toml
@@ -12,9 +12,11 @@ default-run = "hex"
[dependencies]
core_arch = { path = "../crates/core_arch" }
-quickcheck = "1.0"
rand = "0.9.3"
+[dev-dependencies]
+quickcheck = "1.0"
+
[[bin]]
name = "hex"
path = "hex.rs"
diff --git a/library/stdarch/josh-sync.toml b/library/stdarch/josh-sync.toml
index ebdb4576287c8..eeeb82659a0a6 100644
--- a/library/stdarch/josh-sync.toml
+++ b/library/stdarch/josh-sync.toml
@@ -1,3 +1,7 @@
org = "rust-lang"
repo = "stdarch"
path = "library/stdarch"
+
+[[post-pull]]
+cmd = ["cargo", "fmt"]
+commit-message = "Run `cargo fmt`"
diff --git a/library/stdarch/rust-version b/library/stdarch/rust-version
index 61a4b2d8c095f..18fea436747c7 100644
--- a/library/stdarch/rust-version
+++ b/library/stdarch/rust-version
@@ -1 +1 @@
-1e5ee356374211706221b71b6106d297a646ee57
+32d94cc9be3f6e6c3fa1deaea9e0ab93c4980dba
diff --git a/src/bootstrap/src/core/build_steps/install.rs b/src/bootstrap/src/core/build_steps/install.rs
index db0d18e8368e2..cad6117e686da 100644
--- a/src/bootstrap/src/core/build_steps/install.rs
+++ b/src/bootstrap/src/core/build_steps/install.rs
@@ -324,12 +324,12 @@ impl CommandLineStep for Src {
const IS_HOST: bool = true;
fn should_run(run: ShouldRun<'_>) -> ShouldRun<'_> {
- run.path("src")
+ run.alias("rust-src")
}
fn is_default_step(builder: &Builder<'_>) -> bool {
let config = &builder.config;
- config.extended && config.tools.as_ref().is_none_or(|t| t.contains("src"))
+ config.extended && config.tools.as_ref().is_none_or(|t| t.contains("rust-src"))
}
fn make_run(run: RunConfig<'_>) {
diff --git a/src/bootstrap/src/core/build_steps/llvm.rs b/src/bootstrap/src/core/build_steps/llvm.rs
index 096184ee9e5b4..649f638996866 100644
--- a/src/bootstrap/src/core/build_steps/llvm.rs
+++ b/src/bootstrap/src/core/build_steps/llvm.rs
@@ -832,6 +832,40 @@ fn debuginfo_map_cflags(builder: &Builder<'_>, target: TargetSelection) -> Vec,
+ target: TargetSelection,
+ llvm_output: &LlvmOutput,
+ cfg: &mut cmake::Config,
+ ldflags: &mut LdFlags,
+) {
+ // Apple has it's own ld64 linker, so don't use LLD on Darwin.
+ if target.contains("apple") {
+ return;
+ }
+
+ if builder.config.llvm_use_linker.is_some() || !builder.config.lld_enabled || target.is_msvc() {
+ // Logic derived from `configure_llvm`
+ // ThinLTO is only available when building with LLVM, enabling LLD is required.
+ if builder.config.llvm_thin_lto {
+ ldflags.push_all("-fuse-ld=lld");
+ }
+ return;
+ }
+
+ let lld_bin = builder.ensure(Lld { target }).join("bin");
+ ldflags.push_all(format!("-B{} -fuse-ld=lld", lld_bin.display()));
+
+ if llvm_output.link_shared() {
+ // LLD in this case needs the LLVM lib, so tell where to look for it.
+ let mut dylib_path = helpers::dylib_path();
+ dylib_path.insert(0, llvm_output.root_dir().join("lib"));
+ cfg.env(helpers::dylib_path_var(), t!(env::join_paths(&dylib_path)));
+ }
+}
+
fn configure_cmake(
builder: &Builder<'_>,
target: TargetSelection,
@@ -1180,13 +1214,8 @@ impl CommandLineStep for RustOffload {
let mut cfg =
cmake::Config::new(builder.src.join("compiler/rustc_llvm/llvm-wrapper/offload/"));
- // Logic copied from `configure_llvm`
- // ThinLTO is only available when building with LLVM, enabling LLD is required.
- // Apple's linker ld64 supports ThinLTO out of the box though, so don't use LLD on Darwin.
let mut ldflags = LdFlags::default();
- if builder.config.llvm_thin_lto && !target.contains("apple") {
- ldflags.push_all("-fuse-ld=lld");
- }
+ try_link_with_in_tree_lld(builder, target, &llvm_output, &mut cfg, &mut ldflags);
configure_cmake(builder, target, &mut cfg, true, ldflags, CcFlags::default(), &[]);
@@ -1397,13 +1426,8 @@ impl CommandLineStep for OmpOffload {
cflags.push_all(format!(" -I {inc_dir}"));
}
- // Logic copied from `configure_llvm`
- // ThinLTO is only available when building with LLVM, enabling LLD is required.
- // Apple's linker ld64 supports ThinLTO out of the box though, so don't use LLD on Darwin.
let mut ldflags = LdFlags::default();
- if builder.config.llvm_thin_lto && !target.contains("apple") {
- ldflags.push_all("-fuse-ld=lld");
- }
+ try_link_with_in_tree_lld(builder, target, &llvm_output, &mut cfg, &mut ldflags);
if let Some(dir) = &cxx_lib_dir {
ldflags.push_all(format!("-L{}", dir.display()));
@@ -1578,13 +1602,8 @@ impl CommandLineStep for Enzyme {
let mut cflags = CcFlags::default();
cflags.push_all("-Wno-deprecated");
- // Logic copied from `configure_llvm`
- // ThinLTO is only available when building with LLVM, enabling LLD is required.
- // Apple's linker ld64 supports ThinLTO out of the box though, so don't use LLD on Darwin.
let mut ldflags = LdFlags::default();
- if builder.config.llvm_thin_lto && !target.contains("apple") {
- ldflags.push_all("-fuse-ld=lld");
- }
+ try_link_with_in_tree_lld(builder, target, &llvm_output, &mut cfg, &mut ldflags);
configure_cmake(builder, target, &mut cfg, true, ldflags, cflags, &[]);
diff --git a/src/bootstrap/src/core/builder/tests.rs b/src/bootstrap/src/core/builder/tests.rs
index 9c613811c8ccc..cc6ac39672950 100644
--- a/src/bootstrap/src/core/builder/tests.rs
+++ b/src/bootstrap/src/core/builder/tests.rs
@@ -2798,7 +2798,7 @@ mod snapshot {
let ctx = TestCtx::new();
insta::assert_snapshot!(
ctx.config("install")
- .path("src")
+ .path("rust-src")
.args(&[
// Using backslashes fails with `--set`
"--set", &format!("install.prefix={}", ctx.normalized_dir()),
@@ -2815,36 +2815,7 @@ mod snapshot {
.render_with(RenderConfig {
normalize_host: false
}), @r"
- [build] llvm
- [build] rustc 0 -> rustc 1
- [build] rustc 1 -> std 1
- [build] rustc 0 -> UnstableBookGen 1
- [build] rustc 0 -> Rustbook 1
- [doc] unstable-book (book)
- [doc] book (book)
- [doc] book/first-edition (book)
- [doc] book/second-edition (book)
- [doc] book/2018-edition (book)
- [build] rustdoc 1
- [doc] rustc 1 -> standalone 2
- [doc] rustc 1 -> std 1 crates=[alloc,compiler_builtins,core,panic_abort,panic_unwind,proc_macro,rustc-std-workspace-core,std,std_detect,sysroot,test,unwind]
- [build] rustc 1 -> rustc 2
- [build] rustc 1 -> error-index 2
- [doc] rustc 1 -> error-index 2
- [doc] nomicon (book)
- [doc] rustc 1 -> reference (book) 2
- [doc] rustdoc (book)
- [doc] rust-by-example (book)
- [build] rustc 0 -> LintDocs 1
- [doc] rustc (book)
- [doc] cargo (book)
- [doc] clippy (book)
- [doc] embedded-book (book)
- [doc] edition-guide (book)
- [doc] style-guide (book)
- [doc] rustc 1 -> releases 2
[build] rustc 0 -> RustInstaller 1
- [dist] docs
[dist] src <>
");
}
@@ -2854,7 +2825,7 @@ mod snapshot {
let ctx = TestCtx::new();
insta::assert_snapshot!(
ctx.config("install")
- .path("src")
+ .path("rust-src")
.args(&[
// Using backslashes fails with `--set`
"--set", &format!("install.prefix={}", ctx.normalized_dir()),
@@ -2872,10 +2843,7 @@ mod snapshot {
.render_with(RenderConfig {
normalize_host: false
}), @r"
- [build] llvm
- [build] rustc 0 -> rustc 1
[build] rustc 0 -> RustInstaller 1
- [dist] docs
[dist] src <>
");
}
diff --git a/src/bootstrap/src/utils/change_tracker.rs b/src/bootstrap/src/utils/change_tracker.rs
index 25c0963aa4191..922d969ec1f35 100644
--- a/src/bootstrap/src/utils/change_tracker.rs
+++ b/src/bootstrap/src/utils/change_tracker.rs
@@ -671,4 +671,9 @@ pub const CONFIG_CHANGE_HISTORY: &[ChangeInfo] = &[
severity: ChangeSeverity::Warning,
summary: "The `override-allocator` option has been renamed: The global setting is now `build.allocator` and the per-target setting is `target..allocator`. It can now be set to 'system' to explicitly request the system allocator.",
},
+ ChangeInfo {
+ change_id: 162423,
+ severity: ChangeSeverity::Warning,
+ summary: "You should now use `x install rust-src` instead of `x install src` to install the standard library source component. If you want to install it as part of a custom `build.tools` set, include `rust-src` in `build.tools.",
+ },
];
diff --git a/src/doc/rustc/src/platform-support.md b/src/doc/rustc/src/platform-support.md
index 578651820b4dc..c2a86d85dfcde 100644
--- a/src/doc/rustc/src/platform-support.md
+++ b/src/doc/rustc/src/platform-support.md
@@ -47,11 +47,9 @@ target | notes
[`x86_64-pc-windows-gnu`](platform-support/windows-gnu.md) | 64-bit MinGW (Windows 10+, Windows Server 2016+)
[`x86_64-pc-windows-msvc`](platform-support/windows-msvc.md) | 64-bit MSVC (Windows 10+, Windows Server 2016+)
`x86_64-unknown-linux-gnu` | 64-bit Linux (kernel 3.2+, glibc 2.17+)
-[^x86_32-floats-return-ABI]: Due to limitations of the C ABI, floating-point support on `i686` targets is non-compliant: floating-point return values are passed via an x87 register, so NaN payload bits can be lost. Functions with the default Rust ABI are not affected. See [issue #115567][x86-32-float-return-issue].
-[^win32-msvc-alignment]: Due to non-standard behavior of MSVC, native C code on this target can cause types with an alignment of more than 4 bytes to be incorrectly aligned to only 4 bytes (this affects, e.g., `u64` and `i64`). Rust applies some mitigations to reduce the impact of this issue, but this can still cause unsoundness due to unsafe code that (correctly) assumes that references are always properly aligned. See [issue #112480](https://github.com/rust-lang/rust/issues/112480).
+[^x86_32-floats-return-ABI]: Due to limitations of the C ABI, floating-point support on `i686` targets is non-compliant: floating-point return values are passed via an x87 register, so NaN payload bits can be lost. Functions with the default Rust ABI are not affected. See [issue #115567][x86-32-float-return-issue].
-[77071]: https://github.com/rust-lang/rust/issues/77071
[x86-32-float-return-issue]: https://github.com/rust-lang/rust/issues/115567
## Tier 1 without Host Tools
@@ -60,6 +58,8 @@ target | notes
-------|-------
[`i686-pc-windows-msvc`](platform-support/windows-msvc.md) | 32-bit MSVC (Windows 10+, Windows Server 2016+, Pentium 4) [^x86_32-floats-return-ABI] [^win32-msvc-alignment]
+[^win32-msvc-alignment]: Due to non-standard behavior of MSVC, native C code on this target can cause types with an alignment of more than 4 bytes to be incorrectly aligned to only 4 bytes (this affects, e.g., `u64` and `i64`). Rust applies some mitigations to reduce the impact of this issue, but this can still cause unsoundness due to unsafe code that (correctly) assumes that references are always properly aligned. See [issue #112480](https://github.com/rust-lang/rust/issues/112480).
+
All tier 1 (without host tools) targets support the full standard library.
## Tier 2 with Host Tools
@@ -239,8 +239,6 @@ target | std | notes
[x86-32-float-issue]: https://github.com/rust-lang/rust/issues/114479
-[wasi-rename]: https://github.com/rust-lang/compiler-team/issues/607
-
[Fortanix ABI]: https://edp.fortanix.com/
## Tier 3
diff --git a/src/etc/lldb_lookup.py b/src/etc/lldb_lookup.py
index 365816dc8489a..94ed47af1891f 100644
--- a/src/etc/lldb_lookup.py
+++ b/src/etc/lldb_lookup.py
@@ -40,6 +40,7 @@
ClangEncodedEnumSummaryProvider,
StructSummaryProvider,
f16SummaryProvider,
+ f128SummaryProvider,
# re-exports
get_template_args as get_template_args,
resolve_msvc_template_arg as resolve_msvc_template_arg,
@@ -181,6 +182,17 @@ def register_providers_compatibility():
DEFAULT_TYPE_OPTIONS | lldb.eTypeOptionHideChildren,
)
+ if LLDBFeature.Float128 in FEATURE_FLAGS:
+ # Force f128 summary on windows-msvc since most Windows debuggers don't support PDB f128
+ register_summary(
+ f128SummaryProvider,
+ lldb.SBTypeNameSpecifier(
+ MOD_PREFIX + is_msvc_f128.__name__,
+ lldb.eFormatterMatchCallback,
+ ),
+ DEFAULT_TYPE_OPTIONS | lldb.eTypeOptionHideChildren,
+ )
+
# Tuple-structs
register_synth(
TupleSyntheticProvider,
@@ -501,6 +513,11 @@ def is_msvc_f16(type: lldb.SBType, _dict: LLDBOpaque) -> bool:
return type.GetName() == "f16" and type.IsAggregateType()
+def is_msvc_f128(type: lldb.SBType, _dict: LLDBOpaque) -> bool:
+ # Most Windows debuggers don't support PDB f128.
+ return type.GetName() == "f128" and type.IsAggregateType()
+
+
def classify_rust_type(type: lldb.SBType, is_msvc: bool) -> RustType:
if type.IsPointerType():
return RustType.Indirection
diff --git a/src/etc/lldb_providers.py b/src/etc/lldb_providers.py
index 2791dae3600b0..a3a424ac1abce 100644
--- a/src/etc/lldb_providers.py
+++ b/src/etc/lldb_providers.py
@@ -542,6 +542,12 @@ def f16SummaryProvider(valobj: SBValue, _dict: LLDBOpaque) -> str:
)
+def f128SummaryProvider(valobj: SBValue, _dict: LLDBOpaque) -> str:
+ from lldb import eBasicTypeFloat128
+
+ return valobj.Cast(valobj.GetTarget().GetBasicType(eBasicTypeFloat128)).GetValue()
+
+
def sequence_formatter(output: str, valobj: SBValue, _dict: LLDBOpaque):
length: int = valobj.GetNumChildren()
diff --git a/src/etc/natvis/intrinsic.natvis b/src/etc/natvis/intrinsic.natvis
index 49e0ce319efac..ac9bf1c427957 100644
--- a/src/etc/natvis/intrinsic.natvis
+++ b/src/etc/natvis/intrinsic.natvis
@@ -59,6 +59,118 @@
{(float) (sign() * (raw_significand() + 1.0) * two_pow_exponent())}
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ {sign()}inf
+ NaN
+
+ {sign()}0x0p+0
+
+ {sign()}0x1{subnormal_hex()}p{-16382 - subnormal_shift(),d}
+ {sign()}0x1{normal_hex()}p{normal_exponent_sign()}{normal_exponent(),d}
+
+
+ - "0x" + hex128(high_bits, low_bits, 128)
+
+
()
diff --git a/src/tools/miri/src/intrinsics/x86/avx2.rs b/src/tools/miri/src/intrinsics/x86/avx2.rs
index 57ea31d2c58a3..6169a1f785833 100644
--- a/src/tools/miri/src/intrinsics/x86/avx2.rs
+++ b/src/tools/miri/src/intrinsics/x86/avx2.rs
@@ -2,7 +2,7 @@ use rustc_span::Symbol;
use super::{
ShiftOp, mpsadbw, packssdw, packsswb, packusdw, packuswb, permute, pmaddbw, pmaddwd, pmulhrsw,
- psadbw, pshufb, psign, shift_simd_by_scalar,
+ psadbw, pshufb, psign, shift_simd_by_scalar, shift_simd_by_simd,
};
use crate::*;
@@ -201,6 +201,22 @@ pub(super) trait EvalContextExt<'tcx>: crate::MiriInterpCxExt<'tcx> {
pmaddwd(this, left, right, dest)?;
}
+ // Used to implement the _mm{,256}_{sllv,srlv,srav}_epi{32,64} functions
+ // (except _mm{,256}_srav_epi64, which are not available in AVX2).
+ "psllv.d" | "psllv.d.256" | "psllv.q" | "psllv.q.256" | "psrlv.d" | "psrlv.d.256"
+ | "psrlv.q" | "psrlv.q.256" | "psrav.d" | "psrav.d.256" => {
+ let [left, right] = this.check_shim_sig_llvm_intrinsic(link_name, args)?;
+
+ let which = match unprefixed_name {
+ "psllv.d" | "psllv.d.256" | "psllv.q" | "psllv.q.256" => ShiftOp::Left,
+ "psrlv.d" | "psrlv.d.256" | "psrlv.q" | "psrlv.q.256" => ShiftOp::RightLogic,
+ "psrav.d" | "psrav.d.256" => ShiftOp::RightArith,
+ _ => unreachable!(),
+ };
+
+ shift_simd_by_simd(this, left, right, which, dest)?;
+ }
+
_ => return interp_ok(EmulateItemResult::NotSupported),
}
interp_ok(EmulateItemResult::NeedsReturn)
diff --git a/src/tools/miri/src/intrinsics/x86/mod.rs b/src/tools/miri/src/intrinsics/x86/mod.rs
index 1f7cda56ef862..3bd84fecd1079 100644
--- a/src/tools/miri/src/intrinsics/x86/mod.rs
+++ b/src/tools/miri/src/intrinsics/x86/mod.rs
@@ -506,6 +506,56 @@ fn shift_simd_by_scalar<'tcx>(
interp_ok(())
}
+fn shift_simd_by_simd<'tcx>(
+ ecx: &mut crate::MiriInterpCx<'tcx>,
+ left: &OpTy<'tcx>,
+ right: &OpTy<'tcx>,
+ which: ShiftOp,
+ dest: &MPlaceTy<'tcx>,
+) -> InterpResult<'tcx, ()> {
+ let (left, left_len) = ecx.project_to_simd(left)?;
+ let (right, right_len) = ecx.project_to_simd(right)?;
+ let (dest, dest_len) = ecx.project_to_simd(dest)?;
+
+ assert_eq!(dest_len, left_len);
+ assert_eq!(dest_len, right_len);
+
+ for i in 0..dest_len {
+ let left = ecx.read_scalar(&ecx.project_index(&left, i)?)?;
+ let right = ecx.read_scalar(&ecx.project_index(&right, i)?)?;
+ let dest = ecx.project_index(&dest, i)?;
+
+ // It is ok to saturate the value to u32::MAX because any value
+ // above BITS - 1 will produce the same result.
+ let shift = u32::try_from(right.to_uint(dest.layout.size)?).unwrap_or(u32::MAX);
+
+ let res = match which {
+ ShiftOp::Left => {
+ let left = left.to_uint(dest.layout.size)?;
+ let res = left.checked_shl(shift).unwrap_or(0);
+ // `truncate` is needed as left-shift can make the absolute value larger.
+ Scalar::from_uint(dest.layout.size.truncate(res), dest.layout.size)
+ }
+ ShiftOp::RightLogic => {
+ let left = left.to_uint(dest.layout.size)?;
+ let res = left.checked_shr(shift).unwrap_or(0);
+ // No `truncate` needed as right-shift can only make the absolute value smaller.
+ Scalar::from_uint(res, dest.layout.size)
+ }
+ ShiftOp::RightArith => {
+ let left = left.to_int(dest.layout.size)?;
+ // On overflow, copy the sign bit to the remaining bits
+ let res = left.checked_shr(shift).unwrap_or(left >> 127);
+ // No `truncate` needed as right-shift can only make the absolute value smaller.
+ Scalar::from_int(res, dest.layout.size)
+ }
+ };
+ ecx.write_scalar(res, &dest)?;
+ }
+
+ interp_ok(())
+}
+
/// Takes a 128-bit vector, transmutes it to `[u64; 2]` and extracts
/// the first value.
fn extract_first_u64<'tcx>(
diff --git a/src/tools/miri/tests/pass/shims/x86/intrinsics-x86-avx2.rs b/src/tools/miri/tests/pass/shims/x86/intrinsics-x86-avx2.rs
index 7fe75254c2dd8..e98647f6f99ed 100644
--- a/src/tools/miri/tests/pass/shims/x86/intrinsics-x86-avx2.rs
+++ b/src/tools/miri/tests/pass/shims/x86/intrinsics-x86-avx2.rs
@@ -1452,8 +1452,22 @@ unsafe fn test_avx2() {
let a = _mm_set_epi64x(2, 3);
let b = _mm_set_epi64x(1, 2);
let r = _mm_sllv_epi64(a, b);
+ // Compare with the scalar version of the same computation.
+ let e = _mm_set_epi64x(2i64.unbounded_shl(1), 3i64.unbounded_shl(2));
+ assert_eq_m128i(r, e);
+ // Compare with hardcoded output.
let e = _mm_set_epi64x(4, 12);
assert_eq_m128i(r, e);
+
+ // The shift has unbounded semantics: if the shift amount
+ // is >= the number of bits the result is 0.
+ let a = _mm_set_epi64x(1, 2);
+ let b = _mm_set_epi64x(64, 65);
+ let r = _mm_sllv_epi64(a, b);
+ let e = _mm_set_epi64x(1i64.unbounded_shl(64), 2i64.unbounded_shl(65));
+ assert_eq_m128i(r, e);
+ let e = _mm_set_epi64x(0, 0);
+ assert_eq_m128i(r, e);
}
test_mm_sllv_epi64();
@@ -1474,6 +1488,23 @@ unsafe fn test_avx2() {
let r = _mm_srav_epi32(a, b);
let e = _mm_set_epi32(1, -4, 16, -64);
assert_eq_m128i(r, e);
+
+ // The shift has unbounded semantics: if the shift amount
+ // is >= the number of bits the result is -1.
+ let a = _mm_set_epi32(-16, -32, -64, -128);
+ let b = _mm_set_epi32(31, 32, 33, 0);
+ let r = _mm_srav_epi32(a, b);
+ // Compare with the scalar version of the same computation.
+ let e = _mm_set_epi32(
+ (-16i32).unbounded_shr(31),
+ (-32i32).unbounded_shr(32),
+ (-64i32).unbounded_shr(33),
+ (-128i32).unbounded_shr(0),
+ );
+ assert_eq_m128i(r, e);
+ // Compare with hardcoded output.
+ let e = _mm_set_epi32(-1, -1, -1, -128);
+ assert_eq_m128i(r, e);
}
test_mm_srav_epi32();
@@ -1512,8 +1543,22 @@ unsafe fn test_avx2() {
let a = _mm_set_epi64x(4, 8);
let b = _mm_set_epi64x(2, 1);
let r = _mm_srlv_epi64(a, b);
+ // Compare with the scalar version of the same computation.
+ let e = _mm_set_epi64x(4i64.unbounded_shr(2), 8i64.unbounded_shr(1));
+ assert_eq_m128i(r, e);
+ // Compare with hardcoded output.
let e = _mm_set_epi64x(1, 4);
assert_eq_m128i(r, e);
+
+ // The shift has unbounded semantics: if the shift amount
+ // is >= the number of bits the result is 0.
+ let a = _mm_set_epi64x(i64::MAX, i64::MAX);
+ let b = _mm_set_epi64x(64, 65);
+ let r = _mm_sllv_epi64(a, b);
+ let e = _mm_set_epi64x(i64::MAX.unbounded_shr(64), i64::MAX.unbounded_shr(65));
+ assert_eq_m128i(r, e);
+ let e = _mm_set_epi64x(0, 0);
+ assert_eq_m128i(r, e);
}
test_mm_srlv_epi64();
diff --git a/tests/codegen-llvm/cstr-len-plus-one.rs b/tests/codegen-llvm/cstr-len-plus-one.rs
new file mode 100644
index 0000000000000..056f59070df09
--- /dev/null
+++ b/tests/codegen-llvm/cstr-len-plus-one.rs
@@ -0,0 +1,15 @@
+//@ compile-flags: -Copt-level=3 -Cpanic=abort
+
+#![crate_type = "lib"]
+#![feature(cstr_bytes)]
+
+use std::ffi::CStr;
+
+// A `CStr`'s length always fits in an isize after the NUL bit is accounted for
+
+// CHECK-LABEL: @cstr_len_plus_one
+#[no_mangle]
+pub fn cstr_len_plus_one(s: &CStr) -> bool {
+ // CHECK: ret i1 true
+ s.bytes().count() + 1 <= isize::MAX as usize
+}
diff --git a/tests/codegen-llvm/f128-sparc-callconv.rs b/tests/codegen-llvm/f128-sparc-callconv.rs
new file mode 100644
index 0000000000000..b71c6b78a1539
--- /dev/null
+++ b/tests/codegen-llvm/f128-sparc-callconv.rs
@@ -0,0 +1,53 @@
+//! Verify that Rust implements the expected calling convention for `f128`
+
+//@ add-minicore
+//@ revisions: sparc-none sparc-linux
+//@ [sparc-none] compile-flags: --target sparc-unknown-none-elf
+//@ [sparc-linux] compile-flags: --target sparc-unknown-linux-gnu
+//@ compile-flags: -Copt-level=3
+//@ needs-llvm-components: sparc
+
+#![crate_type = "lib"]
+#![no_std]
+#![no_core]
+#![feature(no_core, lang_items, f128)]
+
+extern crate minicore;
+
+unsafe extern "C" {
+ safe fn extern_call(arg0: f128);
+ safe fn extern_ret() -> f128;
+}
+
+#[no_mangle]
+pub extern "C" fn pass(_arg0: u32, arg1: f128) {
+ // CHECK-LABEL: @pass(
+ // an f128 is passed via the stack
+ // CHECK-SAME: ptr {{.*}}
+ // CHECK: call void @extern_call
+ extern_call(arg1);
+}
+
+// Check that we produce the correct return ABI
+#[no_mangle]
+pub extern "C" fn ret(_arg0: u32, arg1: f128) -> f128 {
+ // CHECK-LABEL: @ret(
+ // and an f128 is returned via the stack
+ // CHECK-SAME: sret([16 x i8])
+ // CHECK: %0 = load fp128, ptr %arg1
+ // CHECK-NEXT: store fp128 %0, ptr %_0
+ // CHECK-NEXT: ret void
+ arg1
+}
+
+// Check that we consume the correct return ABI
+#[no_mangle]
+pub extern "C" fn forward(dst: &mut f128) {
+ // CHECK-LABEL: @forward
+ // CHECK-SAME: ptr{{.*}} %dst)
+ // without optimizatons, an intermediate alloca is used
+ // CHECK: call void @extern_ret
+ // CHECK: store fp128
+ // CHECK: ret void
+ *dst = extern_ret();
+}
diff --git a/tests/codegen-llvm/repr/transparent-imm-array.rs b/tests/codegen-llvm/repr/transparent-imm-array.rs
index c72151741400a..04c9727b815d4 100644
--- a/tests/codegen-llvm/repr/transparent-imm-array.rs
+++ b/tests/codegen-llvm/repr/transparent-imm-array.rs
@@ -1,5 +1,5 @@
//@ add-minicore
-//@ revisions: arm-linux arm-android armv7-linux armv7-android mips thumb sparc
+//@ revisions: arm-linux arm-android armv7-linux armv7-android mips thumb
//@ compile-flags: -Copt-level=3 -C no-prepopulate-passes
//@[arm-linux] compile-flags: --target arm-unknown-linux-gnueabi
@@ -14,8 +14,6 @@
//@[mips] needs-llvm-components: mips
//@[thumb] compile-flags: --target thumbv7neon-linux-androideabi
//@[thumb] needs-llvm-components: arm
-//@[sparc] compile-flags: --target sparc-unknown-linux-gnu
-//@[sparc] needs-llvm-components: sparc
// See ./transparent.rs
// Some platforms pass large aggregates using immediate arrays in LLVMIR
diff --git a/tests/debuginfo/basic-types-globals-metadata.rs b/tests/debuginfo/basic-types-globals-metadata.rs
index 3f1d9fd5de278..306c8978a508e 100644
--- a/tests/debuginfo/basic-types-globals-metadata.rs
+++ b/tests/debuginfo/basic-types-globals-metadata.rs
@@ -33,11 +33,13 @@
//@ gdb-check:type = f32
//@ gdb-command:whatis basic_types_globals_metadata::F64
//@ gdb-check:type = f64
+//@ gdb-command:whatis basic_types_globals_metadata::F128
+//@ gdb-check:type = f128
//@ gdb-command:continue
#![allow(unused_variables)]
#![allow(dead_code)]
-#![feature(f16)]
+#![feature(f16, f128)]
// N.B. These are `mut` only so they don't constant fold away.
static mut B: bool = false;
@@ -55,13 +57,14 @@ static mut U64: u64 = 64;
static mut F16: f16 = 1.5;
static mut F32: f32 = 2.5;
static mut F64: f64 = 3.5;
+static mut F128: f128 = 4.5;
fn main() {
_zzz(); // #break
- let a = unsafe { (B, I, C, I8, I16, I32, I64, U, U8, U16, U32, U64, F32, F64) };
- // FIXME: Including f16 and f32 in the same tuple emits `__gnu_h2f_ieee`, which
- // does not exist on some targets like PowerPC.
+ let a = unsafe { (B, I, C, I8, I16, I32, I64, U, U8, U16, U32, U64, F32, F64, F128) };
+ // FIXME(f16): Including f16 and f32 in the same tuple emits `__gnu_h2f_ieee`, which
+ // does not exist on some targets like PowerPC (fixed in llvm22).
// See https://github.com/llvm/llvm-project/issues/97981 and
// https://github.com/rust-lang/compiler-builtins/issues/655
let b = unsafe { F16 };
diff --git a/tests/debuginfo/basic-types-globals.rs b/tests/debuginfo/basic-types-globals.rs
index 044b757aaf470..3bc9d3becdade 100644
--- a/tests/debuginfo/basic-types-globals.rs
+++ b/tests/debuginfo/basic-types-globals.rs
@@ -1,11 +1,20 @@
-//@ revisions: lto no-lto
+//@ revisions: lto no-lto lto-apple no-lto-apple
//@ compile-flags:-g --crate-name=basic_types_globals
//@ disable-gdb-pretty-printers
+// FIXME(f128): Merge `-apple` revisions once Apple releases Xcode with LLVM 22.
+//@ [lto] ignore-apple
+//@ [no-lto] ignore-apple
+//@ [lto-apple] only-apple
+//@ [no-lto-apple] only-apple
//@ [lto] compile-flags:-C lto
//@ [lto] no-prefer-dynamic
+//@ [lto-apple] compile-flags:-C lto
+//@ [lto-apple] no-prefer-dynamic
//@ ignore-backends: gcc
+// `f128` support was added to `lldb` in version 22.
+//@ min-llvm-lldb-version: 22
//@ lldb-command:run
//@ lldb-command:v basic_types_globals::B
@@ -38,6 +47,9 @@
//@ lldb-check:[...]basic_types_globals::F32 = 2.5
//@ lldb-command:v basic_types_globals::F64
//@ lldb-check:[...]basic_types_globals::F64 = 3.5
+//@ lldb-command:v basic_types_globals::F128
+//@[no-lto] lldb-check:[...]basic_types_globals::F128 = 4.5
+//@[lto] lldb-check:[...]basic_types_globals::F128 = 4.5
//@ gdb-command:run
//@ gdb-command:print B
@@ -70,10 +82,11 @@
//@ gdb-check:$14 = 2.5
//@ gdb-command:print F64
//@ gdb-check:$15 = 3.5
+// FIXME(f128): gdb doesn't support Rust `f128` yet.
//@ gdb-command:continue
#![allow(unused_variables)]
-#![feature(f16)]
+#![feature(f16, f128)]
// N.B. These are `mut` only so they don't constant fold away.
static mut B: bool = false;
@@ -91,13 +104,14 @@ static mut U64: u64 = 64;
static mut F16: f16 = 1.5;
static mut F32: f32 = 2.5;
static mut F64: f64 = 3.5;
+static mut F128: f128 = 4.5;
fn main() {
_zzz(); // #break
- let a = unsafe { (B, I, C, I8, I16, I32, I64, U, U8, U16, U32, U64, F32, F64) };
- // FIXME: Including f16 and f32 in the same tuple emits `__gnu_h2f_ieee`, which
- // does not exist on some targets like PowerPC.
+ let a = unsafe { (B, I, C, I8, I16, I32, I64, U, U8, U16, U32, U64, F32, F64, F128) };
+ // FIXME(f16): Including f16 and f32 in the same tuple emits `__gnu_h2f_ieee`, which
+ // does not exist on some targets like PowerPC (fixed in llvm22).
// See https://github.com/llvm/llvm-project/issues/97981 and
// https://github.com/rust-lang/compiler-builtins/issues/655
let b = unsafe { F16 };
diff --git a/tests/debuginfo/basic-types-metadata.rs b/tests/debuginfo/basic-types-metadata.rs
index d3a3d03ef7424..39fa9150214b5 100644
--- a/tests/debuginfo/basic-types-metadata.rs
+++ b/tests/debuginfo/basic-types-metadata.rs
@@ -35,6 +35,8 @@
//@ gdb-check:type = f32
//@ gdb-command:whatis f64
//@ gdb-check:type = f64
+//@ gdb-command:whatis f128
+//@ gdb-check:type = f128
//@ gdb-command:whatis fnptr
//@ gdb-check:type = *mut fn ()
//@ gdb-command:info functions _yyy
@@ -54,7 +56,7 @@
//@ gdb-command:continue
#![allow(unused_variables)]
-#![feature(f16)]
+#![feature(f16, f128)]
fn main() {
let unit: () = ();
@@ -73,6 +75,7 @@ fn main() {
let f16: f16 = 1.5;
let f32: f32 = 2.5;
let f64: f64 = 3.5;
+ let f128: f128 = 4.5;
let fnptr : fn() = _zzz;
let closure_0 = || {};
let closure_1 = || { b; };
diff --git a/tests/debuginfo/basic-types-mut-globals.rs b/tests/debuginfo/basic-types-mut-globals.rs
index c3cc7be549d47..3f59da2a5d2e0 100644
--- a/tests/debuginfo/basic-types-mut-globals.rs
+++ b/tests/debuginfo/basic-types-mut-globals.rs
@@ -1,13 +1,14 @@
-// Caveats - gdb prints any 8-bit value (meaning rust I8 and u8 values)
-// as its numerical value along with its associated ASCII char, there
-// doesn't seem to be any way around this. Also, gdb doesn't know
-// about UTF-32 character encoding and will print a rust char as only
-// its numerical value.
-
-//@ compile-flags:-g
+//@ compile-flags:-g --crate-name=basic_types_mut_globals
//@ disable-gdb-pretty-printers
//@ ignore-backends: gcc
+// FIXME(f128): Merge `apple` revision once Apple releases Xcode with LLVM 22.
+//@ revisions: not-apple apple
+//@[not-apple] ignore-apple
+//@[apple] only-apple
+// `f128` support was added to `lldb` in version 22.
+//@ min-llvm-lldb-version: 22
+
//@ gdb-command:run
// Check initializers
@@ -41,6 +42,7 @@
//@ gdb-check:$14 = 2.5
//@ gdb-command:print F64
//@ gdb-check:$15 = 3.5
+// FIXME(f128): gdb doesn't support Rust `f128` yet.
//@ gdb-command:continue
// Check new values
@@ -50,7 +52,7 @@
//@ gdb-check:$17 = 2
//@ gdb-command:print C
//@ gdb-check:$18 = 102 'f'
-//@ gdb-command:print/d I8
+//@ gdb-command:print I8
//@ gdb-check:$19 = 78
//@ gdb-command:print I16
//@ gdb-check:$20 = -26
@@ -60,7 +62,7 @@
//@ gdb-check:$22 = -54
//@ gdb-command:print U
//@ gdb-check:$23 = 5
-//@ gdb-command:print/d U8
+//@ gdb-command:print U8
//@ gdb-check:$24 = 20
//@ gdb-command:print U16
//@ gdb-check:$25 = 32
@@ -74,9 +76,81 @@
//@ gdb-check:$29 = 5.75
//@ gdb-command:print F64
//@ gdb-check:$30 = 9.25
+// FIXME(f128): gdb doesn't support Rust `f128` yet.
+
+//@ lldb-command:run
+
+// Check initializers
+//@ lldb-command:v basic_types_mut_globals::B
+//@ lldb-check:[...]basic_types_mut_globals::B = false
+//@ lldb-command:v basic_types_mut_globals::I
+//@ lldb-check:[...]basic_types_mut_globals::I = -1
+//@ lldb-command:v basic_types_mut_globals::C
+//@ lldb-check:[...]basic_types_mut_globals::C = U+0x00000061 U'a'
+//@ lldb-command:v/d basic_types_mut_globals::I8
+//@ lldb-check:[...]basic_types_mut_globals::I8 = 68
+//@ lldb-command:v basic_types_mut_globals::I16
+//@ lldb-check:[...]basic_types_mut_globals::I16 = -16
+//@ lldb-command:v basic_types_mut_globals::I32
+//@ lldb-check:[...]basic_types_mut_globals::I32 = -32
+//@ lldb-command:v basic_types_mut_globals::I64
+//@ lldb-check:[...]basic_types_mut_globals::I64 = -64
+//@ lldb-command:v basic_types_mut_globals::U
+//@ lldb-check:[...]basic_types_mut_globals::U = 1
+//@ lldb-command:v/d basic_types_mut_globals::U8
+//@ lldb-check:[...]basic_types_mut_globals::U8 = 100
+//@ lldb-command:v basic_types_mut_globals::U16
+//@ lldb-check:[...]basic_types_mut_globals::U16 = 16
+//@ lldb-command:v basic_types_mut_globals::U32
+//@ lldb-check:[...]basic_types_mut_globals::U32 = 32
+//@ lldb-command:v basic_types_mut_globals::U64
+//@ lldb-check:[...]basic_types_mut_globals::U64 = 64
+//@ lldb-command:v basic_types_mut_globals::F16
+//@ lldb-check:[...]basic_types_mut_globals::F16 = 1.5
+//@ lldb-command:v basic_types_mut_globals::F32
+//@ lldb-check:[...]basic_types_mut_globals::F32 = 2.5
+//@ lldb-command:v basic_types_mut_globals::F64
+//@ lldb-check:[...]basic_types_mut_globals::F64 = 3.5
+//@ lldb-command:v basic_types_mut_globals::F128
+//@[not-apple] lldb-check:[...]basic_types_mut_globals::F128 = 4.5
+//@ lldb-command:continue
+
+// Check new values
+//@ lldb-command:v basic_types_mut_globals::B
+//@ lldb-check:[...]basic_types_mut_globals::B = true
+//@ lldb-command:v basic_types_mut_globals::I
+//@ lldb-check:[...]basic_types_mut_globals::I = 2
+//@ lldb-command:v basic_types_mut_globals::C
+//@ lldb-check:[...]basic_types_mut_globals::C = U+0x00000066 U'f'
+//@ lldb-command:v/d basic_types_mut_globals::I8
+//@ lldb-check:[...]basic_types_mut_globals::I8 = 78
+//@ lldb-command:v basic_types_mut_globals::I16
+//@ lldb-check:[...]basic_types_mut_globals::I16 = -26
+//@ lldb-command:v basic_types_mut_globals::I32
+//@ lldb-check:[...]basic_types_mut_globals::I32 = -12
+//@ lldb-command:v basic_types_mut_globals::I64
+//@ lldb-check:[...]basic_types_mut_globals::I64 = -54
+//@ lldb-command:v basic_types_mut_globals::U
+//@ lldb-check:[...]basic_types_mut_globals::U = 5
+//@ lldb-command:v/d basic_types_mut_globals::U8
+//@ lldb-check:[...]basic_types_mut_globals::U8 = 20
+//@ lldb-command:v basic_types_mut_globals::U16
+//@ lldb-check:[...]basic_types_mut_globals::U16 = 32
+//@ lldb-command:v basic_types_mut_globals::U32
+//@ lldb-check:[...]basic_types_mut_globals::U32 = 16
+//@ lldb-command:v basic_types_mut_globals::U64
+//@ lldb-check:[...]basic_types_mut_globals::U64 = 128
+//@ lldb-command:v basic_types_mut_globals::F16
+//@ lldb-check:[...]basic_types_mut_globals::F16 = 2.25
+//@ lldb-command:v basic_types_mut_globals::F32
+//@ lldb-check:[...]basic_types_mut_globals::F32 = 5.75
+//@ lldb-command:v basic_types_mut_globals::F64
+//@ lldb-check:[...]basic_types_mut_globals::F64 = 9.25
+//@ lldb-command:v basic_types_mut_globals::F128
+//@[not-apple] lldb-check:[...]basic_types_mut_globals::F128 = 12.75
#![allow(unused_variables)]
-#![feature(f16)]
+#![feature(f16, f128)]
static mut B: bool = false;
static mut I: isize = -1;
@@ -93,6 +167,7 @@ static mut U64: u64 = 64;
static mut F16: f16 = 1.5;
static mut F32: f32 = 2.5;
static mut F64: f64 = 3.5;
+static mut F128: f128 = 4.5;
fn main() {
_zzz(); // #break
@@ -113,6 +188,7 @@ fn main() {
F16 = 2.25;
F32 = 5.75;
F64 = 9.25;
+ F128 = 12.75;
}
_zzz(); // #break
diff --git a/tests/debuginfo/basic-types/main.rs b/tests/debuginfo/basic-types/main.rs
index 9f61862c0dfd8..d01e51036f201 100644
--- a/tests/debuginfo/basic-types/main.rs
+++ b/tests/debuginfo/basic-types/main.rs
@@ -1,9 +1,3 @@
-// Caveats - gdb prints any 8-bit value (meaning rust i8 and u8 values)
-// as its numerical value along with its associated ASCII char, there
-// doesn't seem to be any way around this. Also, gdb doesn't know
-// about UTF-32 character encoding and will print a rust char as only
-// its numerical value.
-
//@ compile-flags:-g
//@ disable-gdb-pretty-printers
//@ ignore-backends: gcc
@@ -32,6 +26,7 @@
//@ gdb-repr:f16
//@ gdb-repr:f32
//@ gdb-repr:f64
+// FIXME(f128): gdb doesn't support Rust `f128` yet.
//@ gdb-repr:s
// === LLDB TESTS ==================================================================================
@@ -85,13 +80,16 @@
//@ cdb-check:f32 : 2.500000 [Type: float]
//@ cdb-command:dx f64
//@ cdb-check:f64 : 3.500000 [Type: double]
+//@ cdb-command:dx f128
+//@ cdb-check:f128 : 0x1.2p+2 [Type: f128]
+//@ cdb-check:bits : 0x40012000000000000000000000000000
//@ cdb-command:.enable_unicode 1
// FIXME(#88840): The latest version of the Windows SDK broke the visualizer for str.
//@ cdb-command:dx s
//@ cdb-check:s : [...] [Type: ref$]
#![allow(unused_variables)]
-#![feature(f16)]
+#![feature(f16, f128)]
fn main() {
let b: bool = false;
@@ -109,6 +107,7 @@ fn main() {
let f16: f16 = 1.5;
let f32: f32 = 2.5;
let f64: f64 = 3.5;
+ let f128: f128 = 4.5;
let s: &str = "Hello, World!";
_zzz(); // #break
}
diff --git a/tests/debuginfo/borrowed-basic.rs b/tests/debuginfo/borrowed-basic.rs
index f7b7d2cbd810c..2872bc65fac3f 100644
--- a/tests/debuginfo/borrowed-basic.rs
+++ b/tests/debuginfo/borrowed-basic.rs
@@ -2,6 +2,13 @@
//@ disable-gdb-pretty-printers
//@ ignore-backends: gcc
+// FIXME(f128): Merge `apple` revision once Apple releases Xcode with LLVM 22.
+//@ revisions: not-apple apple
+//@[not-apple] ignore-apple
+//@[apple] only-apple
+// `f128` support was added to `lldb` in version 22.
+//@ min-llvm-lldb-version: 22
+
// === GDB TESTS ===================================================================================
//@ gdb-command:run
@@ -50,6 +57,8 @@
//@ gdb-command:print *f64_ref
//@ gdb-check:$15 = 3.5
+// FIXME(f128): gdb doesn't support Rust `f128` yet.
+
// === LLDB TESTS ==================================================================================
@@ -99,8 +108,11 @@
//@ lldb-command:v *f64_ref
//@ lldb-check:[...] 3.5
+//@ lldb-command:v *f128_ref
+//@[not-apple] lldb-check:[...] 4.5
+
#![allow(unused_variables)]
-#![feature(f16)]
+#![feature(f16, f128)]
fn main() {
let bool_val: bool = true;
@@ -148,6 +160,9 @@ fn main() {
let f64_val: f64 = 3.5;
let f64_ref: &f64 = &f64_val;
+ let f128_val: f128 = 4.5;
+ let f128_ref: &f128 = &f128_val;
+
zzz(); // #break
}
diff --git a/tests/debuginfo/borrowed-unique-basic.rs b/tests/debuginfo/borrowed-unique-basic.rs
index 17939239c0dea..0d1fdec0f58d1 100644
--- a/tests/debuginfo/borrowed-unique-basic.rs
+++ b/tests/debuginfo/borrowed-unique-basic.rs
@@ -2,6 +2,13 @@
//@ disable-gdb-pretty-printers
//@ ignore-backends: gcc
+// FIXME(f128): Merge `apple` revision once Apple releases Xcode with LLVM 22.
+//@ revisions: not-apple apple
+//@[not-apple] ignore-apple
+//@[apple] only-apple
+// `f128` support was added to `lldb` in version 22.
+//@ min-llvm-lldb-version: 22
+
// === GDB TESTS ===================================================================================
//@ gdb-command:run
@@ -51,6 +58,8 @@
//@ gdb-command:print *f64_ref
//@ gdb-check:$15 = 3.5
+// FIXME(f128): gdb doesn't support Rust `f128` yet.
+
// === LLDB TESTS ==================================================================================
@@ -102,8 +111,11 @@
//@ lldb-command:v *f64_ref
//@ lldb-check:[...] 3.5
+//@ lldb-command:v *f128_ref
+//@[not-apple] lldb-check:[...] 4.5
+
#![allow(unused_variables)]
-#![feature(f16)]
+#![feature(f16, f128)]
fn main() {
let bool_box: Box = Box::new(true);
@@ -151,6 +163,9 @@ fn main() {
let f64_box: Box = Box::new(3.5);
let f64_ref: &f64 = &*f64_box;
+ let f128_box: Box = Box::new(4.5);
+ let f128_ref: &f128 = &*f128_box;
+
zzz(); // #break
}
diff --git a/tests/debuginfo/f128-natvis.rs b/tests/debuginfo/f128-natvis.rs
new file mode 100644
index 0000000000000..5f91014cfe5db
--- /dev/null
+++ b/tests/debuginfo/f128-natvis.rs
@@ -0,0 +1,92 @@
+//@ compile-flags: -g
+//@ only-msvc
+
+// This tests the `f128` Natvis visualiser.
+//@ cdb-command:g
+//@ cdb-command:dx v0_0
+//@ cdb-check:v0_0 : 0x0p+0 [Type: f128]
+//@ cdb-check:bits : 0x00000000000000000000000000000000
+//@ cdb-command:dx neg_0_0
+//@ cdb-check:neg_0_0 : -0x0p+0 [Type: f128]
+//@ cdb-check:bits : 0x80000000000000000000000000000000
+//@ cdb-command:dx v1_0
+//@ cdb-check:v1_0 : 0x1p+0 [Type: f128]
+//@ cdb-check:bits : 0x3fff0000000000000000000000000000
+//@ cdb-command:dx v1_5
+//@ cdb-check:v1_5 : 0x1.8p+0 [Type: f128]
+//@ cdb-check:bits : 0x3fff8000000000000000000000000000
+//@ cdb-command:dx v72_3
+//@ cdb-check:v72_3 : 0x1.2133333333333333333333333333p+6 [Type: f128]
+//@ cdb-check:bits : 0x40052133333333333333333333333333
+//@ cdb-command:dx neg_0_126
+//@ cdb-check:neg_0_126 : -0x1.020c49ba5e353f7ced916872b021p-3 [Type: f128]
+//@ cdb-check:bits : 0xbffc020c49ba5e353f7ced916872b021
+//@ cdb-command:dx v0_00003
+//@ cdb-check:v0_00003 : 0x1.f75104d551d68c692f6e82949a56p-16 [Type: f128]
+//@ cdb-check:bits : 0x3feff75104d551d68c692f6e82949a56
+//@ cdb-command:dx neg_0_00004
+//@ cdb-check:neg_0_00004 : -0x1.4f8b588e368f08461f9f01b866e4p-15 [Type: f128]
+//@ cdb-check:bits : 0xbff04f8b588e368f08461f9f01b866e4
+//@ cdb-command:dx very_small
+//@ cdb-check:very_small : 0x1p-16494 [Type: f128]
+//@ cdb-check:bits : 0x00000000000000000000000000000001
+//@ cdb-command:dx not_quite_as_small
+//@ cdb-check:not_quite_as_small : 0x1.8p-16385 [Type: f128]
+//@ cdb-check:bits : 0x00003000000000000000000000000000
+//@ cdb-command:dx smallest_pos_normal
+//@ cdb-check:smallest_pos_normal : 0x1p-16382 [Type: f128]
+//@ cdb-check:bits : 0x00010000000000000000000000000000
+//@ cdb-command:dx smallest_subnormal
+//@ cdb-check:smallest_subnormal : -0x1.fffffffffffffffffffffffffffep-16383 [Type: f128]
+//@ cdb-check:bits : 0x8000ffffffffffffffffffffffffffff
+//@ cdb-command:dx just_above
+//@ cdb-check:just_above : -0x1.ffffffffffffffffffffffffff8p-1 [Type: f128]
+//@ cdb-check:bits : 0xbffeffffffffffffffffffffffffff80
+//@ cdb-command:dx max
+//@ cdb-check:max : 0x1.ffffffffffffffffffffffffffffp+16383 [Type: f128]
+//@ cdb-check:bits : 0x7ffeffffffffffffffffffffffffffff
+//@ cdb-command:dx min
+//@ cdb-check:min : -0x1.ffffffffffffffffffffffffffffp+16383 [Type: f128]
+//@ cdb-check:bits : 0xfffeffffffffffffffffffffffffffff
+//@ cdb-command:dx inf
+//@ cdb-check:inf : inf [Type: f128]
+//@ cdb-check:bits : 0x7fff0000000000000000000000000000
+//@ cdb-command:dx neg_inf
+//@ cdb-check:neg_inf : -inf [Type: f128]
+//@ cdb-check:bits : 0xffff0000000000000000000000000000
+//@ cdb-command:dx nan
+//@ cdb-check:nan : NaN [Type: f128]
+//@ cdb-check:bits : 0x7fff8000000000000000000000000000
+//@ cdb-command:dx other_nan
+//@ cdb-check:other_nan : NaN [Type: f128]
+//@ cdb-check:bits : 0xffff123456789abcdef123456789abcd
+
+#![feature(f128)]
+
+fn main() {
+ let v0_0 = 0.0_f128;
+ let neg_0_0 = -0.0_f128;
+ let v1_0 = 1.0_f128;
+ let v1_5 = 1.5_f128;
+ let v72_3 = 72.3_f128;
+ let neg_0_126 = -0.126_f128;
+ let v0_00003 = 0.00003_f128;
+ let neg_0_00004 = -0.00004_f128;
+ let very_small = 0.0_f128.next_up();
+ let not_quite_as_small = const { f128::MIN_POSITIVE / 8.0 + f128::MIN_POSITIVE / 16.0 };
+ let smallest_pos_normal = f128::MIN_POSITIVE;
+ let smallest_subnormal = (-f128::MIN_POSITIVE).next_up();
+ let just_above = const { -1.0 + f128::EPSILON * 64.0 };
+ let max = f128::MAX;
+ let min = f128::MIN;
+ let inf = f128::INFINITY;
+ let neg_inf = f128::NEG_INFINITY;
+ let nan = f128::NAN;
+ let other_nan = f128::from_bits(0xffff_1234_5678_9abc_def1_2345_6789_abcd);
+
+ _zzz(); // #break
+}
+
+fn _zzz() {
+ ()
+}
diff --git a/tests/debuginfo/reference-debuginfo.rs b/tests/debuginfo/reference-debuginfo.rs
index 518e1dac2885e..495dde379da7e 100644
--- a/tests/debuginfo/reference-debuginfo.rs
+++ b/tests/debuginfo/reference-debuginfo.rs
@@ -2,10 +2,18 @@
// That pass replaces debuginfo for `a => _x` where `_x = &b` to be `a => &b`,
// and leaves codegen to create a ladder of allocations so as `*a == b`.
//
+// FIXME: Currently emits warning: MIR pass `ConstDebugInfo` is unknown and will be ignored
//@ compile-flags:-g -Zmir-enable-passes=+ReferencePropagation,-ConstDebugInfo
//@ disable-gdb-pretty-printers
//@ ignore-backends: gcc
+// FIXME(f128): Merge `apple` revision once Apple releases Xcode with LLVM 22.
+//@ revisions: not-apple apple
+//@[not-apple] ignore-apple
+//@[apple] only-apple
+// `f128` support was added to `lldb` in version 22.
+//@ min-llvm-lldb-version: 22
+
// === GDB TESTS ===================================================================================
//@ gdb-command:run
@@ -54,6 +62,8 @@
//@ gdb-command:print *f64_ref
//@ gdb-check:$15 = 3.5
+// FIXME(f128): gdb doesn't support Rust `f128` yet.
+
//@ gdb-command:print *f64_double_ref
//@ gdb-check:$16 = 3.5
@@ -106,11 +116,14 @@
//@ lldb-command:v *f64_ref
//@ lldb-check:[...] 3.5
+//@ lldb-command:v *f128_ref
+//@[not-apple] lldb-check:[...] 4.5
+
//@ lldb-command:v *f64_double_ref
//@ lldb-check:[...] 3.5
#![allow(unused_variables)]
-#![feature(f16)]
+#![feature(f16, f128)]
fn main() {
let bool_val: bool = true;
@@ -159,6 +172,9 @@ fn main() {
let f64_ref: &f64 = &f64_val;
let f64_double_ref: &f64 = &f64_ref;
+ let f128_val: f128 = 4.5;
+ let f128_ref: &f128 = &f128_val;
+
zzz(); // #break
}
diff --git a/tests/rustdoc-html/slice-links.link_box_generic.html b/tests/rustdoc-html/codeblock/slice-links.link_box_generic.html
similarity index 100%
rename from tests/rustdoc-html/slice-links.link_box_generic.html
rename to tests/rustdoc-html/codeblock/slice-links.link_box_generic.html
diff --git a/tests/rustdoc-html/slice-links.link_box_u32.html b/tests/rustdoc-html/codeblock/slice-links.link_box_u32.html
similarity index 100%
rename from tests/rustdoc-html/slice-links.link_box_u32.html
rename to tests/rustdoc-html/codeblock/slice-links.link_box_u32.html
diff --git a/tests/rustdoc-html/slice-links.link_slice_generic.html b/tests/rustdoc-html/codeblock/slice-links.link_slice_generic.html
similarity index 100%
rename from tests/rustdoc-html/slice-links.link_slice_generic.html
rename to tests/rustdoc-html/codeblock/slice-links.link_slice_generic.html
diff --git a/tests/rustdoc-html/slice-links.link_slice_u32.html b/tests/rustdoc-html/codeblock/slice-links.link_slice_u32.html
similarity index 100%
rename from tests/rustdoc-html/slice-links.link_slice_u32.html
rename to tests/rustdoc-html/codeblock/slice-links.link_slice_u32.html
diff --git a/tests/rustdoc-html/slice-links.rs b/tests/rustdoc-html/codeblock/slice-links.rs
similarity index 100%
rename from tests/rustdoc-html/slice-links.rs
rename to tests/rustdoc-html/codeblock/slice-links.rs
diff --git a/tests/rustdoc-html/tuples.link1_i32.html b/tests/rustdoc-html/codeblock/tuples.link1_i32.html
similarity index 100%
rename from tests/rustdoc-html/tuples.link1_i32.html
rename to tests/rustdoc-html/codeblock/tuples.link1_i32.html
diff --git a/tests/rustdoc-html/tuples.link1_t.html b/tests/rustdoc-html/codeblock/tuples.link1_t.html
similarity index 100%
rename from tests/rustdoc-html/tuples.link1_t.html
rename to tests/rustdoc-html/codeblock/tuples.link1_t.html
diff --git a/tests/rustdoc-html/tuples.link2_i32.html b/tests/rustdoc-html/codeblock/tuples.link2_i32.html
similarity index 100%
rename from tests/rustdoc-html/tuples.link2_i32.html
rename to tests/rustdoc-html/codeblock/tuples.link2_i32.html
diff --git a/tests/rustdoc-html/tuples.link2_t.html b/tests/rustdoc-html/codeblock/tuples.link2_t.html
similarity index 100%
rename from tests/rustdoc-html/tuples.link2_t.html
rename to tests/rustdoc-html/codeblock/tuples.link2_t.html
diff --git a/tests/rustdoc-html/tuples.link2_tu.html b/tests/rustdoc-html/codeblock/tuples.link2_tu.html
similarity index 100%
rename from tests/rustdoc-html/tuples.link2_tu.html
rename to tests/rustdoc-html/codeblock/tuples.link2_tu.html
diff --git a/tests/rustdoc-html/tuples.link_unit.html b/tests/rustdoc-html/codeblock/tuples.link_unit.html
similarity index 100%
rename from tests/rustdoc-html/tuples.link_unit.html
rename to tests/rustdoc-html/codeblock/tuples.link_unit.html
diff --git a/tests/rustdoc-html/tuples.rs b/tests/rustdoc-html/codeblock/tuples.rs
similarity index 100%
rename from tests/rustdoc-html/tuples.rs
rename to tests/rustdoc-html/codeblock/tuples.rs
diff --git a/tests/rustdoc-html/deref-mut-35169-2.rs b/tests/rustdoc-html/deref/deref-mut-35169-2.rs
similarity index 100%
rename from tests/rustdoc-html/deref-mut-35169-2.rs
rename to tests/rustdoc-html/deref/deref-mut-35169-2.rs
diff --git a/tests/rustdoc-html/deref-mut-35169.rs b/tests/rustdoc-html/deref/deref-mut-35169.rs
similarity index 100%
rename from tests/rustdoc-html/deref-mut-35169.rs
rename to tests/rustdoc-html/deref/deref-mut-35169.rs
diff --git a/tests/rustdoc-html/link-on-path-with-generics.rs b/tests/rustdoc-html/jump-to-def/link-on-path-with-generics.rs
similarity index 100%
rename from tests/rustdoc-html/link-on-path-with-generics.rs
rename to tests/rustdoc-html/jump-to-def/link-on-path-with-generics.rs
diff --git a/tests/rustdoc-html/attributes-inlining-108281.rs b/tests/rustdoc-html/reexport/attributes-inlining-108281.rs
similarity index 100%
rename from tests/rustdoc-html/attributes-inlining-108281.rs
rename to tests/rustdoc-html/reexport/attributes-inlining-108281.rs
diff --git a/tests/rustdoc-html/attributes-re-export-2021-edition.rs b/tests/rustdoc-html/reexport/attributes-re-export-2021-edition.rs
similarity index 100%
rename from tests/rustdoc-html/attributes-re-export-2021-edition.rs
rename to tests/rustdoc-html/reexport/attributes-re-export-2021-edition.rs
diff --git a/tests/rustdoc-html/attributes-re-export.rs b/tests/rustdoc-html/reexport/attributes-re-export.rs
similarity index 100%
rename from tests/rustdoc-html/attributes-re-export.rs
rename to tests/rustdoc-html/reexport/attributes-re-export.rs
diff --git a/tests/rustdoc-html/glob-shadowing.rs b/tests/rustdoc-html/reexport/glob-shadowing.rs
similarity index 100%
rename from tests/rustdoc-html/glob-shadowing.rs
rename to tests/rustdoc-html/reexport/glob-shadowing.rs
diff --git a/tests/rustdoc-html/namespaces.rs b/tests/rustdoc-html/reexport/namespaces.rs
similarity index 100%
rename from tests/rustdoc-html/namespaces.rs
rename to tests/rustdoc-html/reexport/namespaces.rs
diff --git a/tests/rustdoc-html/logo-class-default.rs b/tests/rustdoc-html/sidebar/logo-class-default.rs
similarity index 100%
rename from tests/rustdoc-html/logo-class-default.rs
rename to tests/rustdoc-html/sidebar/logo-class-default.rs
diff --git a/tests/rustdoc-html/logo-class-rust.rs b/tests/rustdoc-html/sidebar/logo-class-rust.rs
similarity index 100%
rename from tests/rustdoc-html/logo-class-rust.rs
rename to tests/rustdoc-html/sidebar/logo-class-rust.rs
diff --git a/tests/rustdoc-html/logo-class.rs b/tests/rustdoc-html/sidebar/logo-class.rs
similarity index 100%
rename from tests/rustdoc-html/logo-class.rs
rename to tests/rustdoc-html/sidebar/logo-class.rs
diff --git a/tests/ui/abi/c-zst.aarch64-darwin.stderr b/tests/ui/abi/c-zst.aarch64-darwin.stderr
index 6d2ac90c0c975..2ed9ffdf791f6 100644
--- a/tests/ui/abi/c-zst.aarch64-darwin.stderr
+++ b/tests/ui/abi/c-zst.aarch64-darwin.stderr
@@ -60,7 +60,7 @@ error: fn_abi_of(pass_zst) = FnAbi {
conv: C,
can_unwind: false,
}
- --> $DIR/c-zst.rs:65:1
+ --> $DIR/c-zst.rs:67:1
|
LL | extern "C" fn pass_zst(_: ()) {}
| ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
diff --git a/tests/ui/abi/c-zst.powerpc-linux.stderr b/tests/ui/abi/c-zst.powerpc-linux.stderr
index edea2d5772280..302ffe1efc8b8 100644
--- a/tests/ui/abi/c-zst.powerpc-linux.stderr
+++ b/tests/ui/abi/c-zst.powerpc-linux.stderr
@@ -71,7 +71,7 @@ error: fn_abi_of(pass_zst) = FnAbi {
conv: C,
can_unwind: false,
}
- --> $DIR/c-zst.rs:65:1
+ --> $DIR/c-zst.rs:67:1
|
LL | extern "C" fn pass_zst(_: ()) {}
| ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
diff --git a/tests/ui/abi/c-zst.rs b/tests/ui/abi/c-zst.rs
index 22cb3f98f28dc..973f5f0002f25 100644
--- a/tests/ui/abi/c-zst.rs
+++ b/tests/ui/abi/c-zst.rs
@@ -15,9 +15,9 @@ extern "C" fn(i32, (), i32);
```
*/
-/*
- * ZST IN "C" IS ZERO-SIZED
- */
+//
+// ZST IN "C" IS ZERO-SIZED
+//
//@ revisions: aarch64-darwin
//@[aarch64-darwin] compile-flags: --target aarch64-apple-darwin
@@ -27,10 +27,9 @@ extern "C" fn(i32, (), i32);
//@[x86_64-linux] compile-flags: --target x86_64-unknown-linux-gnu
//@[x86_64-linux] needs-llvm-components: x86
-
-/*
- * ZST IN "C" IS PASS-BY-POINTER
- */
+//
+// ZST IN "C" IS PASS-BY-POINTER
+//
// according to the SRV4 ABI, an aggregate is always passed in registers,
// and it so happens the GCC extension for ZSTs considers them as structs.
@@ -42,7 +41,11 @@ extern "C" fn(i32, (), i32);
//@[s390x-linux] compile-flags: --target s390x-unknown-linux-gnu
//@[s390x-linux] needs-llvm-components: systemz
-//@ revisions: sparc64-linux
+//@ revisions: sparc-none sparc-linux sparc64-linux
+//@[sparc-none] compile-flags: --target sparc-unknown-none-elf
+//@[sparc-none] needs-llvm-components: sparc
+//@[sparc-linux] compile-flags: --target sparc-unknown-linux-gnu
+//@[sparc-linux] needs-llvm-components: sparc
//@[sparc64-linux] compile-flags: --target sparc64-unknown-linux-gnu
//@[sparc64-linux] needs-llvm-components: sparc
@@ -53,7 +56,6 @@ extern "C" fn(i32, (), i32);
//@[x86_64-pc-windows-gnu] needs-llvm-components: x86
//@ ignore-backends: gcc
-
#![feature(no_core, rustc_attrs)]
#![no_core]
#![crate_type = "lib"]
diff --git a/tests/ui/abi/c-zst.s390x-linux.stderr b/tests/ui/abi/c-zst.s390x-linux.stderr
index edea2d5772280..302ffe1efc8b8 100644
--- a/tests/ui/abi/c-zst.s390x-linux.stderr
+++ b/tests/ui/abi/c-zst.s390x-linux.stderr
@@ -71,7 +71,7 @@ error: fn_abi_of(pass_zst) = FnAbi {
conv: C,
can_unwind: false,
}
- --> $DIR/c-zst.rs:65:1
+ --> $DIR/c-zst.rs:67:1
|
LL | extern "C" fn pass_zst(_: ()) {}
| ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
diff --git a/tests/ui/abi/c-zst.sparc-linux.stderr b/tests/ui/abi/c-zst.sparc-linux.stderr
new file mode 100644
index 0000000000000..302ffe1efc8b8
--- /dev/null
+++ b/tests/ui/abi/c-zst.sparc-linux.stderr
@@ -0,0 +1,80 @@
+error: fn_abi_of(pass_zst) = FnAbi {
+ args: [
+ ArgAbi {
+ layout: TyAndLayout {
+ ty: (),
+ layout: Layout {
+ size: Size(0 bytes),
+ align: AbiAlign {
+ abi: $SOME_ALIGN,
+ },
+ backend_repr: Memory {
+ sized: true,
+ },
+ fields: Arbitrary {
+ offsets: [],
+ in_memory_order: [],
+ },
+ largest_niche: None,
+ uninhabited: false,
+ variants: Single {
+ index: 0,
+ },
+ max_repr_align: None,
+ unadjusted_abi_align: $SOME_ALIGN,
+ randomization_seed: 0,
+ },
+ },
+ mode: Indirect {
+ attrs: ArgAttributes {
+ regular: CapturesAddress | NoAlias | NonNull | NoUndef | NoFree,
+ arg_ext: None,
+ pointee_size: Size(0 bytes),
+ pointee_align: Some(
+ Align(1 bytes),
+ ),
+ },
+ meta_attrs: None,
+ on_stack: false,
+ },
+ },
+ ],
+ ret: ArgAbi {
+ layout: TyAndLayout {
+ ty: (),
+ layout: Layout {
+ size: Size(0 bytes),
+ align: AbiAlign {
+ abi: $SOME_ALIGN,
+ },
+ backend_repr: Memory {
+ sized: true,
+ },
+ fields: Arbitrary {
+ offsets: [],
+ in_memory_order: [],
+ },
+ largest_niche: None,
+ uninhabited: false,
+ variants: Single {
+ index: 0,
+ },
+ max_repr_align: None,
+ unadjusted_abi_align: $SOME_ALIGN,
+ randomization_seed: 0,
+ },
+ },
+ mode: Ignore,
+ },
+ c_variadic: false,
+ fixed_count: 1,
+ conv: C,
+ can_unwind: false,
+ }
+ --> $DIR/c-zst.rs:67:1
+ |
+LL | extern "C" fn pass_zst(_: ()) {}
+ | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+error: aborting due to 1 previous error
+
diff --git a/tests/ui/abi/c-zst.sparc-none.stderr b/tests/ui/abi/c-zst.sparc-none.stderr
new file mode 100644
index 0000000000000..302ffe1efc8b8
--- /dev/null
+++ b/tests/ui/abi/c-zst.sparc-none.stderr
@@ -0,0 +1,80 @@
+error: fn_abi_of(pass_zst) = FnAbi {
+ args: [
+ ArgAbi {
+ layout: TyAndLayout {
+ ty: (),
+ layout: Layout {
+ size: Size(0 bytes),
+ align: AbiAlign {
+ abi: $SOME_ALIGN,
+ },
+ backend_repr: Memory {
+ sized: true,
+ },
+ fields: Arbitrary {
+ offsets: [],
+ in_memory_order: [],
+ },
+ largest_niche: None,
+ uninhabited: false,
+ variants: Single {
+ index: 0,
+ },
+ max_repr_align: None,
+ unadjusted_abi_align: $SOME_ALIGN,
+ randomization_seed: 0,
+ },
+ },
+ mode: Indirect {
+ attrs: ArgAttributes {
+ regular: CapturesAddress | NoAlias | NonNull | NoUndef | NoFree,
+ arg_ext: None,
+ pointee_size: Size(0 bytes),
+ pointee_align: Some(
+ Align(1 bytes),
+ ),
+ },
+ meta_attrs: None,
+ on_stack: false,
+ },
+ },
+ ],
+ ret: ArgAbi {
+ layout: TyAndLayout {
+ ty: (),
+ layout: Layout {
+ size: Size(0 bytes),
+ align: AbiAlign {
+ abi: $SOME_ALIGN,
+ },
+ backend_repr: Memory {
+ sized: true,
+ },
+ fields: Arbitrary {
+ offsets: [],
+ in_memory_order: [],
+ },
+ largest_niche: None,
+ uninhabited: false,
+ variants: Single {
+ index: 0,
+ },
+ max_repr_align: None,
+ unadjusted_abi_align: $SOME_ALIGN,
+ randomization_seed: 0,
+ },
+ },
+ mode: Ignore,
+ },
+ c_variadic: false,
+ fixed_count: 1,
+ conv: C,
+ can_unwind: false,
+ }
+ --> $DIR/c-zst.rs:67:1
+ |
+LL | extern "C" fn pass_zst(_: ()) {}
+ | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+error: aborting due to 1 previous error
+
diff --git a/tests/ui/abi/c-zst.sparc64-linux.stderr b/tests/ui/abi/c-zst.sparc64-linux.stderr
index edea2d5772280..302ffe1efc8b8 100644
--- a/tests/ui/abi/c-zst.sparc64-linux.stderr
+++ b/tests/ui/abi/c-zst.sparc64-linux.stderr
@@ -71,7 +71,7 @@ error: fn_abi_of(pass_zst) = FnAbi {
conv: C,
can_unwind: false,
}
- --> $DIR/c-zst.rs:65:1
+ --> $DIR/c-zst.rs:67:1
|
LL | extern "C" fn pass_zst(_: ()) {}
| ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
diff --git a/tests/ui/abi/c-zst.x86_64-linux.stderr b/tests/ui/abi/c-zst.x86_64-linux.stderr
index 6d2ac90c0c975..2ed9ffdf791f6 100644
--- a/tests/ui/abi/c-zst.x86_64-linux.stderr
+++ b/tests/ui/abi/c-zst.x86_64-linux.stderr
@@ -60,7 +60,7 @@ error: fn_abi_of(pass_zst) = FnAbi {
conv: C,
can_unwind: false,
}
- --> $DIR/c-zst.rs:65:1
+ --> $DIR/c-zst.rs:67:1
|
LL | extern "C" fn pass_zst(_: ()) {}
| ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
diff --git a/tests/ui/abi/c-zst.x86_64-pc-windows-gnu.stderr b/tests/ui/abi/c-zst.x86_64-pc-windows-gnu.stderr
index edea2d5772280..302ffe1efc8b8 100644
--- a/tests/ui/abi/c-zst.x86_64-pc-windows-gnu.stderr
+++ b/tests/ui/abi/c-zst.x86_64-pc-windows-gnu.stderr
@@ -71,7 +71,7 @@ error: fn_abi_of(pass_zst) = FnAbi {
conv: C,
can_unwind: false,
}
- --> $DIR/c-zst.rs:65:1
+ --> $DIR/c-zst.rs:67:1
|
LL | extern "C" fn pass_zst(_: ()) {}
| ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
diff --git a/tests/ui/lint/rfc-2383-lint-reason/expect_inside_dead_code.rs b/tests/ui/lint/rfc-2383-lint-reason/expect_inside_dead_code.rs
new file mode 100644
index 0000000000000..8640f56f7d08d
--- /dev/null
+++ b/tests/ui/lint/rfc-2383-lint-reason/expect_inside_dead_code.rs
@@ -0,0 +1,56 @@
+//@ check-pass
+// Expectations on dead code covered by a dead parent's diagnostic must still be fulfilled.
+
+#[cfg_attr(all(), expect(unused))]
+struct Foo {
+ #[expect(unused)]
+ x: u32,
+}
+
+#[expect(dead_code)]
+struct Direct {
+ #[expect(dead_code)]
+ x: u32,
+}
+
+#[expect(unused)]
+enum DeadEnum {
+ Variant {
+ #[expect(unused)]
+ x: u32,
+ },
+}
+
+enum PartiallyDead {
+ Used,
+ #[expect(unused)]
+ Dead {
+ #[expect(unused)]
+ x: u32,
+ },
+}
+
+#[expect(unused)]
+fn dead_outer() {
+ #[expect(unused)]
+ fn dead_inner() {}
+}
+
+#[expect(unused)]
+trait DeadTrait {
+ #[expect(unused)]
+ fn dead_method(&self);
+}
+
+// `y` is read, so this expectation must stay unfulfilled.
+struct Live {
+ #[expect(unused)]
+ //~^ WARNING this lint expectation is unfulfilled
+ //~| NOTE `#[warn(unfulfilled_lint_expectations)]` on by default
+ y: u32,
+}
+
+fn main() {
+ let _ = PartiallyDead::Used;
+ let _ = Live { y: 1 }.y;
+}
diff --git a/tests/ui/lint/rfc-2383-lint-reason/expect_inside_dead_code.stderr b/tests/ui/lint/rfc-2383-lint-reason/expect_inside_dead_code.stderr
new file mode 100644
index 0000000000000..e583497561125
--- /dev/null
+++ b/tests/ui/lint/rfc-2383-lint-reason/expect_inside_dead_code.stderr
@@ -0,0 +1,10 @@
+warning: this lint expectation is unfulfilled
+ --> $DIR/expect_inside_dead_code.rs:47:14
+ |
+LL | #[expect(unused)]
+ | ^^^^^^
+ |
+ = note: `#[warn(unfulfilled_lint_expectations)]` on by default
+
+warning: 1 warning emitted
+
diff --git a/triagebot.toml b/triagebot.toml
index fc9c43d2dbcae..4f2d0a262fdc1 100644
--- a/triagebot.toml
+++ b/triagebot.toml
@@ -1549,6 +1549,14 @@ cc = ["@mejrs"]
message = "Some changes occurred to diagnostic attributes."
cc = ["@mejrs"]
+[mentions."RELEASES.md"]
+message = """
+`RELEASES.md` was changed. Upon merging, each section will be automatically synced with its \
+corresponding GitHub releases, but **only from the `main` branch**.
+
+If it's not already the case, make sure to also merge the changes in the `main` branch.
+"""
+
# Content-based mentions
[mentions."miri"]