From 7d8607d278959270e1c9e0b57681882c5c0785fd Mon Sep 17 00:00:00 2001 From: Szymon Durawa Date: Tue, 22 Oct 2024 17:13:19 +0200 Subject: [PATCH 1/3] PCI: vmd: Clean up vmd_enable_domain function This function is too long and needs to be shortened to make it more readable. Certain VMD devices like Intel Arrow Lake has two bus ranges, current implementation supports only one range. This clean up is a prework for enablement additional VMD bus range. It doesn't change functional behavior of vmd_enable_domain(). Suggested-by: Nirmal Patel Reviewed-by: Mariusz Tkaczyk Signed-off-by: Szymon Durawa --- drivers/pci/controller/vmd.c | 264 +++++++++++++++++++++-------------- 1 file changed, 163 insertions(+), 101 deletions(-) mode change 100644 => 100755 drivers/pci/controller/vmd.c diff --git a/drivers/pci/controller/vmd.c b/drivers/pci/controller/vmd.c old mode 100644 new mode 100755 index 264a180403a0ec..878e14ecad7c23 --- a/drivers/pci/controller/vmd.c +++ b/drivers/pci/controller/vmd.c @@ -34,6 +34,18 @@ #define MB2_SHADOW_OFFSET 0x2000 #define MB2_SHADOW_SIZE 16 +enum vmd_resource { + VMD_RES_CFGBAR = 0, + VMD_RES_MEMBAR_1, + VMD_RES_MEMBAR_2, + VMD_RES_COUNT +}; + +enum vmd_rootbus { + VMD_ROOTBUS_0 = 0, + VMD_ROOTBUS_COUNT +}; + enum vmd_features { /* * Device may contain registers which hint the physical location of the @@ -132,10 +144,10 @@ struct vmd_dev { struct vmd_irq_list *irqs; struct pci_sysdata sysdata; - struct resource resources[3]; + struct resource resources[VMD_RES_COUNT]; struct irq_domain *irq_domain; - struct pci_bus *bus; - u8 busn_start; + struct pci_bus *bus[VMD_ROOTBUS_COUNT]; + u8 busn_start[VMD_ROOTBUS_COUNT]; u8 first_vec; char *name; int instance; @@ -367,7 +379,7 @@ static void vmd_remove_irq_domain(struct vmd_dev *vmd) static void __iomem *vmd_cfg_addr(struct vmd_dev *vmd, struct pci_bus *bus, unsigned int devfn, int reg, int len) { - unsigned int busnr_ecam = bus->number - vmd->busn_start; + unsigned int busnr_ecam = bus->number - vmd->busn_start[VMD_ROOTBUS_0]; u32 offset = PCIE_ECAM_OFFSET(busnr_ecam, devfn, reg); if (offset + len >= resource_size(&vmd->dev->resource[VMD_CFGBAR])) @@ -505,7 +517,7 @@ static inline void vmd_acpi_end(void) { } static void vmd_domain_reset(struct vmd_dev *vmd) { - u16 bus, max_buses = resource_size(&vmd->resources[0]); + u16 bus, max_buses = resource_size(&vmd->resources[VMD_RES_CFGBAR]); u8 dev, functions, fn, hdr_type; char __iomem *base; @@ -553,8 +565,8 @@ static void vmd_domain_reset(struct vmd_dev *vmd) static void vmd_attach_resources(struct vmd_dev *vmd) { - vmd->dev->resource[VMD_MEMBAR1].child = &vmd->resources[1]; - vmd->dev->resource[VMD_MEMBAR2].child = &vmd->resources[2]; + vmd->dev->resource[VMD_MEMBAR1].child = &vmd->resources[VMD_RES_MEMBAR_1]; + vmd->dev->resource[VMD_MEMBAR2].child = &vmd->resources[VMD_RES_MEMBAR_2]; } static void vmd_detach_resources(struct vmd_dev *vmd) @@ -644,13 +656,13 @@ static int vmd_get_bus_number_start(struct vmd_dev *vmd) switch (BUS_RESTRICT_CFG(reg)) { case 0: - vmd->busn_start = 0; + vmd->busn_start[VMD_ROOTBUS_0] = 0; break; case 1: - vmd->busn_start = 128; + vmd->busn_start[VMD_ROOTBUS_0] = 128; break; case 2: - vmd->busn_start = 224; + vmd->busn_start[VMD_ROOTBUS_0] = 224; break; default: pci_err(dev, "Unknown Bus Offset Setting (%d)\n", @@ -767,17 +779,128 @@ static int vmd_pm_enable_quirk(struct pci_dev *pdev, void *userdata) return 0; } -static int vmd_enable_domain(struct vmd_dev *vmd, unsigned long features) +static void vmd_configure_cfgbar(struct vmd_dev *vmd) { - struct pci_sysdata *sd = &vmd->sysdata; - struct resource *res; + struct resource *res = &vmd->dev->resource[VMD_CFGBAR]; + + vmd->resources[VMD_RES_CFGBAR] = (struct resource){ + .name = "VMD CFGBAR", + .start = vmd->busn_start[VMD_ROOTBUS_0], + .end = vmd->busn_start[VMD_ROOTBUS_0] + + (resource_size(res) >> 20) - 1, + .flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED, + }; +} + +/** + * vmd_configure_membar - Configure VMD MemBAR register, which points + * to MMIO address assigned by the OS or BIOS. + * @vmd: the VMD device + * @resource_number: resource buffer number to be filled in + * @membar_number: name of the MemBAR + * @start_offset: 4K aligned offset applied to start of VMD’s MEMBAR MMIO space, + * may be NULL + * @end_offset: 4K aligned offset applied to end of VMD’s MEMBAR MMIO space, may + * be NULL + * @parent: parent resource assigned to resource to be filled in + * + * Function fills resource buffer inside the VMD structure. + */ +static void vmd_configure_membar(struct vmd_dev *vmd, + enum vmd_resource resource_number, + u8 membar_number, resource_size_t start_offset, + resource_size_t end_offset, + struct resource *parent) +{ + struct resource *res_parent; u32 upper_bits; unsigned long flags; + char name[16]; + + struct resource *res = &vmd->dev->resource[membar_number]; + + upper_bits = upper_32_bits(res->end); + flags = res->flags & ~IORESOURCE_SIZEALIGN; + if (!upper_bits) + flags &= ~IORESOURCE_MEM_64; + + snprintf(name, sizeof(name), "VMD MEMBAR%d", membar_number/2); + + res_parent = parent; + if (!res_parent) + res_parent = res; + + vmd->resources[resource_number] = (struct resource){ + .name = name, + .start = res->start + start_offset, + .end = res->end - end_offset, + .flags = flags, + .parent = res_parent, + }; +} + +static void vmd_configure_membar1_membar2(struct vmd_dev *vmd, + resource_size_t membar2_offset) +{ + vmd_configure_membar(vmd, VMD_RES_MEMBAR_1, VMD_MEMBAR1, 0, 0, NULL); + vmd_configure_membar(vmd, VMD_RES_MEMBAR_2, VMD_MEMBAR2, + membar2_offset, 0, NULL); +} + +static void vmd_bus_enumeration(struct pci_bus *bus, unsigned long features) +{ + struct pci_bus *child; + struct pci_dev *dev; + int ret; + + vmd_acpi_begin(); + + pci_scan_child_bus(bus); + vmd_domain_reset(vmd_from_bus(bus)); + + /* + * When Intel VMD is enabled, the OS does not discover the Root Ports + * owned by Intel VMD within the MMCFG space. pci_reset_bus() applies + * a reset to the parent of the PCI device supplied as argument. This + * is why we pass a child device, so the reset can be triggered at + * the Intel bridge level and propagated to all the children in the + * hierarchy. + */ + list_for_each_entry(child, &bus->children, node) { + if (!list_empty(&child->devices)) { + dev = list_first_entry(&child->devices, struct pci_dev, + bus_list); + ret = pci_reset_bus(dev); + if (ret) + pci_warn(dev, "can't reset device: %d\n", ret); + + break; + } + } + + pci_assign_unassigned_bus_resources(bus); + + pci_walk_bus(bus, vmd_pm_enable_quirk, &features); + + /* + * VMD root buses are virtual and don't return true on pci_is_pcie() + * and will fail pcie_bus_configure_settings() early. It can instead be + * run on each of the real root ports. + */ + list_for_each_entry(child, &bus->children, node) + pcie_bus_configure_settings(child); + + pci_bus_add_devices(bus); + + vmd_acpi_end(); +} + +static int vmd_enable_domain(struct vmd_dev *vmd, unsigned long features) +{ + struct pci_sysdata *sd = &vmd->sysdata; LIST_HEAD(resources); resource_size_t offset[2] = {0}; resource_size_t membar2_offset = 0x2000; - struct pci_bus *child; - struct pci_dev *dev; int ret; /* @@ -807,13 +930,7 @@ static int vmd_enable_domain(struct vmd_dev *vmd, unsigned long features) return ret; } - res = &vmd->dev->resource[VMD_CFGBAR]; - vmd->resources[0] = (struct resource) { - .name = "VMD CFGBAR", - .start = vmd->busn_start, - .end = vmd->busn_start + (resource_size(res) >> 20) - 1, - .flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED, - }; + vmd_configure_cfgbar(vmd); /* * If the window is below 4GB, clear IORESOURCE_MEM_64 so we can @@ -827,36 +944,12 @@ static int vmd_enable_domain(struct vmd_dev *vmd, unsigned long features) * * The only way we could use a 64-bit non-prefetchable MEMBAR is * if its address is <4GB so that we can convert it to a 32-bit - * resource. To be visible to the host OS, all VMD endpoints must + * resource. To be visible to the host OS, all VMD endpoints must * be initially configured by platform BIOS, which includes setting - * up these resources. We can assume the device is configured + * up these resources. We can assume the device is configured * according to the platform needs. */ - res = &vmd->dev->resource[VMD_MEMBAR1]; - upper_bits = upper_32_bits(res->end); - flags = res->flags & ~IORESOURCE_SIZEALIGN; - if (!upper_bits) - flags &= ~IORESOURCE_MEM_64; - vmd->resources[1] = (struct resource) { - .name = "VMD MEMBAR1", - .start = res->start, - .end = res->end, - .flags = flags, - .parent = res, - }; - - res = &vmd->dev->resource[VMD_MEMBAR2]; - upper_bits = upper_32_bits(res->end); - flags = res->flags & ~IORESOURCE_SIZEALIGN; - if (!upper_bits) - flags &= ~IORESOURCE_MEM_64; - vmd->resources[2] = (struct resource) { - .name = "VMD MEMBAR2", - .start = res->start + membar2_offset, - .end = res->end, - .flags = flags, - .parent = res, - }; + vmd_configure_membar1_membar2(vmd, membar2_offset); sd->vmd_dev = vmd->dev; sd->domain = vmd_find_free_domain(); @@ -892,70 +985,39 @@ static int vmd_enable_domain(struct vmd_dev *vmd, unsigned long features) vmd_set_msi_remapping(vmd, false); } - pci_add_resource(&resources, &vmd->resources[0]); - pci_add_resource_offset(&resources, &vmd->resources[1], offset[0]); - pci_add_resource_offset(&resources, &vmd->resources[2], offset[1]); + pci_add_resource(&resources, &vmd->resources[VMD_RES_CFGBAR]); + pci_add_resource_offset(&resources, &vmd->resources[VMD_RES_MEMBAR_1], + offset[0]); + pci_add_resource_offset(&resources, &vmd->resources[VMD_RES_MEMBAR_2], + offset[1]); - vmd->bus = pci_create_root_bus(&vmd->dev->dev, vmd->busn_start, - &vmd_ops, sd, &resources); - if (!vmd->bus) { + vmd->bus[VMD_ROOTBUS_0] = pci_create_root_bus( + &vmd->dev->dev, vmd->busn_start[VMD_ROOTBUS_0], &vmd_ops, sd, + &resources); + if (!vmd->bus[VMD_ROOTBUS_0]) { pci_free_resource_list(&resources); vmd_remove_irq_domain(vmd); return -ENODEV; } - vmd_copy_host_bridge_flags(pci_find_host_bridge(vmd->dev->bus), - to_pci_host_bridge(vmd->bus->bridge)); + vmd_copy_host_bridge_flags( + pci_find_host_bridge(vmd->dev->bus), + to_pci_host_bridge(vmd->bus[VMD_ROOTBUS_0]->bridge)); vmd_attach_resources(vmd); if (vmd->irq_domain) - dev_set_msi_domain(&vmd->bus->dev, vmd->irq_domain); + dev_set_msi_domain(&vmd->bus[VMD_ROOTBUS_0]->dev, + vmd->irq_domain); else - dev_set_msi_domain(&vmd->bus->dev, + dev_set_msi_domain(&vmd->bus[VMD_ROOTBUS_0]->dev, dev_get_msi_domain(&vmd->dev->dev)); - WARN(sysfs_create_link(&vmd->dev->dev.kobj, &vmd->bus->dev.kobj, - "domain"), "Can't create symlink to domain\n"); - - vmd_acpi_begin(); + WARN(sysfs_create_link(&vmd->dev->dev.kobj, + &vmd->bus[VMD_ROOTBUS_0]->dev.kobj, "domain"), + "Can't create symlink to domain\n"); - pci_scan_child_bus(vmd->bus); - vmd_domain_reset(vmd); + vmd_bus_enumeration(vmd->bus[VMD_ROOTBUS_0], features); - /* When Intel VMD is enabled, the OS does not discover the Root Ports - * owned by Intel VMD within the MMCFG space. pci_reset_bus() applies - * a reset to the parent of the PCI device supplied as argument. This - * is why we pass a child device, so the reset can be triggered at - * the Intel bridge level and propagated to all the children in the - * hierarchy. - */ - list_for_each_entry(child, &vmd->bus->children, node) { - if (!list_empty(&child->devices)) { - dev = list_first_entry(&child->devices, - struct pci_dev, bus_list); - ret = pci_reset_bus(dev); - if (ret) - pci_warn(dev, "can't reset device: %d\n", ret); - - break; - } - } - - pci_assign_unassigned_bus_resources(vmd->bus); - - pci_walk_bus(vmd->bus, vmd_pm_enable_quirk, &features); - - /* - * VMD root buses are virtual and don't return true on pci_is_pcie() - * and will fail pcie_bus_configure_settings() early. It can instead be - * run on each of the real root ports. - */ - list_for_each_entry(child, &vmd->bus->children, node) - pcie_bus_configure_settings(child); - - pci_bus_add_devices(vmd->bus); - - vmd_acpi_end(); return 0; } @@ -1031,9 +1093,9 @@ static void vmd_remove(struct pci_dev *dev) { struct vmd_dev *vmd = pci_get_drvdata(dev); - pci_stop_root_bus(vmd->bus); + pci_stop_root_bus(vmd->bus[VMD_ROOTBUS_0]); sysfs_remove_link(&vmd->dev->dev.kobj, "domain"); - pci_remove_root_bus(vmd->bus); + pci_remove_root_bus(vmd->bus[VMD_ROOTBUS_0]); vmd_cleanup_srcu(vmd); vmd_detach_resources(vmd); vmd_remove_irq_domain(vmd); From 6a45763d7dac611ae8817fb3e61670395267aefa Mon Sep 17 00:00:00 2001 From: Szymon Durawa Date: Tue, 22 Oct 2024 17:24:57 +0200 Subject: [PATCH 2/3] PCI: vmd: Add VMD PCH rootbus support Starting from Intel Arrow Lake VMD enhacement introduces separate rotbus for PCH. It means that all 3 MMIO BARs exposed by VMD are shared now between CPU IOC and PCH. This patch adds PCH bus enumeration and MMIO management for devices with VMD enhancement support. Suggested-by: Nirmal Patel Reviewed-by: Mariusz Tkaczyk Signed-off-by: Szymon Durawa --- drivers/pci/controller/vmd.c | 171 +++++++++++++++++++++++++++++++++-- 1 file changed, 162 insertions(+), 9 deletions(-) diff --git a/drivers/pci/controller/vmd.c b/drivers/pci/controller/vmd.c index 878e14ecad7c23..62c5ab9df6433a 100755 --- a/drivers/pci/controller/vmd.c +++ b/drivers/pci/controller/vmd.c @@ -31,6 +31,15 @@ #define PCI_REG_VMLOCK 0x70 #define MB2_SHADOW_EN(vmlock) (vmlock & 0x2) +#define VMD_PRIMARY_PCH_BUS 0x80 +#define VMD_REG_BUSRANGE0 0xC8 +#define VMD_REG_BUSRANGE1 0xCC +#define VMD_MEMBAR1_OFFSET 0xD0 +#define VMD_MEMBAR2_OFFSET1 0xD8 +#define VMD_MEMBAR2_OFFSET2 0xDC +#define VMD_ROOTBUS_RANGE_END(busr) ((busr >> 8) & 0xff) +#define VMD_ROOTBUS_RANGE_START(busr) (busr & 0x00ff) + #define MB2_SHADOW_OFFSET 0x2000 #define MB2_SHADOW_SIZE 16 @@ -38,11 +47,15 @@ enum vmd_resource { VMD_RES_CFGBAR = 0, VMD_RES_MEMBAR_1, VMD_RES_MEMBAR_2, + VMD_RES_PCH_CFGBAR, + VMD_RES_PCH_MEMBAR_1, + VMD_RES_PCH_MEMBAR_2, VMD_RES_COUNT }; enum vmd_rootbus { VMD_ROOTBUS_0 = 0, + VMD_ROOTBUS_1, VMD_ROOTBUS_COUNT }; @@ -86,6 +99,12 @@ enum vmd_features { * proper power management of the SoC. */ VMD_FEAT_BIOS_PM_QUIRK = (1 << 5), + + /* + * Starting from Intel Arrow Lake, VMD devices have their VMD rootports + * connected to CPU IOC and PCH rootbuses. + */ + VMD_FEAT_HAS_PCH_ROOTBUS = (1 << 6) }; #define VMD_BIOS_PM_QUIRK_LTR 0x1003 /* 3145728 ns */ @@ -93,7 +112,8 @@ enum vmd_features { #define VMD_FEATS_CLIENT (VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP | \ VMD_FEAT_HAS_BUS_RESTRICTIONS | \ VMD_FEAT_OFFSET_FIRST_VECTOR | \ - VMD_FEAT_BIOS_PM_QUIRK) + VMD_FEAT_BIOS_PM_QUIRK | \ + VMD_FEAT_HAS_PCH_ROOTBUS) static DEFINE_IDA(vmd_instance_ida); @@ -376,6 +396,11 @@ static void vmd_remove_irq_domain(struct vmd_dev *vmd) } } +static inline u8 vmd_has_pch_rootbus(struct vmd_dev *vmd) +{ + return vmd->busn_start[VMD_ROOTBUS_1] != 0; +} + static void __iomem *vmd_cfg_addr(struct vmd_dev *vmd, struct pci_bus *bus, unsigned int devfn, int reg, int len) { @@ -521,6 +546,9 @@ static void vmd_domain_reset(struct vmd_dev *vmd) u8 dev, functions, fn, hdr_type; char __iomem *base; + if (vmd_has_pch_rootbus(vmd)) + max_buses += resource_size(&vmd->resources[VMD_RES_PCH_CFGBAR]) + 2; + for (bus = 0; bus < max_buses; bus++) { for (dev = 0; dev < 32; dev++) { base = vmd->cfgbar + PCIE_ECAM_OFFSET(bus, @@ -645,7 +673,7 @@ static int vmd_get_phys_offsets(struct vmd_dev *vmd, bool native_hint, return 0; } -static int vmd_get_bus_number_start(struct vmd_dev *vmd) +static int vmd_get_bus_number_start(struct vmd_dev *vmd, unsigned long features) { struct pci_dev *dev = vmd->dev; u16 reg; @@ -664,6 +692,18 @@ static int vmd_get_bus_number_start(struct vmd_dev *vmd) case 2: vmd->busn_start[VMD_ROOTBUS_0] = 224; break; + case 3: + if (!(features & VMD_FEAT_HAS_PCH_ROOTBUS)) { + pci_err(dev, "VMD Bus Restriction detected type %d, but PCH Rootbus is not supported, aborting.\n", + BUS_RESTRICT_CFG(reg)); + return -ENODEV; + } + + /* IOC start bus */ + vmd->busn_start[VMD_ROOTBUS_0] = 224; + /* PCH start bus */ + vmd->busn_start[VMD_ROOTBUS_1] = 225; + break; default: pci_err(dev, "Unknown Bus Offset Setting (%d)\n", BUS_RESTRICT_CFG(reg)); @@ -781,6 +821,8 @@ static int vmd_pm_enable_quirk(struct pci_dev *pdev, void *userdata) static void vmd_configure_cfgbar(struct vmd_dev *vmd) { + u16 ioc_bus_range = 0; + u16 pch_bus_range = 0; struct resource *res = &vmd->dev->resource[VMD_CFGBAR]; vmd->resources[VMD_RES_CFGBAR] = (struct resource){ @@ -790,6 +832,29 @@ static void vmd_configure_cfgbar(struct vmd_dev *vmd) (resource_size(res) >> 20) - 1, .flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED, }; + + if (vmd_has_pch_rootbus(vmd)) { + pci_read_config_word(vmd->dev, VMD_REG_BUSRANGE0, &ioc_bus_range); + pci_read_config_word(vmd->dev, VMD_REG_BUSRANGE1, &pch_bus_range); + + /* + * Resize CPU IOC CFGBAR range to make space for PCH owned + * devices by adjusting range end with value stored in + * PCI_REG_BUSRANGE0 register. + */ + vmd->resources[VMD_RES_CFGBAR].start = + VMD_ROOTBUS_RANGE_START(ioc_bus_range); + vmd->resources[VMD_RES_CFGBAR].end = + VMD_ROOTBUS_RANGE_END(ioc_bus_range); + + vmd->resources[VMD_RES_PCH_CFGBAR] = (struct resource){ + .name = "VMD CFGBAR PCH", + .start = VMD_ROOTBUS_RANGE_START(pch_bus_range), + .end = VMD_ROOTBUS_RANGE_END(pch_bus_range), + .flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED, + .parent = &vmd->resources[VMD_RES_CFGBAR], + }; + } } /** @@ -824,7 +889,8 @@ static void vmd_configure_membar(struct vmd_dev *vmd, if (!upper_bits) flags &= ~IORESOURCE_MEM_64; - snprintf(name, sizeof(name), "VMD MEMBAR%d", membar_number/2); + snprintf(name, sizeof(name), "VMD MEMBAR%d %s", membar_number / 2, + resource_number > VMD_RES_MEMBAR_2 ? "PCH" : ""); res_parent = parent; if (!res_parent) @@ -842,9 +908,42 @@ static void vmd_configure_membar(struct vmd_dev *vmd, static void vmd_configure_membar1_membar2(struct vmd_dev *vmd, resource_size_t membar2_offset) { - vmd_configure_membar(vmd, VMD_RES_MEMBAR_1, VMD_MEMBAR1, 0, 0, NULL); - vmd_configure_membar(vmd, VMD_RES_MEMBAR_2, VMD_MEMBAR2, - membar2_offset, 0, NULL); + if (vmd_has_pch_rootbus(vmd)) { + u32 pch_mbar1_offset = 0; + u64 pch_mbar2_offset = 0; + u32 reg; + + pci_read_config_dword(vmd->dev, VMD_MEMBAR1_OFFSET, + &pch_mbar1_offset); + + pci_read_config_dword(vmd->dev, VMD_MEMBAR2_OFFSET1, ®); + pch_mbar2_offset = reg; + + pci_read_config_dword(vmd->dev, VMD_MEMBAR2_OFFSET2, ®); + pch_mbar2_offset |= (u64)reg << 32; + + /* + * Resize CPU IOC MEMBAR1 and MEMBAR2 ranges to make space + * for PCH owned devices by adjusting range end with values + * stored in PCI_MEMBAR1_OFFSET and PCI_MEMBAR2_OFFSET registers + */ + vmd_configure_membar(vmd, VMD_RES_MEMBAR_1, VMD_MEMBAR1, 0, + pch_mbar1_offset, NULL); + vmd_configure_membar(vmd, VMD_RES_MEMBAR_2, VMD_MEMBAR2, + membar2_offset, + pch_mbar2_offset - membar2_offset, NULL); + + vmd_configure_membar(vmd, VMD_RES_PCH_MEMBAR_1, VMD_MEMBAR1, + pch_mbar1_offset, 0, + &vmd->resources[VMD_RES_MEMBAR_1]); + vmd_configure_membar(vmd, VMD_RES_PCH_MEMBAR_2, VMD_MEMBAR2, + membar2_offset + pch_mbar2_offset, 0, + &vmd->resources[VMD_RES_MEMBAR_2]); + } else { + vmd_configure_membar(vmd, VMD_RES_MEMBAR_1, VMD_MEMBAR1, 0, 0, NULL); + vmd_configure_membar(vmd, VMD_RES_MEMBAR_2, VMD_MEMBAR2, + membar2_offset, 0, NULL); + } } static void vmd_bus_enumeration(struct pci_bus *bus, unsigned long features) @@ -856,7 +955,9 @@ static void vmd_bus_enumeration(struct pci_bus *bus, unsigned long features) vmd_acpi_begin(); pci_scan_child_bus(bus); - vmd_domain_reset(vmd_from_bus(bus)); + + if (bus->primary == 0) + vmd_domain_reset(vmd_from_bus(bus)); /* * When Intel VMD is enabled, the OS does not discover the Root Ports @@ -895,6 +996,44 @@ static void vmd_bus_enumeration(struct pci_bus *bus, unsigned long features) vmd_acpi_end(); } +static int vmd_create_pch_bus(struct vmd_dev *vmd, struct pci_sysdata *sd, + resource_size_t *offset) +{ + LIST_HEAD(resources_pch); + + pci_add_resource(&resources_pch, &vmd->resources[VMD_RES_PCH_CFGBAR]); + pci_add_resource_offset(&resources_pch, + &vmd->resources[VMD_RES_PCH_MEMBAR_1], offset[0]); + pci_add_resource_offset(&resources_pch, + &vmd->resources[VMD_RES_PCH_MEMBAR_2], offset[1]); + + vmd->bus[VMD_ROOTBUS_1] = pci_create_root_bus( + &vmd->dev->dev, vmd->busn_start[VMD_ROOTBUS_1], &vmd_ops, sd, + &resources_pch); + + if (!vmd->bus[VMD_ROOTBUS_1]) { + pci_free_resource_list(&resources_pch); + pci_stop_root_bus(vmd->bus[VMD_ROOTBUS_1]); + pci_remove_root_bus(vmd->bus[VMD_ROOTBUS_1]); + return -ENODEV; + } + + vmd->bus[VMD_ROOTBUS_1]->primary = VMD_PRIMARY_PCH_BUS; + + vmd_copy_host_bridge_flags( + pci_find_host_bridge(vmd->dev->bus), + to_pci_host_bridge(vmd->bus[VMD_ROOTBUS_1]->bridge)); + + if (vmd->irq_domain) + dev_set_msi_domain(&vmd->bus[VMD_ROOTBUS_1]->dev, + vmd->irq_domain); + else + dev_set_msi_domain(&vmd->bus[VMD_ROOTBUS_1]->dev, + dev_get_msi_domain(&vmd->dev->dev)); + + return 0; +} + static int vmd_enable_domain(struct vmd_dev *vmd, unsigned long features) { struct pci_sysdata *sd = &vmd->sysdata; @@ -925,7 +1064,7 @@ static int vmd_enable_domain(struct vmd_dev *vmd, unsigned long features) * limits the bus range to between 0-127, 128-255, or 224-255 */ if (features & VMD_FEAT_HAS_BUS_RESTRICTIONS) { - ret = vmd_get_bus_number_start(vmd); + ret = vmd_get_bus_number_start(vmd, features); if (ret) return ret; } @@ -1018,6 +1157,16 @@ static int vmd_enable_domain(struct vmd_dev *vmd, unsigned long features) vmd_bus_enumeration(vmd->bus[VMD_ROOTBUS_0], features); + if (vmd_has_pch_rootbus(vmd)) { + ret = vmd_create_pch_bus(vmd, sd, offset); + if (ret) { + pci_err(vmd->dev, "Can't create PCH bus: %d\n", ret); + return ret; + } + + vmd_bus_enumeration(vmd->bus[VMD_ROOTBUS_1], features); + } + return 0; } @@ -1096,6 +1245,10 @@ static void vmd_remove(struct pci_dev *dev) pci_stop_root_bus(vmd->bus[VMD_ROOTBUS_0]); sysfs_remove_link(&vmd->dev->dev.kobj, "domain"); pci_remove_root_bus(vmd->bus[VMD_ROOTBUS_0]); + if (vmd_has_pch_rootbus(vmd)) { + pci_stop_root_bus(vmd->bus[VMD_ROOTBUS_1]); + pci_remove_root_bus(vmd->bus[VMD_ROOTBUS_1]); + } vmd_cleanup_srcu(vmd); vmd_detach_resources(vmd); vmd_remove_irq_domain(vmd); @@ -1181,4 +1334,4 @@ module_pci_driver(vmd_drv); MODULE_AUTHOR("Intel Corporation"); MODULE_DESCRIPTION("Volume Management Device driver"); MODULE_LICENSE("GPL v2"); -MODULE_VERSION("0.6"); +MODULE_VERSION("0.7"); From c4ede0896fd55dd6dcc4a89775a54ab2476b1ff8 Mon Sep 17 00:00:00 2001 From: Szymon Durawa Date: Tue, 22 Oct 2024 11:09:46 +0200 Subject: [PATCH 3/3] PCI: vmd: Add WA for VMD PCH rootbus support VMD PCH rootbus primary number is 0x80 and pci_scan_bridge_extend() cannot assign it as "hard-wired to 0" and marks setup as broken. To avoid this, PCH bus number has to be the same as PCH primary number. Suggested-by: Nirmal Patel Reviewed-by: Mariusz Tkaczyk Signed-off-by: Szymon Durawa --- drivers/pci/controller/vmd.c | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/vmd.c b/drivers/pci/controller/vmd.c index 62c5ab9df6433a..f6cf34c8778cb3 100755 --- a/drivers/pci/controller/vmd.c +++ b/drivers/pci/controller/vmd.c @@ -404,8 +404,21 @@ static inline u8 vmd_has_pch_rootbus(struct vmd_dev *vmd) static void __iomem *vmd_cfg_addr(struct vmd_dev *vmd, struct pci_bus *bus, unsigned int devfn, int reg, int len) { - unsigned int busnr_ecam = bus->number - vmd->busn_start[VMD_ROOTBUS_0]; - u32 offset = PCIE_ECAM_OFFSET(busnr_ecam, devfn, reg); + unsigned char bus_number; + unsigned int busnr_ecam; + u32 offset; + + /* + * VMD WA: for PCH rootbus, bus number is set to PCI_VMD_PRIMARY_PCH_BUS + * (see comment in vmd_create_pch_bus()) but original value is 0xE1 + * which is stored in vmd->busn_start[VMD_ROOTBUS_1]. + */ + bus_number = (bus->number == VMD_PRIMARY_PCH_BUS) ? + vmd->busn_start[VMD_ROOTBUS_1] : + bus->number; + + busnr_ecam = bus_number - vmd->busn_start[VMD_ROOTBUS_0]; + offset = PCIE_ECAM_OFFSET(busnr_ecam, devfn, reg); if (offset + len >= resource_size(&vmd->dev->resource[VMD_CFGBAR])) return NULL; @@ -1018,6 +1031,14 @@ static int vmd_create_pch_bus(struct vmd_dev *vmd, struct pci_sysdata *sd, return -ENODEV; } + /* + * This is a workaround for pci_scan_bridge_extend() code. + * It assigns setup as broken when primary != bus->number and + * for PCH rootbus primary is not "hard-wired to 0". + * To avoid this, vmd->bus[VMD_ROOTBUS1]->number and + * vmd->bus[VMD_ROOTBUS1]->primary are updated to the same value. + */ + vmd->bus[VMD_ROOTBUS_1]->number = VMD_PRIMARY_PCH_BUS; vmd->bus[VMD_ROOTBUS_1]->primary = VMD_PRIMARY_PCH_BUS; vmd_copy_host_bridge_flags(