sheiny.github.io/index.html at master · sheiny/sheiny.github.io · GitHub

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<!DOCTYPE html>
<html lang="en">
  <head>
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    <title>Sheiny's Resume</title>
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    <header>
      <img src="static/img/profile.jpg" alt="Profile Picture">
      <div class="header-info">
        <h1>Sheiny Fabre Almeida, Ph.D.</h1>
        <div class="contact">
          Location: Brazil<br>
          Email: sheiny.fabre@gmail.com<br>
          Linkedin: <a href="https://www.linkedin.com/in/sheiny-fabre-almeida-b974a8171/">linkedin.com/in/sheiny-fabre-almeida-b974a8171</a> <br>
          Github: <a href="https://github.com/sheiny">github.com/sheiny</a>
        </div>
      </div>
    </header>

    <main>
      <!-- LEFT COLUMN -->
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        <section>
          <h2>SUMMARY</h2>
          <p>
          Innovative <strong>Lead Software Engineer</strong> with a <strong>Ph.D. in Computer Science</strong> and 3+ years of experience developing scalable solutions in the EDA (Electronic Design Automation) industry.
          Expert in software development, electronic design automation, and high-performance computing, with a strong record of bridging research and production.
          Enthusiastic about continuously learning new technologies and applying them to drive innovation and deliver results.
          </p>
        </section>

        <section>
          <h2>PROFESSIONAL EXPERIENCE</h2>
          <div class="job">
            <div class="job-title">Lead Software Engineer — Cadence Design Systems Brazil</div>
            <div class="date">Oct 2024 – <strong>Now</strong></div>
            <p>
            Lead software engineer in CCOpt (Concurrent Clock Optimization) team, Brazil — Belo Horizonte.
            </p>
          </div>

          <div class="job">
            <div class="job-title">Software Engineer Intern — Cadence Design Systems</div>
            <div class="date"><strong>(2 years)</strong> Apr 2021 – Dec 2021 &amp; Jan 2023 – Jul 2024</div>
            <p>
            Worked as research and development software engineer intern in CCOpt (Concurrent Clock Optimization) team, Austin TX (remote).
            Delivered key QoR (Quality of Results) for relevant customers.
            My work contributions resulted in to two U.S. patents under Cadence's ownership.
            </p>
          </div>

        <section>
          <h2>EDUCATION</h2>
          <p><strong>Ph.D., Computer Science — Federal University of Santa Catarina (UFSC), Brazil</strong><br>
          <em>(Feb 2025) Thesis:</em> <a href="https://repositorio.ufsc.br/bitstream/handle/123456789/264897/PGCC1295-T.pdf">A Hyper-Image-Based Initial DRV Predictor Combining Placement and Global Routing Data</a><br>
          </p>
          <p><strong>(2017) B.Sc. and (2019) M.Sc., Computer Science — UFSC</strong></p>
        </section>

        <section class="skills">
          <h2>TECHNICAL SKILLS &amp; COMPETENCIES</h2>
          <ul>
            <li>Software Architecture</li>
            <li>Machine Learning &amp; AI</li>
            <li>Multithreading</li>
            <li>Object Oriented Design</li>
            <li>Test Driven Development</li>
            <li>C++, Python, TCL, Scripting</li>
            <li>Optimization Methods</li>
            <li>Debug (GDB)</li>
            <li>TensorFlow</li>
            <li>Git, Perforce</li>
          </ul>
        </section>

        <section>
          <h2>REFERENCES</h2>
          <p>Available upon request</p>
        </section>
      </div>

      <!-- RIGHT COLUMN -->
      <div class="right">

        <section>
          <h2>MAIN PUBLICATIONS</h2>
          <ul>
            <li><a href="https://doi.org/10.1016/j.vlsi.2024.102309">A Hyper-Image-Based Initial DRV Predictor Combining Placement and Global Routing Data</a> <em>Integration</em>, 2025.</li>
            <li><a href="https://ieeexplore.ieee.org/document/9970846">E-RVP: An Initial Design Rule Violation Predictor Using Placement Information</a> <em>ICECS</em>, 2022.</li>
            <li><a href="https://ieeexplore.ieee.org/document/9428588">Algorithm Selection Framework for Legalization Using Deep Convolutional Neural Networks and Transfer Learning</a> <em>Transactions</em>, 2021.</li>
            <li><a href="https://woset-workshop.github.io/WOSET2018.html">Ophidian: an Open-Source Library for Physical Design Research and Teaching</a> <em>WOSET</em>, 2018.</li>
            <li><a href="https://ieeexplore.ieee.org/document/8533264">Enhancing Multi-Threaded Legalization Through k-d Tree Circuit Partitioning</a> <em>SBCCI</em>, 2018.</li>
          </ul>
        </section>

        <section>
          <h2>AWARDS & HONORS</h2>
          <ul>
            <li>Doctoral Exchange Scholarship at UCalgary Canada - CAPES PrInt (Brazil's Government), 2020.</li>
            <li>A. Richard Newton Young Student Fellow, DAC, 2019 and 2020 (Virtual).</li>
            <li>3rd Place Award on Multi-Deck Standard Cell Legalization, ICCAD, 2017</li>
            <li>A. Richard Newton Young Student Fellow, DAC, 2017</li>
            <li>Member of Brazilian Programming Contest for Design Automation of Integrated Circuits</li>
          </ul>
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