From 7cb75a63e9241465b983dca9faf9cc948f8c95b7 Mon Sep 17 00:00:00 2001
From: Jeremy Soller <jackpot51@gmail.com>
Date: Thu, 5 Mar 2026 13:32:22 -0700
Subject: [PATCH 01/13] mainboard/system76/ptl: init with lemp14

---
 src/mainboard/system76/ptl/Kconfig            |   89 ++
 src/mainboard/system76/ptl/Kconfig.name       |    4 +
 src/mainboard/system76/ptl/Makefile.mk        |   17 +
 src/mainboard/system76/ptl/acpi/backlight.asl |   31 +
 src/mainboard/system76/ptl/acpi/mainboard.asl |   12 +
 src/mainboard/system76/ptl/acpi/sleep.asl     |    9 +
 src/mainboard/system76/ptl/board_info.txt     |    6 +
 src/mainboard/system76/ptl/bootblock.c        |    9 +
 src/mainboard/system76/ptl/cmos.default       |    5 +
 src/mainboard/system76/ptl/cmos.layout        |   43 +
 src/mainboard/system76/ptl/devicetree.cb      |   65 +
 src/mainboard/system76/ptl/dsdt.asl           |   36 +
 .../system76/ptl/include/mainboard/gpio.h     |    9 +
 src/mainboard/system76/ptl/ramstage.c         |   13 +
 src/mainboard/system76/ptl/spd/Makefile.mk    |    6 +
 .../system76/ptl/variants/lemp14/board.fmd    |   12 +
 .../ptl/variants/lemp14/board_info.txt        |    2 +
 .../system76/ptl/variants/lemp14/data.vbt     |  Bin 0 -> 7680 bytes
 .../system76/ptl/variants/lemp14/gpio.c       |  203 ++++
 .../system76/ptl/variants/lemp14/gpio_early.c |   17 +
 .../system76/ptl/variants/lemp14/hda_verb.c   |   51 +
 .../ptl/variants/lemp14/memory/Makefile.mk    |    7 +
 .../lemp14/memory/dram_id.generated.txt       |    7 +
 .../variants/lemp14/memory/mem_parts_used.txt |   12 +
 .../ptl/variants/lemp14/overridetree.cb       |  112 ++
 .../system76/ptl/variants/lemp14/ramstage.c   |   18 +
 .../system76/ptl/variants/lemp14/romstage.c   |   78 ++
 .../system76/ptl/variants/lemp14/tas5825m.c   | 1049 +++++++++++++++++
 28 files changed, 1922 insertions(+)
 create mode 100644 src/mainboard/system76/ptl/Kconfig
 create mode 100644 src/mainboard/system76/ptl/Kconfig.name
 create mode 100644 src/mainboard/system76/ptl/Makefile.mk
 create mode 100644 src/mainboard/system76/ptl/acpi/backlight.asl
 create mode 100644 src/mainboard/system76/ptl/acpi/mainboard.asl
 create mode 100644 src/mainboard/system76/ptl/acpi/sleep.asl
 create mode 100644 src/mainboard/system76/ptl/board_info.txt
 create mode 100644 src/mainboard/system76/ptl/bootblock.c
 create mode 100644 src/mainboard/system76/ptl/cmos.default
 create mode 100644 src/mainboard/system76/ptl/cmos.layout
 create mode 100644 src/mainboard/system76/ptl/devicetree.cb
 create mode 100644 src/mainboard/system76/ptl/dsdt.asl
 create mode 100644 src/mainboard/system76/ptl/include/mainboard/gpio.h
 create mode 100644 src/mainboard/system76/ptl/ramstage.c
 create mode 100644 src/mainboard/system76/ptl/spd/Makefile.mk
 create mode 100644 src/mainboard/system76/ptl/variants/lemp14/board.fmd
 create mode 100644 src/mainboard/system76/ptl/variants/lemp14/board_info.txt
 create mode 100644 src/mainboard/system76/ptl/variants/lemp14/data.vbt
 create mode 100644 src/mainboard/system76/ptl/variants/lemp14/gpio.c
 create mode 100644 src/mainboard/system76/ptl/variants/lemp14/gpio_early.c
 create mode 100644 src/mainboard/system76/ptl/variants/lemp14/hda_verb.c
 create mode 100644 src/mainboard/system76/ptl/variants/lemp14/memory/Makefile.mk
 create mode 100644 src/mainboard/system76/ptl/variants/lemp14/memory/dram_id.generated.txt
 create mode 100644 src/mainboard/system76/ptl/variants/lemp14/memory/mem_parts_used.txt
 create mode 100644 src/mainboard/system76/ptl/variants/lemp14/overridetree.cb
 create mode 100644 src/mainboard/system76/ptl/variants/lemp14/ramstage.c
 create mode 100644 src/mainboard/system76/ptl/variants/lemp14/romstage.c
 create mode 100644 src/mainboard/system76/ptl/variants/lemp14/tas5825m.c

diff --git a/src/mainboard/system76/ptl/Kconfig b/src/mainboard/system76/ptl/Kconfig
new file mode 100644
index 00000000000..da29d0a0030
--- /dev/null
+++ b/src/mainboard/system76/ptl/Kconfig
@@ -0,0 +1,89 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_SYSTEM76_PTL_COMMON
+	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
+	select BOARD_ROMSIZE_KB_32768
+	select DRIVERS_GENERIC_BAYHUB_LV2
+	select DRIVERS_GENERIC_CBFS_SERIAL
+	select DRIVERS_GENERIC_CBFS_UUID
+	select DRIVERS_I2C_HID
+	select EC_SYSTEM76_EC
+	select EC_SYSTEM76_EC_LOCKDOWN
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_CMOS_DEFAULT
+	select HAVE_OPTION_TABLE
+	select INTEL_GMA_HAVE_VBT
+	select INTEL_LPSS_UART_FOR_CONSOLE
+	select MAINBOARD_HAS_TPM2
+	select MEMORY_MAPPED_TPM
+	select NO_UART_ON_SUPERIO
+	select PCIEXP_SUPPORT_RESIZABLE_BARS
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SOC_INTEL_CRASHLOG
+	select SOC_INTEL_PANTHERLAKE_U_H
+	select SPD_READ_BY_WORD
+	select SYSTEM_TYPE_LAPTOP
+
+config BOARD_SYSTEM76_LEMP14
+	select BOARD_SYSTEM76_PTL_COMMON
+	select DRIVERS_I2C_TAS5825M
+	select HAVE_SPD_IN_CBFS
+	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
+
+if BOARD_SYSTEM76_PTL_COMMON
+
+config MAINBOARD_DIR
+	default "system76/ptl"
+
+config VARIANT_DIR
+	default "lemp14" if BOARD_SYSTEM76_LEMP14
+
+config OVERRIDE_DEVICETREE
+	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
+config MAINBOARD_PART_NUMBER
+	default "lemp14" if BOARD_SYSTEM76_LEMP14
+
+config MAINBOARD_SMBIOS_PRODUCT_NAME
+	default "Lemur Pro" if BOARD_SYSTEM76_LEMP14
+
+config MAINBOARD_VERSION
+	default "lemp14" if BOARD_SYSTEM76_LEMP14
+
+config CMOS_DEFAULT_FILE
+	default "src/mainboard/\$(MAINBOARDDIR)/cmos.default"
+
+config CONSOLE_POST
+	default y
+
+config D3COLD_SUPPORT
+	default n
+
+config DIMM_SPD_SIZE
+	default 512
+
+config FMDFILE
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd"
+
+config ONBOARD_VGA_IS_PRIMARY
+	default y
+
+config PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS
+	default 36
+
+config POST_DEVICE
+	default n
+
+config TPM_MEASURED_BOOT
+	default y
+
+config UART_FOR_CONSOLE
+	default 0
+
+# PM Timer Disabled, saves power
+config USE_PM_ACPI_TIMER
+	default n
+
+endif
diff --git a/src/mainboard/system76/ptl/Kconfig.name b/src/mainboard/system76/ptl/Kconfig.name
new file mode 100644
index 00000000000..eb83581a0d0
--- /dev/null
+++ b/src/mainboard/system76/ptl/Kconfig.name
@@ -0,0 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_SYSTEM76_LEMP14
+	bool "lemp14"
diff --git a/src/mainboard/system76/ptl/Makefile.mk b/src/mainboard/system76/ptl/Makefile.mk
new file mode 100644
index 00000000000..08bd6b0627b
--- /dev/null
+++ b/src/mainboard/system76/ptl/Makefile.mk
@@ -0,0 +1,17 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+
+bootblock-y += bootblock.c
+bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
+
+romstage-y += variants/$(VARIANT_DIR)/romstage.c
+
+ramstage-y += ramstage.c
+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
+ramstage-y += variants/$(VARIANT_DIR)/gpio.c
+ramstage-y += variants/$(VARIANT_DIR)/ramstage.c
+ramstage-$(CONFIG_DRIVERS_I2C_TAS5825M) += variants/$(VARIANT_DIR)/tas5825m.c
+
+subdirs-y += variants/$(VARIANT_DIR)/memory
+subdirs-$(CONFIG_HAVE_SPD_IN_CBFS) += spd
diff --git a/src/mainboard/system76/ptl/acpi/backlight.asl b/src/mainboard/system76/ptl/acpi/backlight.asl
new file mode 100644
index 00000000000..053ce57b5d4
--- /dev/null
+++ b/src/mainboard/system76/ptl/acpi/backlight.asl
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/acpi/gma.asl>
+
+Scope (GFX0)
+{
+	Name (BRIG, Package (22) {
+		100, /* default AC */
+		100, /* default Battery */
+		5,
+		10,
+		15,
+		20,
+		25,
+		30,
+		35,
+		40,
+		45,
+		50,
+		55,
+		60,
+		65,
+		70,
+		75,
+		80,
+		85,
+		90,
+		95,
+		100
+	})
+}
diff --git a/src/mainboard/system76/ptl/acpi/mainboard.asl b/src/mainboard/system76/ptl/acpi/mainboard.asl
new file mode 100644
index 00000000000..c982a9ee4cb
--- /dev/null
+++ b/src/mainboard/system76/ptl/acpi/mainboard.asl
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define EC_GPE_SCI 0x6E
+#define EC_GPE_SWI 0x6B
+#include <ec/system76/ec/acpi/ec.asl>
+
+Scope (\_SB) {
+	#include "sleep.asl"
+	Scope (PCI0) {
+		#include "backlight.asl"
+	}
+}
diff --git a/src/mainboard/system76/ptl/acpi/sleep.asl b/src/mainboard/system76/ptl/acpi/sleep.asl
new file mode 100644
index 00000000000..8a2a22c55b6
--- /dev/null
+++ b/src/mainboard/system76/ptl/acpi/sleep.asl
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+External(\TBTS, MethodObj)
+
+Method(MPTS, 1, Serialized) {
+	If (CondRefOf(\TBTS)) {
+		\TBTS()
+	}
+}
diff --git a/src/mainboard/system76/ptl/board_info.txt b/src/mainboard/system76/ptl/board_info.txt
new file mode 100644
index 00000000000..e67d8800620
--- /dev/null
+++ b/src/mainboard/system76/ptl/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: System76
+Category: laptop
+ROM package: WSON-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/system76/ptl/bootblock.c b/src/mainboard/system76/ptl/bootblock.c
new file mode 100644
index 00000000000..8d06adc9d7f
--- /dev/null
+++ b/src/mainboard/system76/ptl/bootblock.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <mainboard/gpio.h>
+
+void bootblock_mainboard_early_init(void)
+{
+	mainboard_configure_early_gpios();
+}
diff --git a/src/mainboard/system76/ptl/cmos.default b/src/mainboard/system76/ptl/cmos.default
new file mode 100644
index 00000000000..0cc5970e49b
--- /dev/null
+++ b/src/mainboard/system76/ptl/cmos.default
@@ -0,0 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+boot_option=Fallback
+debug_level=Debug
+me_state=Disable
diff --git a/src/mainboard/system76/ptl/cmos.layout b/src/mainboard/system76/ptl/cmos.layout
new file mode 100644
index 00000000000..b3df3808ccb
--- /dev/null
+++ b/src/mainboard/system76/ptl/cmos.layout
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+entries
+
+0	384	r	0	reserved_memory
+
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384	1	e	4	boot_option
+388	4	h	0	reboot_counter
+
+# RTC_CLK_ALTCENTURY
+400	8	r	0	century
+
+412	4	e	6	debug_level
+416	1	e	2	me_state
+417	3	h	0	me_state_counter
+
+# CMOS_VSTART_ramtop
+800	80	r	0	ramtop
+
+984	16	h	0	check_sum
+
+enumerations
+
+2	0	Enable
+2	1	Disable
+
+4	0	Fallback
+4	1	Normal
+
+6	0	Emergency
+6	1	Alert
+6	2	Critical
+6	3	Error
+6	4	Warning
+6	5	Notice
+6	6	Info
+6	7	Debug
+6	8	Spew
+
+checksums
+
+checksum 408 799 984
diff --git a/src/mainboard/system76/ptl/devicetree.cb b/src/mainboard/system76/ptl/devicetree.cb
new file mode 100644
index 00000000000..2c5189ca923
--- /dev/null
+++ b/src/mainboard/system76/ptl/devicetree.cb
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/pantherlake
+	register "common_soc_config" = "{
+		// Touchpad I2C bus
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 80,
+			.fall_time_ns = 110,
+		},
+	}"
+
+	# Enable Enhanced Intel SpeedStep
+	register "eist_enable" = "true"
+
+	# Thermal
+	register "tcc_offset" = "8"
+
+	device cpu_cluster 0 on end
+
+	device domain 0 on
+		device ref system_agent on end
+		device ref igpu on
+			# DDIA is eDP, TCP3 is HDMI
+			register "ddi_port_A_config" = "1"
+			register "ddi_ports_config" = "{
+				[DDI_PORT_A] = DDI_ENABLE_HPD,
+				[DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+			}"
+
+			#TODO: not in pantherlake chip: register "gfx" = "GMA_DEFAULT_PANEL(0)"
+		end
+		device ref npu on end
+		device ref pmc_shared_sram on end
+		device ref cnvi_wifi on
+			register "cnvi_wifi_core" = "true"
+			register "cnvi_bt_core" = "true"
+			register "cnvi_bt_audio_offload" = "true"
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end
+
+		device ref heci1 on end
+		device ref soc_espi on
+			register "gen1_dec" = "0x00040069" # EC PM channel
+			register "gen2_dec" = "0x00fc0e01" # AP/EC command
+			register "gen3_dec" = "0x00fc0f01" # AP/EC debug
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end
+		device ref p2sb on end
+		device ref hda on
+			register "pch_hda_audio_link_hda_enable" = "1"
+			register "pch_hda_sdi_enable[0]" = "true"
+			register "pch_hda_idisp_codec_enable" = "1"
+			register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
+			register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
+		end
+		device ref smbus on end
+		device ref fast_spi on end
+	end
+end
diff --git a/src/mainboard/system76/ptl/dsdt.asl b/src/mainboard/system76/ptl/dsdt.asl
new file mode 100644
index 00000000000..f6e4cf756bf
--- /dev/null
+++ b/src/mainboard/system76/ptl/dsdt.asl
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+//TODO: HACK FOR MISSING MISCCFG_GPIO_PM_CONFIG_BITS
+#include <soc/gpio.h>
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include <soc/intel/common/block/acpi/acpi/platform.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/pantherlake/acpi/southbridge.asl>
+		#include <soc/intel/pantherlake/acpi/tcss.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Scope (\_SB.PCI0.LPCB)
+	{
+		#include <drivers/pc80/pc/ps2_controller.asl>
+	}
+
+	#include "acpi/mainboard.asl"
+}
diff --git a/src/mainboard/system76/ptl/include/mainboard/gpio.h b/src/mainboard/system76/ptl/include/mainboard/gpio.h
new file mode 100644
index 00000000000..c6393beebb6
--- /dev/null
+++ b/src/mainboard/system76/ptl/include/mainboard/gpio.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+void mainboard_configure_early_gpios(void);
+void mainboard_configure_gpios(void);
+
+#endif
diff --git a/src/mainboard/system76/ptl/ramstage.c b/src/mainboard/system76/ptl/ramstage.c
new file mode 100644
index 00000000000..a3b12bb1f2e
--- /dev/null
+++ b/src/mainboard/system76/ptl/ramstage.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/ramstage.h>
+
+static void mainboard_init(void *chip_info)
+{
+	mainboard_configure_gpios();
+}
+
+struct chip_operations mainboard_ops = {
+	.init = mainboard_init,
+};
diff --git a/src/mainboard/system76/ptl/spd/Makefile.mk b/src/mainboard/system76/ptl/spd/Makefile.mk
new file mode 100644
index 00000000000..be4d98bd1d7
--- /dev/null
+++ b/src/mainboard/system76/ptl/spd/Makefile.mk
@@ -0,0 +1,6 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+##
+
+ifneq ($(SPD_SOURCES),)
+LIB_SPD_DEPS := $(SPD_SOURCES)
+endif
diff --git a/src/mainboard/system76/ptl/variants/lemp14/board.fmd b/src/mainboard/system76/ptl/variants/lemp14/board.fmd
new file mode 100644
index 00000000000..c466748dc44
--- /dev/null
+++ b/src/mainboard/system76/ptl/variants/lemp14/board.fmd
@@ -0,0 +1,12 @@
+FLASH 32M {
+	SI_DESC 16K
+	SI_ME 9176K
+	SI_BIOS@16M 16M {
+		RW_MRC_CACHE 64K
+		SMMSTORE(PRESERVE) 256K
+		WP_RO {
+			FMAP 4K
+			COREBOOT(CBFS)
+		}
+	}
+}
diff --git a/src/mainboard/system76/ptl/variants/lemp14/board_info.txt b/src/mainboard/system76/ptl/variants/lemp14/board_info.txt
new file mode 100644
index 00000000000..75ed180caf4
--- /dev/null
+++ b/src/mainboard/system76/ptl/variants/lemp14/board_info.txt
@@ -0,0 +1,2 @@
+Board name: lemp14
+Release year: 2026
diff --git a/src/mainboard/system76/ptl/variants/lemp14/data.vbt b/src/mainboard/system76/ptl/variants/lemp14/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..d7979238a977974bac0992745d65ca79f1c4c15b
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A3IG5A

literal 0
HcmV?d00001

diff --git a/src/mainboard/system76/ptl/variants/lemp14/gpio.c b/src/mainboard/system76/ptl/variants/lemp14/gpio.c
new file mode 100644
index 00000000000..d81813108f6
--- /dev/null
+++ b/src/mainboard/system76/ptl/variants/lemp14/gpio.c
@@ -0,0 +1,203 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config gpio_table[] = {
+	PAD_CFG_NF(GPP_A00, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_A01, 1, DEEP),
+	PAD_CFG_GPO(GPP_A02, 1, DEEP),
+	PAD_CFG_GPO(GPP_A03, 1, DEEP),
+	PAD_CFG_GPO(GPP_A04, 1, DEEP),
+	PAD_CFG_GPO(GPP_A05, 1, DEEP),
+	PAD_CFG_GPO(GPP_A06, 1, DEEP),
+	PAD_CFG_GPO(GPP_A07, 1, DEEP),
+	PAD_CFG_NF(GPP_A08, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A09, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A10, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A11, UP_20K, DEEP, NF1),
+	PAD_NC(GPP_A12, NATIVE),
+	PAD_CFG_NF(GPP_A13, NATIVE, DEEP, NF2),
+	_PAD_CFG_STRUCT(GPP_A14, 0x40001300, 0x3c00),
+	PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A16, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A17, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_B00, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPP_B01, NONE, PWROK, NF1),
+	PAD_CFG_GPO(GPP_B02, 1, DEEP),
+	PAD_CFG_GPO(GPP_B03, 1, DEEP),
+	PAD_CFG_GPO(GPP_B04, 1, DEEP),
+	PAD_CFG_GPO(GPP_B05, 1, DEEP),
+	PAD_CFG_GPO(GPP_B06, 0, PLTRST),
+	PAD_CFG_GPO(GPP_B07, 1, DEEP),
+	PAD_CFG_GPO(GPP_B08, 1, DEEP),
+	PAD_CFG_GPO(GPP_B09, 1, PLTRST),
+	PAD_CFG_GPO(GPP_B10, 1, PLTRST),
+	PAD_NC(GPP_B11, NONE),
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2),
+	PAD_NC(GPP_B15, NONE),
+	PAD_CFG_GPO(GPP_B16, 1, DEEP),
+	PAD_CFG_GPO(GPP_B17, 1, DEEP),
+	PAD_CFG_GPO(GPP_B18, 1, DEEP),
+	PAD_CFG_GPO(GPP_B19, 1, DEEP),
+	PAD_NC(GPP_B20, NONE),
+	PAD_CFG_GPO(GPP_B21, 0, PLTRST),
+	PAD_CFG_GPO(GPP_B22, 1, DEEP),
+	PAD_CFG_GPO(GPP_B23, 1, DEEP),
+	PAD_CFG_GPO(GPP_B24, 1, DEEP),
+	PAD_CFG_GPO(GPP_B25, 1, DEEP),
+	PAD_CFG_NF(GPP_C00, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_C01, UP_20K, DEEP, NF1),
+	PAD_CFG_GPO(GPP_C02, 1, DEEP),
+	PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_C05, 1, DEEP),
+	PAD_NC(GPP_C06, NONE),
+	PAD_NC(GPP_C07, NONE),
+	PAD_CFG_GPO(GPP_C08, 1, DEEP),
+	PAD_CFG_GPO(GPP_C09, 1, DEEP),
+	PAD_CFG_GPO(GPP_C10, 1, DEEP),
+	PAD_CFG_GPO(GPP_C11, 1, DEEP),
+	PAD_CFG_NF(GPP_C12, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_C13, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_C14, NONE, PLTRST, NF1),
+	PAD_CFG_GPO(GPP_C15, 1, DEEP),
+	//TODO PAD_CFG_NF(GPP_C16, NONE, TODO_0xc4000700, NF1),
+	//TODO PAD_CFG_NF(GPP_C17, NONE, TODO_0xc4000700, NF1),
+	PAD_CFG_GPO(GPP_C18, 1, DEEP),
+	PAD_CFG_GPO(GPP_C19, 1, DEEP),
+	PAD_CFG_GPO(GPP_C20, 1, DEEP),
+	PAD_CFG_GPO(GPP_C21, 1, DEEP),
+	PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2),
+	PAD_CFG_GPO(GPP_D00, 1, PLTRST),
+	PAD_CFG_GPO(GPP_D01, 1, DEEP),
+	PAD_CFG_GPO(GPP_D02, 1, DEEP),
+	PAD_CFG_GPO(GPP_D03, 1, DEEP),
+	PAD_CFG_GPO(GPP_D04, 1, DEEP),
+	PAD_CFG_GPO(GPP_D05, 1, DEEP),
+	PAD_CFG_GPO(GPP_D06, 1, DEEP),
+	PAD_CFG_GPO(GPP_D07, 1, DEEP),
+	PAD_CFG_GPO(GPP_D08, 1, DEEP),
+	PAD_CFG_GPO(GPP_D09, 1, DEEP),
+	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_D14, 1, DEEP),
+	PAD_NC(GPP_D15, NONE),
+	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_D17, 1, DEEP),
+	PAD_CFG_NF(GPP_D18, NONE, PLTRST, NF1),
+	PAD_CFG_GPO(GPP_D19, 1, PLTRST),
+	PAD_CFG_GPO(GPP_D20, 1, DEEP),
+	PAD_CFG_GPO(GPP_D21, 1, DEEP),
+	PAD_CFG_NF(GPP_D22, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D23, NATIVE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_D24, 1, DEEP),
+	PAD_CFG_GPO(GPP_D25, 1, DEEP),
+	_PAD_CFG_STRUCT(GPP_E01, 0x42880100, 0x0000),
+	PAD_NC(GPP_E02, NONE),
+	PAD_CFG_GPO(GPP_E03, 1, DEEP),
+	PAD_CFG_GPO(GPP_E04, 1, DEEP),
+	PAD_CFG_GPO(GPP_E05, 1, DEEP),
+	PAD_CFG_GPO(GPP_E06, 1, DEEP),
+	PAD_CFG_GPO(GPP_E07, 1, DEEP),
+	PAD_NC(GPP_E08, NONE),
+	PAD_NC(GPP_E09, NONE),
+	PAD_CFG_GPO(GPP_E10, 1, DEEP),
+	PAD_CFG_GPI(GPP_E11, NONE, DEEP),
+	_PAD_CFG_STRUCT(GPP_E12, 0x44002300, 0x0000),
+	_PAD_CFG_STRUCT(GPP_E13, 0x44002300, 0x0000),
+	PAD_CFG_GPI(GPP_E14, NONE, DEEP),
+	PAD_CFG_GPI(GPP_E15, NONE, DEEP),
+	PAD_CFG_GPO(GPP_E16, 1, DEEP),
+	PAD_CFG_GPI(GPP_E17, NONE, DEEP),
+	PAD_CFG_GPO(GPP_E18, 1, DEEP),
+	PAD_CFG_GPO(GPP_E19, 1, DEEP),
+	PAD_CFG_GPO(GPP_E20, 1, DEEP),
+	PAD_CFG_NF(GPP_E21, NONE, PWROK, NF1),
+	PAD_CFG_GPO(GPP_E22, 1, DEEP),
+	PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F01, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F03, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3),
+	PAD_CFG_GPO(GPP_F06, 1, DEEP),
+	PAD_CFG_GPO(GPP_F07, 1, DEEP),
+	PAD_CFG_GPO(GPP_F08, 1, DEEP),
+	PAD_CFG_GPI(GPP_F09, NONE, DEEP),
+	PAD_CFG_GPO(GPP_F10, 1, DEEP),
+	PAD_CFG_GPO(GPP_F11, 1, DEEP),
+	_PAD_CFG_STRUCT(GPP_F12, 0x44002300, 0x0000),
+	_PAD_CFG_STRUCT(GPP_F13, 0x44002300, 0x0000),
+	PAD_CFG_GPO(GPP_F14, 1, DEEP),
+	PAD_CFG_GPO(GPP_F15, 1, DEEP),
+	PAD_CFG_GPO(GPP_F16, 1, PLTRST),
+	PAD_CFG_GPO(GPP_F17, 1, DEEP),
+	_PAD_CFG_STRUCT(GPP_F18, 0x80800100, 0x0000),
+	PAD_CFG_GPO(GPP_F19, 1, DEEP),
+	PAD_CFG_GPO(GPP_F20, 1, DEEP),
+	PAD_CFG_GPO(GPP_F21, 1, DEEP),
+	PAD_CFG_GPO(GPP_F22, 1, DEEP),
+	PAD_CFG_GPO(GPP_F23, 1, DEEP),
+	PAD_CFG_NF(GPP_H00, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H01, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H02, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H03, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H04, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H05, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H06, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H09, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_H10, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_H11, DN_20K, DEEP, NF1),
+	//TODO: PAD_CFG_NF(GPP_H12, TODO_0x2400, DEEP, NF1),
+	PAD_CFG_NF(GPP_H13, DN_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_H14, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_H15, 1, DEEP),
+	PAD_CFG_GPO(GPP_H16, 1, DEEP),
+	PAD_CFG_GPO(GPP_H17, 1, DEEP),
+	PAD_NC(GPP_H18, NONE),
+	_PAD_CFG_STRUCT(GPP_H19, 0x44000601, 0x0000),
+	_PAD_CFG_STRUCT(GPP_H20, 0x44000601, 0x0000),
+	PAD_CFG_GPO(GPP_H21, 1, DEEP),
+	PAD_CFG_GPO(GPP_H22, 1, DEEP),
+	PAD_NC(GPP_H23, NONE),
+	PAD_NC(GPP_H24, NONE),
+	PAD_CFG_GPO(GPP_S00, 1, DEEP),
+	PAD_CFG_GPO(GPP_S01, 1, DEEP),
+	PAD_CFG_GPO(GPP_S02, 1, DEEP),
+	PAD_CFG_GPO(GPP_S03, 1, DEEP),
+	PAD_CFG_GPO(GPP_S04, 1, DEEP),
+	PAD_CFG_GPO(GPP_S05, 1, DEEP),
+	PAD_CFG_GPO(GPP_S06, 1, DEEP),
+	PAD_CFG_GPO(GPP_S07, 1, DEEP),
+	PAD_CFG_NF(GPP_V00, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_V01, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_V02, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_V03, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_V07, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_V08, 1, DEEP),
+	PAD_CFG_GPO(GPP_V09, 1, DEEP),
+	PAD_CFG_GPO(GPP_V10, 1, DEEP),
+	PAD_CFG_GPO(GPP_V11, 1, DEEP),
+	PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1),
+	_PAD_CFG_STRUCT(GPP_V13, 0x44000601, 0x0000),
+	_PAD_CFG_STRUCT(GPP_V14, 0x44000601, 0x0000),
+	_PAD_CFG_STRUCT(GPP_V15, 0x44000601, 0x0000),
+	PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_V17, 1, DEEP),
+};
+
+void mainboard_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/system76/ptl/variants/lemp14/gpio_early.c b/src/mainboard/system76/ptl/variants/lemp14/gpio_early.c
new file mode 100644
index 00000000000..a2a5e5bb19f
--- /dev/null
+++ b/src/mainboard/system76/ptl/variants/lemp14/gpio_early.c
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), // SMB_CLK
+	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), // SMB_DATA
+	PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID1
+	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), // UART0_RX
+	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), // UART0_TX
+};
+
+void mainboard_configure_early_gpios(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
diff --git a/src/mainboard/system76/ptl/variants/lemp14/hda_verb.c b/src/mainboard/system76/ptl/variants/lemp14/hda_verb.c
new file mode 100644
index 00000000000..004c6fc6851
--- /dev/null
+++ b/src/mainboard/system76/ptl/variants/lemp14/hda_verb.c
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC245 */
+	0x10ec0245, /* Vendor ID */
+	0x15582a00, /* Subsystem ID */
+	34, /* Number of entries */
+
+	AZALIA_SUBVENDOR(0, 0x15582a00),
+	AZALIA_RESET(1),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x17, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x41789b2d),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x21, 0x04211020),
+
+	//TODO: VERIFY THESE COMMANDS
+	0x05b50006, 0x05b40011, 0x0205001a, 0x0204810b,
+	0x0205004a, 0x02042010, 0x02050038, 0x02046909,
+	0x05c50000, 0x05c43d82, 0x05c50000, 0x05c43d82,
+	0x05350000, 0x0534201a, 0x05350000, 0x0534201a,
+	0x0535001d, 0x05340800, 0x0535001e, 0x05340800,
+	0x05350003, 0x05341ec4, 0x05350004, 0x05340000,
+	0x05450000, 0x05442000, 0x0545001d, 0x05440800,
+	0x0545001e, 0x05440800, 0x05450003, 0x05441ec4,
+	0x05450004, 0x05440000, 0x05350000, 0x0534a01a,
+	0x0205003c, 0x0204f175, 0x0205003c, 0x0204f135,
+	0x02050040, 0x02048800, 0x05a50001, 0x05a4001f,
+	0x02050010, 0x02040020, 0x02050010, 0x02040020,
+	0x0205006b, 0x0204a390, 0x0205006b, 0x0204a390,
+	0x0205006c, 0x02040c9e, 0x0205006d, 0x02040c00,
+	0x00170500, 0x00170500, 0x05a50004, 0x05a40113,
+	0x02050008, 0x02046a8c, 0x02050076, 0x0204f000,
+	0x0205000e, 0x020465c0, 0x02050033, 0x02048580,
+	0x02050069, 0x0204fda8, 0x02050068, 0x02040000,
+	0x02050003, 0x02040002, 0x02050069, 0x02040000,
+	0x02050068, 0x02040001, 0x0205002e, 0x0204290e,
+	0x02050010, 0x02040020, 0x02050010, 0x02040020,
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/system76/ptl/variants/lemp14/memory/Makefile.mk b/src/mainboard/system76/ptl/variants/lemp14/memory/Makefile.mk
new file mode 100644
index 00000000000..2909100fa27
--- /dev/null
+++ b/src/mainboard/system76/ptl/variants/lemp14/memory/Makefile.mk
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/system76/ptl/variants/lemp14/memory src/mainboard/system76/ptl/variants/lemp14/memory/mem_parts_used.txt
+
+SPD_SOURCES =
+SPD_SOURCES += spd/lp5/set-0/spd-2.hex      # ID = 0(0b0000)  Parts = MT62F1G32D4DR-031 WT:B
diff --git a/src/mainboard/system76/ptl/variants/lemp14/memory/dram_id.generated.txt b/src/mainboard/system76/ptl/variants/lemp14/memory/dram_id.generated.txt
new file mode 100644
index 00000000000..4e6a073f961
--- /dev/null
+++ b/src/mainboard/system76/ptl/variants/lemp14/memory/dram_id.generated.txt
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/system76/ptl/variants/lemp14/memory src/mainboard/system76/ptl/variants/lemp14/memory/mem_parts_used.txt
+
+DRAM Part Name                 ID to assign
+MT62F1G32D4DR-031 WT:B         0 (0000)
diff --git a/src/mainboard/system76/ptl/variants/lemp14/memory/mem_parts_used.txt b/src/mainboard/system76/ptl/variants/lemp14/memory/mem_parts_used.txt
new file mode 100644
index 00000000000..b079d45cde5
--- /dev/null
+++ b/src/mainboard/system76/ptl/variants/lemp14/memory/mem_parts_used.txt
@@ -0,0 +1,12 @@
+# This is a CSV file containing a list of memory parts used by this variant.
+# One part per line with an optional fixed ID in column 2.
+# Only include a fixed ID if it is required for legacy reasons!
+# Generated IDs are dependent on the order of parts in this file,
+# so new parts must always be added at the end of the file!
+#
+# Generate an updated Makefile.mk and dram_id.generated.txt by running the
+# part_id_gen tool from util/spd_tools.
+# See util/spd_tools/README.md for more details and instructions.
+
+# Part Name
+MT62F1G32D4DR-031 WT:B
diff --git a/src/mainboard/system76/ptl/variants/lemp14/overridetree.cb b/src/mainboard/system76/ptl/variants/lemp14/overridetree.cb
new file mode 100644
index 00000000000..3193b169a71
--- /dev/null
+++ b/src/mainboard/system76/ptl/variants/lemp14/overridetree.cb
@@ -0,0 +1,112 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/pantherlake
+	#TODO: POWER LIMITS
+	#register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{
+	#	.tdp_pl1_override = 15,
+	#	.tdp_pl2_override = 46,
+	#}"
+
+	device domain 0 on
+		subsystemid 0x1558 0x2a00 inherit
+
+		device ref tbt_pcie_rp0 on end
+		device ref tcss_xhci on
+			register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+			#TODO: TCP1 goes to redriver, then USB Type-C
+			register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+			#TODO: TCP2 is used as USB Type-A
+			register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+			#TODO: TCP3 is used as HDMI
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""TBT Type-C""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref tcss_usb3_port0 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB Type-C""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref tcss_usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB Type-A""
+						register "type" = "UPC_TYPE_USB3_A"
+						device ref tcss_usb3_port2 on end
+					end
+				end
+			end
+		end
+		device ref tcss_dma0 on end
+		device ref xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_TYPE_C(OC_SKIP),	/* USB Type-C */
+				[1] = USB2_PORT_TYPE_C(OC_SKIP),	/* TBT Type-C */
+				[2] = USB2_PORT_MID(OC_SKIP),		/* USB 3.2 Gen 2 Type-A */
+				[4] = USB2_PORT_MID(OC_SKIP),		/* USB 3.2 Gen 1 Type-A */
+				[6] = USB2_PORT_MID(OC_SKIP),		/* Camera */
+				[7] = USB2_PORT_MID(OC_SKIP),		/* Bluetooth */
+			}"
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC_SKIP),	/* USB 3.2 Gen 1 Type-A */
+			}"
+		end
+
+		device ref i2c4 on
+			# Smart Amplifier I2C bus
+			register "serial_io_i2c_mode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
+			chip drivers/i2c/tas5825m
+				register "id" = "0"
+				device i2c 4e on end # (8bit address: 0x9c)
+			end
+		end
+		device ref i2c5 on
+			# Touchpad I2C bus
+			register "serial_io_i2c_mode[PchSerialIoIndexI2C5]" = "PchSerialIoPci"
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN0412""
+				register "generic.desc" = ""ELAN Touchpad""
+				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 15 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""FTCS1000""
+				register "generic.desc" = ""FocalTech Touchpad""
+				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 38 on end
+			end
+		end
+
+		device ref pcie_rp1 on
+			# CPU RP#1 x4, Clock 6 (SSD1)
+			register "pcie_rp[PCIE_RP(1)]" = "{
+				.clk_src = 6,
+				.clk_req = 6,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
+		end
+		device ref pcie_rp7 on
+			# PCH RP#7 x1, Clock 3 (CARD)
+			register "pcie_rp[PCH_RP(7)]" = "{
+				.clk_src = 3,
+				.clk_req = 3,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end
+		device ref pcie_rp8 on
+			# PCH RP#8 x1, Clock 4 (WLAN)
+			register "pcie_rp[PCH_RP(8)]" = "{
+				.clk_src = 4,
+				.clk_req = 4,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
+		end
+	end
+end
diff --git a/src/mainboard/system76/ptl/variants/lemp14/ramstage.c b/src/mainboard/system76/ptl/variants/lemp14/ramstage.c
new file mode 100644
index 00000000000..9118fea7e96
--- /dev/null
+++ b/src/mainboard/system76/ptl/variants/lemp14/ramstage.c
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	// TODO: Pin Mux settings
+
+	// Enable TCP2 USB-A conversion
+	// BIT 0:3 is mapping to PCH XHCI USB2 port
+	// BIT 4:5 is reserved
+	// BIT 6 is orientational
+	// BIT 7 is enable
+	params->EnableTcssCovTypeA[2] = 0x83;
+
+	// Disable reporting CPU C10 state over eSPI (causes LED flicker).
+	params->PchEspiHostC10ReportEnable = 0;
+}
diff --git a/src/mainboard/system76/ptl/variants/lemp14/romstage.c b/src/mainboard/system76/ptl/variants/lemp14/romstage.c
new file mode 100644
index 00000000000..f5413d4629a
--- /dev/null
+++ b/src/mainboard/system76/ptl/variants/lemp14/romstage.c
@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+
+// Verified from lemp14 schematic mappings
+static const struct mb_cfg board_cfg = {
+	.type = MEM_TYPE_LP5X,
+
+	.lpx_dq_map = {
+		.ddr0 = {
+			.dq0 = {  13,  14,  12,  15, 11,  10,  8,  9, },
+			.dq1 = {  7,  5,  4,  6,  0,  3,  1,  2 },
+		},
+		.ddr1 = {
+			.dq0 = {  1,  3,  0,  2,  7,  4,  6,  5, },
+			.dq1 = {  12,  13,  14,  15,  11,  10,  9,  8 },
+		},
+		.ddr2 = {
+			.dq0 = {  0,  2,  1,  3,  6,  4,  7,  5 },
+			.dq1 = {  14,  13,  15,  12,  8,  11,  10,  9, },
+		},
+		.ddr3 = {
+			.dq0 = {  6,  5,  7,  4,  2,  3,  1,  0, },
+			.dq1 = {  10,  8,  11,  9,  12,  15,  13,  14 },
+		},
+		.ddr4 = {
+			.dq0 = {  2,  1,  3,  0,  4,  7,  5,  6 },
+			.dq1 = {  15,  14,  12,  13,  9,  11,  10,  8, },
+		},
+		.ddr5 = {
+			.dq0 = {  6,  5,  7,  4,  3,  1,  0,  2, },
+			.dq1 = {  10,  9,  11,  8,  13,  14,  12,  15 },
+		},
+		.ddr6 = {
+			.dq0 = {  9,  10,  11,  8,  14,  12,  13, 15, },
+			.dq1 = {  0,  1,  2,  3,  5,  7,  4,  6 },
+		},
+		.ddr7 = {
+			.dq0 = {  0,  1,  2,  3,  7,  5,  6,  4, },
+			.dq1 = {  14,  13,  15,  12,  10,  8,  11,  9 },
+		},
+	},
+
+	.lpx_dqs_map = {
+		.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr4 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr6 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr7 = { .dqs0 = 0, .dqs1 = 1 }
+	},
+
+	.ect = true, /* Early Command Training */
+
+	.user_bd = BOARD_TYPE_ULT_ULX,
+
+	.lp5x_config = {
+		.ccc_config = 0xFF,
+	},
+};
+
+static const struct mem_spd spd_info = {
+	.topo = MEM_TOPO_MEMORY_DOWN,
+	.cbfs_index = 0,
+};
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	const bool half_populated = false;
+
+	mupd->FspmConfig.GpioOverride = 0;
+
+	memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
+}
diff --git a/src/mainboard/system76/ptl/variants/lemp14/tas5825m.c b/src/mainboard/system76/ptl/variants/lemp14/tas5825m.c
new file mode 100644
index 00000000000..171d9c1ed20
--- /dev/null
+++ b/src/mainboard/system76/ptl/variants/lemp14/tas5825m.c
@@ -0,0 +1,1049 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <delay.h>
+#include <drivers/i2c/tas5825m/tas5825m.h>
+
+int tas5825m_setup(struct device *dev, int id)
+{
+	int res;
+
+	res = tas5825m_set_book(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x03, 0x02);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x01, 0x11);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x03, 0x02);
+	if (res < 0)
+		return res;
+
+	mdelay(5);
+
+	res = tas5825m_write_at(dev, 0x03, 0x12);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x48, 0x0C);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x7F, 0x64);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x01);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0xFE, 0x00, 0x40, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x50, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0x82, 0x00, 0x93, 0x00, 0xFC, 0x00, 0x00,
+			0x8F, 0x00, 0xFF, 0xEF, 0x84, 0x49, 0x03, 0x27,
+			0x84, 0x02, 0x04, 0x06, 0x02, 0x60, 0x00, 0x01,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x02);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x02, 0x70, 0x00, 0x06, 0x02, 0x78, 0x00, 0x05,
+			0x02, 0x68, 0x00, 0x02, 0x02, 0x28, 0x03, 0x4D,
+			0x84, 0x2A, 0x04, 0x00, 0xE2, 0x57, 0x91, 0x9F,
+			0x84, 0x82, 0x20, 0xE0, 0x84, 0x82, 0x04, 0x01,
+			0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31, 0xA1,
+			0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31, 0xA3,
+			0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80, 0xE1,
+			0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D, 0x31, 0xA5,
+			0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F, 0x31, 0xA8,
+			0x02, 0x78, 0x00, 0x03, 0xE2, 0x68, 0xF1, 0xC3,
+			0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x27,
+			0x02, 0x70, 0x00, 0x04, 0x84, 0x41, 0x03, 0x37,
+			0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11, 0xA9,
+			0x84, 0x82, 0x00, 0xE0, 0x8E, 0xFC, 0x04, 0x10,
+			0xF0, 0x1C, 0x11, 0xAA, 0xF0, 0x1C, 0x11, 0xAB,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x03);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0xF0, 0x1C, 0x11, 0xAC, 0xF0, 0x1F, 0x11, 0xAD,
+			0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xE8,
+			0x60, 0x00, 0x00, 0x00, 0x84, 0x43, 0x03, 0x37,
+			0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10, 0x20,
+			0x84, 0x51, 0x03, 0x3E, 0x08, 0x44, 0x26, 0x30,
+			0x84, 0xC3, 0x03, 0x47, 0x84, 0xC2, 0x40, 0xE0,
+			0x8C, 0xFF, 0x03, 0x23, 0xE0, 0x10, 0x11, 0xB3,
+			0xF0, 0x1C, 0x51, 0xB4, 0xF0, 0x1C, 0x51, 0xB5,
+			0xF0, 0x1C, 0x51, 0xB6, 0xF0, 0x1F, 0x51, 0xB7,
+			0x86, 0xA1, 0x01, 0xC6, 0x80, 0x27, 0x80, 0xEA,
+			0x84, 0x53, 0x03, 0x3E, 0x84, 0x82, 0x04, 0x05,
+			0x84, 0x51, 0x03, 0x75, 0xE2, 0x6B, 0xC0, 0x00,
+			0x80, 0x07, 0x00, 0x80, 0xE0, 0x80, 0x31, 0xB8,
+			0x84, 0x82, 0x40, 0xE0, 0xF0, 0x1C, 0x51, 0xB9,
+			0xF0, 0x1C, 0x51, 0xBA, 0xF0, 0x1C, 0x51, 0xBB,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x04);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0xF0, 0x1F, 0x51, 0xBC, 0x86, 0xA1, 0x01, 0xC5,
+			0x80, 0x27, 0x80, 0xEA, 0x60, 0x00, 0x00, 0x00,
+			0x80, 0x00, 0x00, 0x81, 0x84, 0xA1, 0x03, 0x4F,
+			0xE0, 0x80, 0xA0, 0x00, 0x01, 0x07, 0x11, 0x20,
+			0x08, 0x44, 0x26, 0x30, 0x08, 0x00, 0x98, 0x4A,
+			0x84, 0x53, 0x03, 0x75, 0x08, 0x00, 0x30, 0x48,
+			0x02, 0xCA, 0x00, 0x01, 0x08, 0x60, 0x26, 0x32,
+			0x84, 0x51, 0x03, 0x45, 0xE4, 0x10, 0x40, 0x00,
+			0x80, 0x40, 0xC0, 0x82, 0x84, 0xC2, 0x40, 0xE0,
+			0x84, 0xC3, 0x03, 0x5E, 0x08, 0x00, 0x50, 0x48,
+			0xE0, 0x10, 0x11, 0xBD, 0x02, 0xC2, 0x00, 0x02,
+			0x08, 0x60, 0x06, 0x12, 0x84, 0xD3, 0x03, 0x4F,
+			0xF0, 0x1C, 0x51, 0xBE, 0xF0, 0x1C, 0x51, 0xBF,
+			0xF0, 0x1C, 0x51, 0xC0, 0xF0, 0x1F, 0x51, 0xC1,
+			0x84, 0xA1, 0x03, 0x65, 0x80, 0x27, 0x80, 0xEA,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x05);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0xE0, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x83,
+			0x08, 0x00, 0x98, 0x6B, 0x08, 0x00, 0x30, 0x68,
+			0x84, 0x53, 0x03, 0x45, 0x08, 0x60, 0x26, 0x33,
+			0x84, 0x51, 0x03, 0x25, 0xE4, 0x10, 0x60, 0x00,
+			0x80, 0x40, 0xC0, 0x81, 0x02, 0x70, 0x00, 0x7F,
+			0x08, 0x00, 0x50, 0x28, 0x08, 0x60, 0x06, 0x11,
+			0x84, 0xCB, 0x03, 0x65, 0xE0, 0x10, 0x51, 0xC4,
+			0x84, 0x80, 0x41, 0x00, 0x02, 0xA3, 0x00, 0x10,
+			0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0, 0x04, 0x01,
+			0x84, 0xA2, 0x04, 0x03, 0x84, 0xD2, 0x50, 0x01,
+			0x84, 0x53, 0x03, 0x25, 0x80, 0x00, 0xC4, 0x04,
+			0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00,
+			0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x60, 0x00,
+			0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00, 0x80,
+			0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01, 0x9D,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x06);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E,
+			0x80, 0x00, 0xC4, 0x02, 0x02, 0x50, 0x01, 0x9C,
+			0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00,
+			0x02, 0x60, 0x00, 0x01, 0x02, 0x70, 0x00, 0x04,
+			0x84, 0xC8, 0x04, 0x10, 0x84, 0x41, 0x03, 0x67,
+			0x84, 0x51, 0x03, 0x6D, 0x84, 0xC0, 0x04, 0x02,
+			0x04, 0x80, 0x91, 0x20, 0x08, 0x60, 0x26, 0x30,
+			0x02, 0x78, 0x00, 0x03, 0x02, 0x68, 0x00, 0x02,
+			0x0D, 0x00, 0x10, 0x10, 0x08, 0x60, 0x06, 0x12,
+			0x84, 0x49, 0x03, 0x2F, 0xE0, 0x80, 0x71, 0xA9,
+			0x02, 0x28, 0x03, 0x55, 0x84, 0x82, 0x00, 0xE0,
+			0x84, 0x2A, 0x04, 0x00, 0xF0, 0x1C, 0x11, 0xAA,
+			0xF0, 0x1C, 0x11, 0xAB, 0xF0, 0x1C, 0x11, 0xAC,
+			0xF0, 0x1F, 0x11, 0xAD, 0x86, 0xA1, 0x01, 0xAE,
+			0x80, 0x27, 0x80, 0xE8, 0x84, 0x82, 0x04, 0x07,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x07);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0xE0, 0x80, 0x60, 0x00, 0x84, 0x82, 0x40, 0xE0,
+			0x84, 0x43, 0x03, 0x67, 0xF0, 0x1C, 0x51, 0xAF,
+			0xF0, 0x1C, 0x51, 0xB0, 0xF0, 0x1C, 0x51, 0xB1,
+			0xF0, 0x1F, 0x51, 0xB2, 0x02, 0x78, 0x00, 0x05,
+			0x80, 0x27, 0x80, 0xEA, 0x84, 0x82, 0x04, 0x08,
+			0x02, 0x70, 0x00, 0x06, 0x84, 0x53, 0x03, 0x6D,
+			0x84, 0x80, 0x04, 0x07, 0xE0, 0x00, 0x00, 0x82,
+			0xF0, 0x81, 0x00, 0x80, 0x80, 0x07, 0x12, 0xBC,
+			0x86, 0xA1, 0x01, 0x9F, 0xE2, 0x57, 0xA0, 0x00,
+			0x84, 0x82, 0x04, 0x09, 0x84, 0x82, 0x20, 0xE0,
+			0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31, 0xA1,
+			0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31, 0xA3,
+			0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80, 0xE1,
+			0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D, 0x31, 0xA5,
+			0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F, 0x31, 0xA8,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x08);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x02, 0x78, 0x00, 0x03, 0xE2, 0x6A, 0xF1, 0xC3,
+			0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x2F,
+			0x02, 0x70, 0x00, 0x04, 0x84, 0x59, 0x03, 0x3D,
+			0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11, 0xA9,
+			0x84, 0x82, 0x60, 0xE0, 0x8E, 0xFC, 0x04, 0x10,
+			0xF0, 0x1C, 0x71, 0xAA, 0xF0, 0x1C, 0x71, 0xAB,
+			0xF0, 0x1C, 0x71, 0xAC, 0xF0, 0x1F, 0x71, 0xAD,
+			0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xEB,
+			0x60, 0x00, 0x00, 0x00, 0x84, 0x5B, 0x03, 0x3D,
+			0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10, 0x20,
+			0x84, 0x59, 0x03, 0x3F, 0x08, 0x44, 0x26, 0x30,
+			0x84, 0xC3, 0x03, 0x57, 0x84, 0xC2, 0x60, 0xE0,
+			0xE0, 0x10, 0x11, 0xB3, 0xF0, 0x1C, 0x71, 0xB4,
+			0xF0, 0x1C, 0x71, 0xB5, 0xF0, 0x1C, 0x71, 0xB6,
+			0xF0, 0x1F, 0x71, 0xB7, 0x86, 0xA1, 0x01, 0xC6,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x09);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x80, 0x27, 0x80, 0xEB, 0x84, 0x5B, 0x03, 0x3F,
+			0x84, 0x82, 0x04, 0x0D, 0x84, 0x41, 0x03, 0x76,
+			0xE2, 0x6B, 0xE0, 0x00, 0x80, 0x07, 0x00, 0x80,
+			0xE0, 0x81, 0x31, 0xB8, 0x84, 0x82, 0x00, 0xE0,
+			0xF0, 0x1C, 0x11, 0xB9, 0xF0, 0x1C, 0x11, 0xBA,
+			0xF0, 0x1C, 0x11, 0xBB, 0xF0, 0x1F, 0x11, 0xBC,
+			0x86, 0xA1, 0x01, 0xC5, 0x80, 0x27, 0x80, 0xE8,
+			0x60, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x81,
+			0x84, 0xA1, 0x03, 0x5D, 0xE0, 0x81, 0xA0, 0x00,
+			0x01, 0x07, 0x11, 0x20, 0x08, 0x44, 0x26, 0x30,
+			0x08, 0x00, 0x98, 0x4A, 0x84, 0x43, 0x03, 0x76,
+			0x08, 0x00, 0x30, 0x48, 0x02, 0xCA, 0x00, 0x01,
+			0x08, 0x60, 0x26, 0x32, 0x84, 0x41, 0x03, 0x46,
+			0xE4, 0x10, 0x40, 0x00, 0x80, 0x40, 0xC0, 0x82,
+			0x84, 0xC2, 0x00, 0xE0, 0x84, 0xC3, 0x03, 0x5F,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0A);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x08, 0x00, 0x50, 0x48, 0xE0, 0x10, 0x11, 0xBD,
+			0x02, 0xC2, 0x00, 0x02, 0x08, 0x60, 0x06, 0x12,
+			0x84, 0xD3, 0x03, 0x5D, 0xF0, 0x1C, 0x11, 0xBE,
+			0xF0, 0x1C, 0x11, 0xBF, 0xF0, 0x1C, 0x11, 0xC0,
+			0xF0, 0x1F, 0x11, 0xC1, 0x84, 0xA1, 0x03, 0x66,
+			0x80, 0x27, 0x80, 0xE8, 0xE0, 0x00, 0x00, 0x00,
+			0x80, 0x07, 0x00, 0x83, 0x08, 0x00, 0x98, 0x6B,
+			0x08, 0x00, 0x30, 0x68, 0x84, 0x43, 0x03, 0x46,
+			0x08, 0x60, 0x26, 0x33, 0x84, 0x51, 0x03, 0x26,
+			0xE4, 0x10, 0x60, 0x00, 0x80, 0x40, 0xC0, 0x81,
+			0x02, 0x70, 0x00, 0x7F, 0x08, 0x00, 0x50, 0x28,
+			0x08, 0x60, 0x06, 0x11, 0x8C, 0xFF, 0x03, 0x24,
+			0x84, 0xCB, 0x03, 0x66, 0xE0, 0x10, 0x51, 0xC4,
+			0x84, 0x80, 0x41, 0x00, 0x02, 0xA3, 0x00, 0x10,
+			0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0, 0x04, 0x09,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0B);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x84, 0xA2, 0x04, 0x0B, 0x84, 0xD2, 0x50, 0x01,
+			0x84, 0x53, 0x03, 0x26, 0x80, 0x00, 0xC4, 0x0C,
+			0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00,
+			0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x80, 0x00,
+			0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00, 0x80,
+			0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01, 0x9D,
+			0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E,
+			0x80, 0x00, 0xC4, 0x0A, 0x02, 0x50, 0x01, 0x9C,
+			0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00,
+			0x02, 0x70, 0x00, 0x04, 0x02, 0x68, 0x00, 0x01,
+			0x02, 0x60, 0x00, 0x03, 0x02, 0x78, 0x00, 0x02,
+			0x84, 0x49, 0x03, 0x6E, 0x84, 0x41, 0x03, 0x6F,
+			0x84, 0xC8, 0x04, 0x10, 0x84, 0xC0, 0x04, 0x0A,
+			0x04, 0x81, 0x91, 0x20, 0x08, 0x60, 0x26, 0x30,
+			0x0D, 0x00, 0x10, 0x10, 0x08, 0x60, 0x06, 0x12,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0C);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x84, 0x00, 0x04, 0x06, 0xE0, 0x81, 0x71, 0xA9,
+			0x84, 0x82, 0x20, 0xE8, 0xF0, 0x1D, 0x31, 0xAA,
+			0xF0, 0x1D, 0x31, 0xAB, 0xF0, 0x1D, 0x31, 0xAC,
+			0xF0, 0x1C, 0x31, 0xAD, 0x86, 0xA1, 0x01, 0xAE,
+			0x80, 0x27, 0x80, 0xF9, 0x84, 0x82, 0x04, 0x0E,
+			0xE0, 0x81, 0x60, 0x00, 0x84, 0x82, 0x00, 0xE8,
+			0x84, 0x4B, 0x03, 0x6E, 0xF0, 0x1D, 0x11, 0xAF,
+			0xF0, 0x1D, 0x11, 0xB0, 0xF0, 0x1D, 0x11, 0xB1,
+			0xF0, 0x1C, 0x11, 0xB2, 0x02, 0xA3, 0x00, 0x1A,
+			0x80, 0x27, 0x80, 0xF8, 0x84, 0x82, 0x04, 0x0F,
+			0xE0, 0x81, 0xC0, 0x00, 0xF0, 0x81, 0xE0, 0x80,
+			0x84, 0x43, 0x03, 0x6F, 0x80, 0x07, 0x12, 0xBD,
+			0x02, 0xC0, 0x00, 0x00, 0x00, 0xFC, 0x50, 0x00,
+			0x8F, 0x00, 0x00, 0x11, 0x8F, 0x00, 0xFF, 0xFF,
+			0x84, 0x58, 0x04, 0x01, 0x84, 0xC2, 0x04, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0D);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x02, 0xC2, 0x60, 0x00, 0x84, 0xA0, 0x61, 0x00,
+			0xE0, 0x20, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x40, 0x40, 0xA0, 0x00, 0x80, 0x00, 0xC0, 0x82,
+			0x08, 0xFC, 0x48, 0x3A, 0x08, 0xFC, 0x18, 0x50,
+			0x00, 0xFC, 0x00, 0x00, 0xE0, 0x10, 0x00, 0x00,
+			0x86, 0xA0, 0x41, 0x00, 0x40, 0x47, 0x20, 0x00,
+			0x80, 0x00, 0xC0, 0x83, 0x04, 0xE0, 0x3D, 0x1E,
+			0x04, 0x80, 0x11, 0xE0, 0x08, 0x44, 0x26, 0x33,
+			0x02, 0xCB, 0x00, 0x10, 0xE0, 0x10, 0x40, 0x83,
+			0x08, 0x00, 0x28, 0x21, 0x84, 0xCA, 0x61, 0x00,
+			0x80, 0x07, 0x00, 0x81, 0x0C, 0xE0, 0x2C, 0x09,
+			0x84, 0xCA, 0x21, 0x00, 0x00, 0xFC, 0x50, 0x00,
+			0x8F, 0x00, 0x00, 0x01, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0x78);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x18);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x30, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x1B);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x03, 0x80, 0x00, 0x00, 0x04, 0x00,
+			0x00, 0x00, 0x03, 0x28, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x1C);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x03, 0x30, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x1C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x03, 0x38, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x3C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x03, 0x40, 0x00, 0x00, 0x03, 0x48,
+			0x00, 0x00, 0x03, 0x50, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x54, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x03, 0x58, 0x00, 0x00, 0x03, 0x60,
+			0x00, 0x00, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x74, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x1D);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x1C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x3C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x1E);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x03, 0x68, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x0C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x03, 0x70, 0x00, 0x00, 0x03, 0x78,
+			0x00, 0x00, 0x04, 0x80, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x24, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x04, 0x88, 0x00, 0x00, 0x04, 0x90,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x44, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0x8C);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x0E);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0xA7, 0x26, 0x4A, 0x7F, 0xFF, 0xFF, 0xFF,
+			0x00, 0x20, 0xC4, 0x9C, 0x00, 0x20, 0xC4, 0x9C,
+			0x00, 0x00, 0x68, 0xDB, 0x00, 0x00, 0xD1, 0xB7,
+			0x00, 0x00, 0x68, 0xDB, 0x0F, 0xA4, 0xA8, 0xC1,
+			0xF8, 0x59, 0x7F, 0x63, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0F);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x2F, 0xB7, 0xE9,
+			0x00, 0x5F, 0x6F, 0xD2, 0x00, 0x2F, 0xB7, 0xE9,
+			0x0B, 0x1E, 0x4F, 0x76, 0xFC, 0x23, 0x05, 0x54,
+			0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x7D, 0xBF, 0x48,
+			0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x1E, 0x4F, 0x76,
+			0xFC, 0x23, 0x05, 0x54, 0x00, 0x04, 0x81, 0x6F,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB, 0x98, 0xC8,
+			0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x81, 0x6F,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB, 0x98, 0xC8,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x10);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x89, 0xA0, 0x27, 0x7F, 0xEC, 0x56, 0xD5,
+			0x7F, 0xFC, 0xB9, 0x23, 0x00, 0x89, 0xA0, 0x27,
+			0x7F, 0xEC, 0x56, 0xD5, 0x7F, 0xFC, 0xB9, 0x23,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x40, 0x00);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x11, 0xFF, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x7D, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x01);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x51, 0x05);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x02);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x19, 0xDF);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x46, 0x11);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x02, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x53, 0x01);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x54, 0x17);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x03, 0x02);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x7F, 0x8C);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x01);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x71, 0x94, 0x9A, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x2C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0A);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x64, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0B);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x28, 0x7A, 0x27,
+			0x00, 0x28, 0x7A, 0x27, 0x00, 0x80, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x57, 0x62, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x28, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0E);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x03, 0x69, 0xC5, 0x00, 0xEE, 0xC9, 0x55,
+			0x00, 0x22, 0x1D, 0x95, 0x00, 0x03, 0x69, 0xC5,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0F);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x7F, 0xF9, 0x2C, 0x60, 0x07, 0x77, 0x1A, 0x4F,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x07);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x80, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x64, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	{
+		const uint8_t values[] = {
+			0x40, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0xAA);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x01);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x30, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x02);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x03);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x07, 0xC5, 0xCA, 0x98,
+			0xF0, 0x74, 0x6A, 0xD0, 0x07, 0xC5, 0xCA, 0x98,
+			0x0F, 0x8A, 0x9A, 0x1D, 0xF8, 0x73, 0x6F, 0xBD,
+			0x07, 0xCC, 0x4D, 0x23, 0xF0, 0x8F, 0xEC, 0x92,
+			0x07, 0xA8, 0xA9, 0xB4, 0x0F, 0x70, 0x13, 0x6E,
+			0xF8, 0x8B, 0x09, 0x29, 0x08, 0x2F, 0x93, 0x82,
+			0xF0, 0x34, 0x1D, 0x7A, 0x07, 0xA1, 0x4F, 0x7F,
+			0x0F, 0xCD, 0x63, 0x79, 0xF8, 0x30, 0x9D, 0xF2,
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x04);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x05);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x07, 0xC5, 0xCA, 0x98, 0xF0, 0x74, 0x6A, 0xD0,
+			0x07, 0xC5, 0xCA, 0x98, 0x0F, 0x8A, 0x9A, 0x1D,
+			0xF8, 0x73, 0x6F, 0xBD, 0x07, 0xCC, 0x4D, 0x23,
+			0xF0, 0x8F, 0xEC, 0x92, 0x07, 0xA8, 0xA9, 0xB4,
+			0x0F, 0x70, 0x13, 0x6E, 0xF8, 0x8B, 0x09, 0x29,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x06);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x08, 0x2F, 0x93, 0x82, 0xF0, 0x34, 0x1D, 0x7A,
+			0x07, 0xA1, 0x4F, 0x7F, 0x0F, 0xCD, 0x63, 0x79,
+			0xF8, 0x30, 0x9D, 0xF2, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0E);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x91, 0xDC, 0xC5, 0xFF, 0x04, 0xF3, 0x02,
+			0x00, 0x6E, 0x34, 0x0A, 0x0F, 0xD6, 0x6C, 0x7A,
+			0xF8, 0x24, 0x8F, 0xB5, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0F);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0xFF, 0xF4, 0x49, 0x81,
+			0xFF, 0xE8, 0x93, 0x02, 0xFF, 0xF4, 0x49, 0x81,
+			0x0D, 0x94, 0x7A, 0x64, 0xFA, 0x3C, 0xAB, 0xA1,
+			0x06, 0xD5, 0xF3, 0xB1, 0xF2, 0x54, 0x18, 0x9F,
+			0x06, 0xD5, 0xF3, 0xB1, 0x0D, 0x94, 0x7A, 0x64,
+			0xFA, 0x3C, 0xAB, 0xA1, 0x00, 0x00, 0x38, 0xE4,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x0F, 0xD5, 0x55, 0x55, 0xF8, 0x2A, 0x71, 0xC7,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x30, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x60, 0x02);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x62, 0x09);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x4C, 0x30);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x03, 0x03);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x78, 0x80);
+	if (res < 0)
+		return res;
+
+	return 0;
+}

From 97e8d7a99a7f6495cb7c646cba5ec2cd86df3a76 Mon Sep 17 00:00:00 2001
From: Jeremy Soller <jackpot51@gmail.com>
Date: Fri, 6 Mar 2026 13:34:51 -0700
Subject: [PATCH 02/13] lemp14: use correct SPDs

---
 src/mainboard/system76/ptl/Makefile.mk        |  3 +-
 src/mainboard/system76/ptl/spd/Makefile.mk    |  6 ----
 .../ptl/spd/samsung-K3KL8L80DM-MGCU.spd.hex   | 33 +++++++++++++++++++
 .../ptl/spd/samsung-K3KL9L90EM-MGCU.spd.hex   | 33 +++++++++++++++++++
 .../system76/ptl/variants/lemp14/gpio_early.c |  2 --
 .../ptl/variants/lemp14/memory/Makefile.mk    |  7 ----
 .../lemp14/memory/dram_id.generated.txt       |  7 ----
 .../variants/lemp14/memory/mem_parts_used.txt | 12 -------
 .../system76/ptl/variants/lemp14/romstage.c   | 21 +++++++++---
 9 files changed, 84 insertions(+), 40 deletions(-)
 delete mode 100644 src/mainboard/system76/ptl/spd/Makefile.mk
 create mode 100644 src/mainboard/system76/ptl/spd/samsung-K3KL8L80DM-MGCU.spd.hex
 create mode 100644 src/mainboard/system76/ptl/spd/samsung-K3KL9L90EM-MGCU.spd.hex
 delete mode 100644 src/mainboard/system76/ptl/variants/lemp14/memory/Makefile.mk
 delete mode 100644 src/mainboard/system76/ptl/variants/lemp14/memory/dram_id.generated.txt
 delete mode 100644 src/mainboard/system76/ptl/variants/lemp14/memory/mem_parts_used.txt

diff --git a/src/mainboard/system76/ptl/Makefile.mk b/src/mainboard/system76/ptl/Makefile.mk
index 08bd6b0627b..33c81b161cc 100644
--- a/src/mainboard/system76/ptl/Makefile.mk
+++ b/src/mainboard/system76/ptl/Makefile.mk
@@ -13,5 +13,4 @@ ramstage-y += variants/$(VARIANT_DIR)/gpio.c
 ramstage-y += variants/$(VARIANT_DIR)/ramstage.c
 ramstage-$(CONFIG_DRIVERS_I2C_TAS5825M) += variants/$(VARIANT_DIR)/tas5825m.c
 
-subdirs-y += variants/$(VARIANT_DIR)/memory
-subdirs-$(CONFIG_HAVE_SPD_IN_CBFS) += spd
+SPD_SOURCES = samsung-K3KL8L80DM-MGCU samsung-K3KL9L90EM-MGCU
diff --git a/src/mainboard/system76/ptl/spd/Makefile.mk b/src/mainboard/system76/ptl/spd/Makefile.mk
deleted file mode 100644
index be4d98bd1d7..00000000000
--- a/src/mainboard/system76/ptl/spd/Makefile.mk
+++ /dev/null
@@ -1,6 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-or-later
-##
-
-ifneq ($(SPD_SOURCES),)
-LIB_SPD_DEPS := $(SPD_SOURCES)
-endif
diff --git a/src/mainboard/system76/ptl/spd/samsung-K3KL8L80DM-MGCU.spd.hex b/src/mainboard/system76/ptl/spd/samsung-K3KL8L80DM-MGCU.spd.hex
new file mode 100644
index 00000000000..7e41dd28542
--- /dev/null
+++ b/src/mainboard/system76/ptl/spd/samsung-K3KL8L80DM-MGCU.spd.hex
@@ -0,0 +1,33 @@
+# Samsung K3KL8L80DM-MGCU
+23 10 15 0e 86 22 95 08 00 40 00 00 02 01 00 00
+48 00 08 ff 92 55 05 00 aa 00 90 a8 90 c0 08 60
+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 7f c1 89 20
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 4b 33 4b 4c 38 4c 38
+30 44 4d 2d 4d 47 43 55 00 00 00 00 00 00 80 ce
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/system76/ptl/spd/samsung-K3KL9L90EM-MGCU.spd.hex b/src/mainboard/system76/ptl/spd/samsung-K3KL9L90EM-MGCU.spd.hex
new file mode 100644
index 00000000000..62f8ae330c1
--- /dev/null
+++ b/src/mainboard/system76/ptl/spd/samsung-K3KL9L90EM-MGCU.spd.hex
@@ -0,0 +1,33 @@
+# Samsung K3KL9L90EM-MGCU
+23 10 15 0e 86 22 b5 08 00 40 00 00 0a 01 00 00
+48 00 08 ff 92 55 05 00 aa 00 90 a8 90 c0 08 60
+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 7f c1 c5 78
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 4b 33 4b 4c 39 4c 39
+30 44 4d 2d 4d 47 43 55 00 00 00 00 00 00 80 ce
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/system76/ptl/variants/lemp14/gpio_early.c b/src/mainboard/system76/ptl/variants/lemp14/gpio_early.c
index a2a5e5bb19f..46ed8112dc5 100644
--- a/src/mainboard/system76/ptl/variants/lemp14/gpio_early.c
+++ b/src/mainboard/system76/ptl/variants/lemp14/gpio_early.c
@@ -4,8 +4,6 @@
 #include <soc/gpio.h>
 
 static const struct pad_config early_gpio_table[] = {
-	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), // SMB_CLK
-	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), // SMB_DATA
 	PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID1
 	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), // UART0_RX
 	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), // UART0_TX
diff --git a/src/mainboard/system76/ptl/variants/lemp14/memory/Makefile.mk b/src/mainboard/system76/ptl/variants/lemp14/memory/Makefile.mk
deleted file mode 100644
index 2909100fa27..00000000000
--- a/src/mainboard/system76/ptl/variants/lemp14/memory/Makefile.mk
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-or-later
-# This is an auto-generated file. Do not edit!!
-# Generated by:
-# util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/system76/ptl/variants/lemp14/memory src/mainboard/system76/ptl/variants/lemp14/memory/mem_parts_used.txt
-
-SPD_SOURCES =
-SPD_SOURCES += spd/lp5/set-0/spd-2.hex      # ID = 0(0b0000)  Parts = MT62F1G32D4DR-031 WT:B
diff --git a/src/mainboard/system76/ptl/variants/lemp14/memory/dram_id.generated.txt b/src/mainboard/system76/ptl/variants/lemp14/memory/dram_id.generated.txt
deleted file mode 100644
index 4e6a073f961..00000000000
--- a/src/mainboard/system76/ptl/variants/lemp14/memory/dram_id.generated.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-or-later
-# This is an auto-generated file. Do not edit!!
-# Generated by:
-# util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/system76/ptl/variants/lemp14/memory src/mainboard/system76/ptl/variants/lemp14/memory/mem_parts_used.txt
-
-DRAM Part Name                 ID to assign
-MT62F1G32D4DR-031 WT:B         0 (0000)
diff --git a/src/mainboard/system76/ptl/variants/lemp14/memory/mem_parts_used.txt b/src/mainboard/system76/ptl/variants/lemp14/memory/mem_parts_used.txt
deleted file mode 100644
index b079d45cde5..00000000000
--- a/src/mainboard/system76/ptl/variants/lemp14/memory/mem_parts_used.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-# This is a CSV file containing a list of memory parts used by this variant.
-# One part per line with an optional fixed ID in column 2.
-# Only include a fixed ID if it is required for legacy reasons!
-# Generated IDs are dependent on the order of parts in this file,
-# so new parts must always be added at the end of the file!
-#
-# Generate an updated Makefile.mk and dram_id.generated.txt by running the
-# part_id_gen tool from util/spd_tools.
-# See util/spd_tools/README.md for more details and instructions.
-
-# Part Name
-MT62F1G32D4DR-031 WT:B
diff --git a/src/mainboard/system76/ptl/variants/lemp14/romstage.c b/src/mainboard/system76/ptl/variants/lemp14/romstage.c
index f5413d4629a..03aec239999 100644
--- a/src/mainboard/system76/ptl/variants/lemp14/romstage.c
+++ b/src/mainboard/system76/ptl/variants/lemp14/romstage.c
@@ -63,13 +63,26 @@ static const struct mb_cfg board_cfg = {
 	},
 };
 
-static const struct mem_spd spd_info = {
-	.topo = MEM_TOPO_MEMORY_DOWN,
-	.cbfs_index = 0,
-};
+
+
+static size_t get_spd_index(void)
+{
+	if (gpio_get(GPP_E11)) {
+		// If BOARD_ID1 is high, the system has 16 GB of RAM using 4x32Gb modules
+		return 0;
+	} else {
+		// If BOARD_ID1 is low, the system has 32 GB of RAM using 4x64Gb modules
+		return 1;
+	}
+}
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
+
+	const struct mem_spd spd_info = {
+		.topo = MEM_TOPO_MEMORY_DOWN,
+		.cbfs_index = get_spd_index(),
+	};
 	const bool half_populated = false;
 
 	mupd->FspmConfig.GpioOverride = 0;

From fa71b911c21fa531633b99487ff45fa50f6abe6c Mon Sep 17 00:00:00 2001
From: Jeremy Soller <jackpot51@gmail.com>
Date: Thu, 12 Mar 2026 14:04:40 -0600
Subject: [PATCH 03/13] lemp14: use correct SPDs

---
 src/mainboard/system76/ptl/Makefile.mk        |  2 +-
 ....hex => Foresee-16GB-FX5P2004G-60.spd.hex} | 10 +++---
 .../ptl/spd/Foresee-32GB-FX5P4008G-60.spd.hex | 33 +++++++++++++++++++
 .../spd/Micron-16GB-MT62F1G32D2DS-023.spd.hex | 33 +++++++++++++++++++
 ... => Micron-32GB-MT62F2G32D4DS-023.spd.hex} |  8 ++---
 .../system76/ptl/variants/lemp14/gpio_early.c |  1 +
 .../system76/ptl/variants/lemp14/romstage.c   | 19 +++++++----
 7 files changed, 90 insertions(+), 16 deletions(-)
 rename src/mainboard/system76/ptl/spd/{samsung-K3KL8L80DM-MGCU.spd.hex => Foresee-16GB-FX5P2004G-60.spd.hex} (85%)
 create mode 100644 src/mainboard/system76/ptl/spd/Foresee-32GB-FX5P4008G-60.spd.hex
 create mode 100644 src/mainboard/system76/ptl/spd/Micron-16GB-MT62F1G32D2DS-023.spd.hex
 rename src/mainboard/system76/ptl/spd/{samsung-K3KL9L90EM-MGCU.spd.hex => Micron-32GB-MT62F2G32D4DS-023.spd.hex} (88%)

diff --git a/src/mainboard/system76/ptl/Makefile.mk b/src/mainboard/system76/ptl/Makefile.mk
index 33c81b161cc..b06b69bc86a 100644
--- a/src/mainboard/system76/ptl/Makefile.mk
+++ b/src/mainboard/system76/ptl/Makefile.mk
@@ -13,4 +13,4 @@ ramstage-y += variants/$(VARIANT_DIR)/gpio.c
 ramstage-y += variants/$(VARIANT_DIR)/ramstage.c
 ramstage-$(CONFIG_DRIVERS_I2C_TAS5825M) += variants/$(VARIANT_DIR)/tas5825m.c
 
-SPD_SOURCES = samsung-K3KL8L80DM-MGCU samsung-K3KL9L90EM-MGCU
+SPD_SOURCES = Foresee-16GB-FX5P2004G-60 Foresee-32GB-FX5P4008G-60 Micron-16GB-MT62F1G32D2DS-023 Micron-32GB-MT62F2G32D4DS-023
diff --git a/src/mainboard/system76/ptl/spd/samsung-K3KL8L80DM-MGCU.spd.hex b/src/mainboard/system76/ptl/spd/Foresee-16GB-FX5P2004G-60.spd.hex
similarity index 85%
rename from src/mainboard/system76/ptl/spd/samsung-K3KL8L80DM-MGCU.spd.hex
rename to src/mainboard/system76/ptl/spd/Foresee-16GB-FX5P2004G-60.spd.hex
index 7e41dd28542..c852010c722 100644
--- a/src/mainboard/system76/ptl/spd/samsung-K3KL8L80DM-MGCU.spd.hex
+++ b/src/mainboard/system76/ptl/spd/Foresee-16GB-FX5P2004G-60.spd.hex
@@ -1,12 +1,14 @@
-# Samsung K3KL8L80DM-MGCU
+# Foresee-16GB-FX5P2004G-60
 23 10 15 0e 86 22 95 08 00 40 00 00 02 01 00 00
-48 00 08 ff 92 55 05 00 aa 00 90 a8 90 c0 08 60
+48 00 09 ff 92 55 05 00 aa 00 90 a8 90 c0 08 60
 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 7f c1 89 20
+00 00 00 00 00 00 00 00 00 00 00 00 7f c6 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
@@ -19,8 +21,6 @@
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 4b 33 4b 4c 38 4c 38
-30 44 4d 2d 4d 47 43 55 00 00 00 00 00 00 80 ce
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/system76/ptl/spd/Foresee-32GB-FX5P4008G-60.spd.hex b/src/mainboard/system76/ptl/spd/Foresee-32GB-FX5P4008G-60.spd.hex
new file mode 100644
index 00000000000..d468db80bd7
--- /dev/null
+++ b/src/mainboard/system76/ptl/spd/Foresee-32GB-FX5P4008G-60.spd.hex
@@ -0,0 +1,33 @@
+# Foresee-32GB-FX5P4008G-60
+23 10 15 0e 86 22 b5 08 00 40 00 00 0a 01 00 00
+48 00 09 ff 92 55 05 00 aa 00 90 a8 90 c0 08 60
+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 7f c6 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/system76/ptl/spd/Micron-16GB-MT62F1G32D2DS-023.spd.hex b/src/mainboard/system76/ptl/spd/Micron-16GB-MT62F1G32D2DS-023.spd.hex
new file mode 100644
index 00000000000..c566640ec54
--- /dev/null
+++ b/src/mainboard/system76/ptl/spd/Micron-16GB-MT62F1G32D2DS-023.spd.hex
@@ -0,0 +1,33 @@
+# Micron-16GB-MT62F1G32D2DS-023
+23 10 13 0e 16 22 95 08 00 40 00 00 02 01 00 00
+48 00 0a ff 92 55 05 00 aa 00 90 a8 90 c0 08 60
+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 7f 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/system76/ptl/spd/samsung-K3KL9L90EM-MGCU.spd.hex b/src/mainboard/system76/ptl/spd/Micron-32GB-MT62F2G32D4DS-023.spd.hex
similarity index 88%
rename from src/mainboard/system76/ptl/spd/samsung-K3KL9L90EM-MGCU.spd.hex
rename to src/mainboard/system76/ptl/spd/Micron-32GB-MT62F2G32D4DS-023.spd.hex
index 62f8ae330c1..f9b37252a16 100644
--- a/src/mainboard/system76/ptl/spd/samsung-K3KL9L90EM-MGCU.spd.hex
+++ b/src/mainboard/system76/ptl/spd/Micron-32GB-MT62F2G32D4DS-023.spd.hex
@@ -1,4 +1,4 @@
-# Samsung K3KL9L90EM-MGCU
+# Micron-32GB-MT62F2G32D4DS-023
 23 10 15 0e 86 22 b5 08 00 40 00 00 0a 01 00 00
 48 00 08 ff 92 55 05 00 aa 00 90 a8 90 c0 08 60
 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
@@ -6,7 +6,9 @@
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 7f c1 c5 78
+00 00 00 00 00 00 00 00 00 00 00 00 7f c2 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
@@ -19,8 +21,6 @@
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 4b 33 4b 4c 39 4c 39
-30 44 4d 2d 4d 47 43 55 00 00 00 00 00 00 80 ce
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/system76/ptl/variants/lemp14/gpio_early.c b/src/mainboard/system76/ptl/variants/lemp14/gpio_early.c
index 46ed8112dc5..9897e3c7df7 100644
--- a/src/mainboard/system76/ptl/variants/lemp14/gpio_early.c
+++ b/src/mainboard/system76/ptl/variants/lemp14/gpio_early.c
@@ -5,6 +5,7 @@
 
 static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID1
+	PAD_CFG_GPI(GPP_E15, NONE, DEEP), // BOARD_ID3
 	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), // UART0_RX
 	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), // UART0_TX
 };
diff --git a/src/mainboard/system76/ptl/variants/lemp14/romstage.c b/src/mainboard/system76/ptl/variants/lemp14/romstage.c
index 03aec239999..6d1c2a26366 100644
--- a/src/mainboard/system76/ptl/variants/lemp14/romstage.c
+++ b/src/mainboard/system76/ptl/variants/lemp14/romstage.c
@@ -67,13 +67,20 @@ static const struct mb_cfg board_cfg = {
 
 static size_t get_spd_index(void)
 {
-	if (gpio_get(GPP_E11)) {
-		// If BOARD_ID1 is high, the system has 16 GB of RAM using 4x32Gb modules
-		return 0;
-	} else {
-		// If BOARD_ID1 is low, the system has 32 GB of RAM using 4x64Gb modules
-		return 1;
+    // 0: Foresee 16 GiB
+    // 1: Foresee 32 GiB
+    // 2: Micron 16 GiB
+    // 3: Micron 32 GiB
+    size_t index = 0;
+    if (gpio_get(GPP_E15)) {
+        // If BOARD_ID3 is high, the system uses Micron memory
+        index += 2;
+    }
+	if (!gpio_get(GPP_E11)) {
+		// If BOARD_ID1 is low, the system has 32 GB of RAM
+		index += 1;
 	}
+	return index;
 }
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)

From 0329ed63d620970ac797462dfcc4d525045b1c55 Mon Sep 17 00:00:00 2001
From: Tim Crawford <tcrawford@system76.com>
Date: Mon, 23 Mar 2026 10:17:43 -0600
Subject: [PATCH 04/13] mb/system76/ptl: Fix indentation

Signed-off-by: Tim Crawford <tcrawford@system76.com>
---
 .../system76/ptl/variants/lemp14/romstage.c    | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/mainboard/system76/ptl/variants/lemp14/romstage.c b/src/mainboard/system76/ptl/variants/lemp14/romstage.c
index 6d1c2a26366..4d6a105bcdb 100644
--- a/src/mainboard/system76/ptl/variants/lemp14/romstage.c
+++ b/src/mainboard/system76/ptl/variants/lemp14/romstage.c
@@ -67,15 +67,15 @@ static const struct mb_cfg board_cfg = {
 
 static size_t get_spd_index(void)
 {
-    // 0: Foresee 16 GiB
-    // 1: Foresee 32 GiB
-    // 2: Micron 16 GiB
-    // 3: Micron 32 GiB
-    size_t index = 0;
-    if (gpio_get(GPP_E15)) {
-        // If BOARD_ID3 is high, the system uses Micron memory
-        index += 2;
-    }
+	// 0: Foresee 16 GiB
+	// 1: Foresee 32 GiB
+	// 2: Micron 16 GiB
+	// 3: Micron 32 GiB
+	size_t index = 0;
+	if (gpio_get(GPP_E15)) {
+		// If BOARD_ID3 is high, the system uses Micron memory
+		index += 2;
+	}
 	if (!gpio_get(GPP_E11)) {
 		// If BOARD_ID1 is low, the system has 32 GB of RAM
 		index += 1;

From 698d79d4176f6d6b19e7bb92ea1275e59cc78511 Mon Sep 17 00:00:00 2001
From: Tim Crawford <tcrawford@system76.com>
Date: Mon, 23 Mar 2026 10:18:21 -0600
Subject: [PATCH 05/13] mb/system76/ptl: Remove crashlog selection

Config is selected by SoC.

Signed-off-by: Tim Crawford <tcrawford@system76.com>
---
 src/mainboard/system76/ptl/Kconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/mainboard/system76/ptl/Kconfig b/src/mainboard/system76/ptl/Kconfig
index da29d0a0030..c8970a51310 100644
--- a/src/mainboard/system76/ptl/Kconfig
+++ b/src/mainboard/system76/ptl/Kconfig
@@ -21,7 +21,6 @@ config BOARD_SYSTEM76_PTL_COMMON
 	select NO_UART_ON_SUPERIO
 	select PCIEXP_SUPPORT_RESIZABLE_BARS
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
-	select SOC_INTEL_CRASHLOG
 	select SOC_INTEL_PANTHERLAKE_U_H
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP

From 4a1314a8e24fcfc68d416a970f60a313423279d9 Mon Sep 17 00:00:00 2001
From: Tim Crawford <tcrawford@system76.com>
Date: Mon, 23 Mar 2026 10:51:12 -0600
Subject: [PATCH 06/13] mb/system76/ptl: Document GPIOs

Signed-off-by: Tim Crawford <tcrawford@system76.com>
---
 .../system76/ptl/variants/lemp14/gpio.c       | 208 +++++++++---------
 1 file changed, 108 insertions(+), 100 deletions(-)

diff --git a/src/mainboard/system76/ptl/variants/lemp14/gpio.c b/src/mainboard/system76/ptl/variants/lemp14/gpio.c
index d81813108f6..843090bd662 100644
--- a/src/mainboard/system76/ptl/variants/lemp14/gpio.c
+++ b/src/mainboard/system76/ptl/variants/lemp14/gpio.c
@@ -4,75 +4,78 @@
 #include <soc/gpio.h>
 
 static const struct pad_config gpio_table[] = {
-	PAD_CFG_NF(GPP_A00, NONE, DEEP, NF1),
-	PAD_CFG_GPO(GPP_A01, 1, DEEP),
-	PAD_CFG_GPO(GPP_A02, 1, DEEP),
-	PAD_CFG_GPO(GPP_A03, 1, DEEP),
-	PAD_CFG_GPO(GPP_A04, 1, DEEP),
-	PAD_CFG_GPO(GPP_A05, 1, DEEP),
-	PAD_CFG_GPO(GPP_A06, 1, DEEP),
+	PAD_CFG_NF(GPP_A00, NONE, DEEP, NF1), // ESPI_IO0_EC
+	PAD_CFG_GPO(GPP_A01, 1, DEEP), // ESPI_IO1_EC
+	PAD_CFG_GPO(GPP_A02, 1, DEEP), // ESPI_IO2_EC
+	PAD_CFG_GPO(GPP_A03, 1, DEEP), // ESPI_IO3_EC
+	PAD_CFG_GPO(GPP_A04, 1, DEEP), // ESPI_CS_EC#
+	PAD_CFG_GPO(GPP_A05, 1, DEEP), // ESPI_CLK_EC
+	PAD_CFG_GPO(GPP_A06, 1, DEEP), // ESPI_RESET#
 	PAD_CFG_GPO(GPP_A07, 1, DEEP),
-	PAD_CFG_NF(GPP_A08, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A08, NONE, DEEP, NF1), // SD_PWR_EN
 	PAD_CFG_NF(GPP_A09, NONE, DEEP, NF1),
 	PAD_CFG_NF(GPP_A10, UP_20K, DEEP, NF1),
-	PAD_CFG_NF(GPP_A11, UP_20K, DEEP, NF1),
-	PAD_NC(GPP_A12, NATIVE),
-	PAD_CFG_NF(GPP_A13, NATIVE, DEEP, NF2),
+	PAD_CFG_NF(GPP_A11, UP_20K, DEEP, NF1), // WLAN_RST#
+	PAD_NC(GPP_A12, NATIVE), // WLAN_WAKEUP#
+	PAD_CFG_NF(GPP_A13, NATIVE, DEEP, NF2), // BODYSAR#
 	_PAD_CFG_STRUCT(GPP_A14, 0x40001300, 0x3c00),
 	PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1),
-	PAD_CFG_NF(GPP_A16, UP_20K, DEEP, NF1),
-	PAD_CFG_NF(GPP_A17, UP_20K, DEEP, NF1),
-	PAD_CFG_NF(GPP_B00, NONE, PWROK, NF1),
-	PAD_CFG_NF(GPP_B01, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPP_A16, UP_20K, DEEP, NF1), // PCH_BT_EN
+	PAD_CFG_NF(GPP_A17, UP_20K, DEEP, NF1), // WIFI_RF_EN
+
+	PAD_CFG_NF(GPP_B00, NONE, PWROK, NF1), // TBT_I2C_SCL
+	PAD_CFG_NF(GPP_B01, NONE, PWROK, NF1), // TBT_I2C_SDA
 	PAD_CFG_GPO(GPP_B02, 1, DEEP),
 	PAD_CFG_GPO(GPP_B03, 1, DEEP),
-	PAD_CFG_GPO(GPP_B04, 1, DEEP),
+	PAD_CFG_GPO(GPP_B04, 1, DEEP), // strap
 	PAD_CFG_GPO(GPP_B05, 1, DEEP),
-	PAD_CFG_GPO(GPP_B06, 0, PLTRST),
+	PAD_CFG_GPO(GPP_B06, 0, PLTRST), // ROM_I2C_EN
 	PAD_CFG_GPO(GPP_B07, 1, DEEP),
 	PAD_CFG_GPO(GPP_B08, 1, DEEP),
-	PAD_CFG_GPO(GPP_B09, 1, PLTRST),
-	PAD_CFG_GPO(GPP_B10, 1, PLTRST),
+	PAD_CFG_GPO(GPP_B09, 1, PLTRST), // M2_SSD1_RST#
+	PAD_CFG_GPO(GPP_B10, 1, PLTRST), // SSD1_PWR_EN
 	PAD_NC(GPP_B11, NONE),
-	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2),
-	PAD_NC(GPP_B15, NONE),
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2), // CPU_HDMI_HPD
+	PAD_NC(GPP_B15, NONE), // USB_OC3#
 	PAD_CFG_GPO(GPP_B16, 1, DEEP),
-	PAD_CFG_GPO(GPP_B17, 1, DEEP),
+	PAD_CFG_GPO(GPP_B17, 1, DEEP), // HDMI_EN
 	PAD_CFG_GPO(GPP_B18, 1, DEEP),
 	PAD_CFG_GPO(GPP_B19, 1, DEEP),
-	PAD_NC(GPP_B20, NONE),
-	PAD_CFG_GPO(GPP_B21, 0, PLTRST),
+	PAD_NC(GPP_B20, NONE), // LTE_RST_N
+	PAD_CFG_GPO(GPP_B21, 0, PLTRST), // DG_FORCE_PWR
 	PAD_CFG_GPO(GPP_B22, 1, DEEP),
-	PAD_CFG_GPO(GPP_B23, 1, DEEP),
+	PAD_CFG_GPO(GPP_B23, 1, DEEP), // strap
 	PAD_CFG_GPO(GPP_B24, 1, DEEP),
 	PAD_CFG_GPO(GPP_B25, 1, DEEP),
+
 	PAD_CFG_NF(GPP_C00, UP_20K, DEEP, NF1),
 	PAD_CFG_NF(GPP_C01, UP_20K, DEEP, NF1),
-	PAD_CFG_GPO(GPP_C02, 1, DEEP),
-	PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1),
-	PAD_CFG_GPO(GPP_C05, 1, DEEP),
+	PAD_CFG_GPO(GPP_C02, 1, DEEP), // strap
+	PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1), // SML0_CLK
+	PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1), // SML0_DATA
+	PAD_CFG_GPO(GPP_C05, 1, DEEP), // strap
 	PAD_NC(GPP_C06, NONE),
 	PAD_NC(GPP_C07, NONE),
 	PAD_CFG_GPO(GPP_C08, 1, DEEP),
 	PAD_CFG_GPO(GPP_C09, 1, DEEP),
 	PAD_CFG_GPO(GPP_C10, 1, DEEP),
 	PAD_CFG_GPO(GPP_C11, 1, DEEP),
-	PAD_CFG_NF(GPP_C12, NONE, PLTRST, NF1),
-	PAD_CFG_NF(GPP_C13, NONE, PLTRST, NF1),
-	PAD_CFG_NF(GPP_C14, NONE, PLTRST, NF1),
-	PAD_CFG_GPO(GPP_C15, 1, DEEP),
-	//TODO PAD_CFG_NF(GPP_C16, NONE, TODO_0xc4000700, NF1),
-	//TODO PAD_CFG_NF(GPP_C17, NONE, TODO_0xc4000700, NF1),
+	PAD_CFG_NF(GPP_C12, NONE, PLTRST, NF1), // CARD_CLKREQ#_N
+	PAD_CFG_NF(GPP_C13, NONE, PLTRST, NF1), // WLAN_CLKREQ#_N
+	PAD_CFG_NF(GPP_C14, NONE, PLTRST, NF1), // 5G_PCIE_CLKREQ#_N
+	PAD_CFG_GPO(GPP_C15, 1, DEEP), // strap
+	//TODO PAD_CFG_NF(GPP_C16, NONE, TODO_0xc4000700, NF1), // TBTA_LSX0_TXD
+	//TODO PAD_CFG_NF(GPP_C17, NONE, TODO_0xc4000700, NF1), // TBTA_LSX0_RXD
 	PAD_CFG_GPO(GPP_C18, 1, DEEP),
 	PAD_CFG_GPO(GPP_C19, 1, DEEP),
 	PAD_CFG_GPO(GPP_C20, 1, DEEP),
 	PAD_CFG_GPO(GPP_C21, 1, DEEP),
-	PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2),
-	PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2),
-	PAD_CFG_GPO(GPP_D00, 1, PLTRST),
+	PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2), // HDMI_CTRLCLK
+	PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2), // HDMI_CTRLDATA
+
+	PAD_CFG_GPO(GPP_D00, 1, PLTRST), // SB_BLON
 	PAD_CFG_GPO(GPP_D01, 1, DEEP),
 	PAD_CFG_GPO(GPP_D02, 1, DEEP),
 	PAD_CFG_GPO(GPP_D03, 1, DEEP),
@@ -82,82 +85,85 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_D07, 1, DEEP),
 	PAD_CFG_GPO(GPP_D08, 1, DEEP),
 	PAD_CFG_GPO(GPP_D09, 1, DEEP),
-	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), // HDA_BITCLK
+	PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1), // HDA_SYNC
+	PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1), // HDA_SDOUT / strap
+	PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1), // HDA_SDIN0
 	PAD_CFG_GPO(GPP_D14, 1, DEEP),
-	PAD_NC(GPP_D15, NONE),
-	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),
+	PAD_NC(GPP_D15, NONE), // CNVI_WAKE#
+	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), // HDA_RST#
 	PAD_CFG_GPO(GPP_D17, 1, DEEP),
-	PAD_CFG_NF(GPP_D18, NONE, PLTRST, NF1),
-	PAD_CFG_GPO(GPP_D19, 1, PLTRST),
+	PAD_CFG_NF(GPP_D18, NONE, PLTRST, NF1), // SSD1_CLKREQ#_N
+	PAD_CFG_GPO(GPP_D19, 1, PLTRST), // SD_PCIE_RST_N
 	PAD_CFG_GPO(GPP_D20, 1, DEEP),
 	PAD_CFG_GPO(GPP_D21, 1, DEEP),
 	PAD_CFG_NF(GPP_D22, NATIVE, DEEP, NF1),
 	PAD_CFG_NF(GPP_D23, NATIVE, DEEP, NF1),
 	PAD_CFG_GPO(GPP_D24, 1, DEEP),
 	PAD_CFG_GPO(GPP_D25, 1, DEEP),
-	_PAD_CFG_STRUCT(GPP_E01, 0x42880100, 0x0000),
-	PAD_NC(GPP_E02, NONE),
+
+	_PAD_CFG_STRUCT(GPP_E01, 0x42880100, 0x0000), // TPM_PIRQ#
+	PAD_NC(GPP_E02, NONE), // VRALERT#
 	PAD_CFG_GPO(GPP_E03, 1, DEEP),
 	PAD_CFG_GPO(GPP_E04, 1, DEEP),
 	PAD_CFG_GPO(GPP_E05, 1, DEEP),
-	PAD_CFG_GPO(GPP_E06, 1, DEEP),
+	PAD_CFG_GPO(GPP_E06, 1, DEEP), // strap
 	PAD_CFG_GPO(GPP_E07, 1, DEEP),
-	PAD_NC(GPP_E08, NONE),
-	PAD_NC(GPP_E09, NONE),
+	PAD_NC(GPP_E08, NONE), // WAKE_ON_WWAN_N
+	PAD_NC(GPP_E09, NONE), // USB_OC0#
 	PAD_CFG_GPO(GPP_E10, 1, DEEP),
-	PAD_CFG_GPI(GPP_E11, NONE, DEEP),
-	_PAD_CFG_STRUCT(GPP_E12, 0x44002300, 0x0000),
-	_PAD_CFG_STRUCT(GPP_E13, 0x44002300, 0x0000),
-	PAD_CFG_GPI(GPP_E14, NONE, DEEP),
-	PAD_CFG_GPI(GPP_E15, NONE, DEEP),
+	PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID1
+	_PAD_CFG_STRUCT(GPP_E12, 0x44002300, 0x0000), // AMP_SMB_CLK
+	_PAD_CFG_STRUCT(GPP_E13, 0x44002300, 0x0000), // AMP_SMB_DATA
+	PAD_CFG_GPI(GPP_E14, NONE, DEEP), // BOARD_ID2
+	PAD_CFG_GPI(GPP_E15, NONE, DEEP), // BOARD_ID3
 	PAD_CFG_GPO(GPP_E16, 1, DEEP),
-	PAD_CFG_GPI(GPP_E17, NONE, DEEP),
+	PAD_CFG_GPI(GPP_E17, NONE, DEEP), // BOARD_ID4
 	PAD_CFG_GPO(GPP_E18, 1, DEEP),
 	PAD_CFG_GPO(GPP_E19, 1, DEEP),
 	PAD_CFG_GPO(GPP_E20, 1, DEEP),
-	PAD_CFG_NF(GPP_E21, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPP_E21, NONE, PWROK, NF1), // TBT_I2C_INT
 	PAD_CFG_GPO(GPP_E22, 1, DEEP),
-	PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_F01, UP_20K, DEEP, NF1),
-	PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_F03, UP_20K, DEEP, NF1),
-	PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3),
-	PAD_CFG_GPO(GPP_F06, 1, DEEP),
+
+	PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1), // CNVI_BRI_DT
+	PAD_CFG_NF(GPP_F01, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
+	PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1), // CNVI_RGI_DT
+	PAD_CFG_NF(GPP_F03, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
+	PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1), // CNVI_RST#
+	PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3), // CNVI_CLKREQ
+	PAD_CFG_GPO(GPP_F06, 1, DEEP), // CNVI_GNSS_PA_BLANKING
 	PAD_CFG_GPO(GPP_F07, 1, DEEP),
 	PAD_CFG_GPO(GPP_F08, 1, DEEP),
-	PAD_CFG_GPI(GPP_F09, NONE, DEEP),
+	PAD_CFG_GPI(GPP_F09, NONE, DEEP), // TPM_DET
 	PAD_CFG_GPO(GPP_F10, 1, DEEP),
 	PAD_CFG_GPO(GPP_F11, 1, DEEP),
-	_PAD_CFG_STRUCT(GPP_F12, 0x44002300, 0x0000),
-	_PAD_CFG_STRUCT(GPP_F13, 0x44002300, 0x0000),
+	_PAD_CFG_STRUCT(GPP_F12, 0x44002300, 0x0000), // I2C_SCL_TP
+	_PAD_CFG_STRUCT(GPP_F13, 0x44002300, 0x0000), // I2C_SDA_TP
 	PAD_CFG_GPO(GPP_F14, 1, DEEP),
 	PAD_CFG_GPO(GPP_F15, 1, DEEP),
-	PAD_CFG_GPO(GPP_F16, 1, PLTRST),
+	PAD_CFG_GPO(GPP_F16, 1, PLTRST), // CCD_WP#
 	PAD_CFG_GPO(GPP_F17, 1, DEEP),
-	_PAD_CFG_STRUCT(GPP_F18, 0x80800100, 0x0000),
-	PAD_CFG_GPO(GPP_F19, 1, DEEP),
+	_PAD_CFG_STRUCT(GPP_F18, 0x80800100, 0x0000), // TP_ATTN#_N
+	PAD_CFG_GPO(GPP_F19, 1, DEEP), // strap
 	PAD_CFG_GPO(GPP_F20, 1, DEEP),
 	PAD_CFG_GPO(GPP_F21, 1, DEEP),
 	PAD_CFG_GPO(GPP_F22, 1, DEEP),
 	PAD_CFG_GPO(GPP_F23, 1, DEEP),
-	PAD_CFG_NF(GPP_H00, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_H01, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_H02, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_H03, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_H04, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_H05, NONE, DEEP, NF1),
+
+	PAD_CFG_NF(GPP_H00, NONE, DEEP, NF1), // strap
+	PAD_CFG_NF(GPP_H01, NONE, DEEP, NF1), // strap
+	PAD_CFG_NF(GPP_H02, NONE, DEEP, NF1), // strap
+	PAD_CFG_NF(GPP_H03, NONE, DEEP, NF1), // PCH_MUTE
+	PAD_CFG_NF(GPP_H04, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
+	PAD_CFG_NF(GPP_H05, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
 	PAD_CFG_NF(GPP_H06, UP_20K, DEEP, NF1),
 	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_H09, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), // UART_RX
+	PAD_CFG_NF(GPP_H09, UP_20K, DEEP, NF1), // UART_TX
 	PAD_CFG_NF(GPP_H10, UP_20K, DEEP, NF1),
 	PAD_CFG_NF(GPP_H11, DN_20K, DEEP, NF1),
 	//TODO: PAD_CFG_NF(GPP_H12, TODO_0x2400, DEEP, NF1),
-	PAD_CFG_NF(GPP_H13, DN_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_H13, DN_20K, DEEP, NF1), // CPU_C10_GATE#
 	PAD_CFG_NF(GPP_H14, NONE, DEEP, NF1),
 	PAD_CFG_GPO(GPP_H15, 1, DEEP),
 	PAD_CFG_GPO(GPP_H16, 1, DEEP),
@@ -165,35 +171,37 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_H18, NONE),
 	_PAD_CFG_STRUCT(GPP_H19, 0x44000601, 0x0000),
 	_PAD_CFG_STRUCT(GPP_H20, 0x44000601, 0x0000),
-	PAD_CFG_GPO(GPP_H21, 1, DEEP),
-	PAD_CFG_GPO(GPP_H22, 1, DEEP),
+	PAD_CFG_GPO(GPP_H21, 1, DEEP), // PCH_I2C_SDA
+	PAD_CFG_GPO(GPP_H22, 1, DEEP), // PCH_I2C_SCL
 	PAD_NC(GPP_H23, NONE),
 	PAD_NC(GPP_H24, NONE),
+
 	PAD_CFG_GPO(GPP_S00, 1, DEEP),
 	PAD_CFG_GPO(GPP_S01, 1, DEEP),
-	PAD_CFG_GPO(GPP_S02, 1, DEEP),
-	PAD_CFG_GPO(GPP_S03, 1, DEEP),
-	PAD_CFG_GPO(GPP_S04, 1, DEEP),
-	PAD_CFG_GPO(GPP_S05, 1, DEEP),
-	PAD_CFG_GPO(GPP_S06, 1, DEEP),
-	PAD_CFG_GPO(GPP_S07, 1, DEEP),
+	PAD_CFG_GPO(GPP_S02, 1, DEEP), // DMIC_CLK
+	PAD_CFG_GPO(GPP_S03, 1, DEEP), // DMIC_DATA
+	PAD_CFG_GPO(GPP_S04, 1, DEEP), // BT_PCMCLK
+	PAD_CFG_GPO(GPP_S05, 1, DEEP), // BT_PCMFRM
+	PAD_CFG_GPO(GPP_S06, 1, DEEP), // BT_PCMOUT
+	PAD_CFG_GPO(GPP_S07, 1, DEEP), // BT_PCMIN
+
 	PAD_CFG_NF(GPP_V00, UP_20K, DEEP, NF1),
-	PAD_CFG_NF(GPP_V01, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(GPP_V02, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(GPP_V03, UP_20K, DEEP, NF1),
-	PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_V07, NONE, DEEP, NF1),
-	PAD_CFG_GPO(GPP_V08, 1, DEEP),
+	PAD_CFG_NF(GPP_V01, NATIVE, DEEP, NF1), // AC_PRESENT
+	PAD_CFG_NF(GPP_V02, NATIVE, DEEP, NF1), // SOC_WAKE#
+	PAD_CFG_NF(GPP_V03, UP_20K, DEEP, NF1), // CPU_PWR_BTN#
+	PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), // SUSB#_PCH
+	PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1), // SUSC#_PCH
+	PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1), // SLP_A#
+	PAD_CFG_NF(GPP_V07, NONE, DEEP, NF1), // SUS_CLK
+	PAD_CFG_GPO(GPP_V08, 1, DEEP), // SLP_WLAN#
 	PAD_CFG_GPO(GPP_V09, 1, DEEP),
 	PAD_CFG_GPO(GPP_V10, 1, DEEP),
 	PAD_CFG_GPO(GPP_V11, 1, DEEP),
-	PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1), // PCH_WAKE#
 	_PAD_CFG_STRUCT(GPP_V13, 0x44000601, 0x0000),
 	_PAD_CFG_STRUCT(GPP_V14, 0x44000601, 0x0000),
 	_PAD_CFG_STRUCT(GPP_V15, 0x44000601, 0x0000),
-	PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1), // VCCST_EN
 	PAD_CFG_GPO(GPP_V17, 1, DEEP),
 };
 

From 75517baac32cf27e709d59ae73fe84458d54d23b Mon Sep 17 00:00:00 2001
From: Tim Crawford <tcrawford@system76.com>
Date: Mon, 23 Mar 2026 10:58:56 -0600
Subject: [PATCH 07/13] mb/system76/ptl: Fix eSPI GPIOs

TODO: Is `IOSTANDBY_IGNORE` needed?

Signed-off-by: Tim Crawford <tcrawford@system76.com>
---
 src/mainboard/system76/ptl/variants/lemp14/gpio.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/mainboard/system76/ptl/variants/lemp14/gpio.c b/src/mainboard/system76/ptl/variants/lemp14/gpio.c
index 843090bd662..7ee01909343 100644
--- a/src/mainboard/system76/ptl/variants/lemp14/gpio.c
+++ b/src/mainboard/system76/ptl/variants/lemp14/gpio.c
@@ -4,13 +4,13 @@
 #include <soc/gpio.h>
 
 static const struct pad_config gpio_table[] = {
-	PAD_CFG_NF(GPP_A00, NONE, DEEP, NF1), // ESPI_IO0_EC
-	PAD_CFG_GPO(GPP_A01, 1, DEEP), // ESPI_IO1_EC
-	PAD_CFG_GPO(GPP_A02, 1, DEEP), // ESPI_IO2_EC
-	PAD_CFG_GPO(GPP_A03, 1, DEEP), // ESPI_IO3_EC
-	PAD_CFG_GPO(GPP_A04, 1, DEEP), // ESPI_CS_EC#
-	PAD_CFG_GPO(GPP_A05, 1, DEEP), // ESPI_CLK_EC
-	PAD_CFG_GPO(GPP_A06, 1, DEEP), // ESPI_RESET#
+	PAD_CFG_NF(GPP_A00, UP_20K, DEEP, NF1), // ESPI_IO0_EC
+	PAD_CFG_NF(GPP_A01, UP_20K, DEEP, NF1), // ESPI_IO1_EC
+	PAD_CFG_NF(GPP_A02, UP_20K, DEEP, NF1), // ESPI_IO2_EC
+	PAD_CFG_NF(GPP_A03, UP_20K, DEEP, NF1), // ESPI_IO3_EC
+	PAD_CFG_NF(GPP_A04, UP_20K, DEEP, NF1), // ESPI_CS_EC#
+	PAD_CFG_NF(GPP_A05, UP_20K, DEEP, NF1), // ESPI_CLK_EC
+	PAD_CFG_NF(GPP_A06, NONE, DEEP, NF1), // ESPI_RESET#
 	PAD_CFG_GPO(GPP_A07, 1, DEEP),
 	PAD_CFG_NF(GPP_A08, NONE, DEEP, NF1), // SD_PWR_EN
 	PAD_CFG_NF(GPP_A09, NONE, DEEP, NF1),

From 3910cbd6b9080d18dab255f281720005fa512d46 Mon Sep 17 00:00:00 2001
From: Tim Crawford <tcrawford@system76.com>
Date: Mon, 23 Mar 2026 12:54:04 -0600
Subject: [PATCH 08/13] mb/system76/ptl: Increase size of SMMSTORE to 512KB

Ref: commit d32a3728465d ("drivers/smmstore: Increase default size of store to 512KB")
Signed-off-by: Tim Crawford <tcrawford@system76.com>
---
 src/mainboard/system76/ptl/variants/lemp14/board.fmd | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/system76/ptl/variants/lemp14/board.fmd b/src/mainboard/system76/ptl/variants/lemp14/board.fmd
index c466748dc44..aec4da22f06 100644
--- a/src/mainboard/system76/ptl/variants/lemp14/board.fmd
+++ b/src/mainboard/system76/ptl/variants/lemp14/board.fmd
@@ -3,7 +3,7 @@ FLASH 32M {
 	SI_ME 9176K
 	SI_BIOS@16M 16M {
 		RW_MRC_CACHE 64K
-		SMMSTORE(PRESERVE) 256K
+		SMMSTORE(PRESERVE) 512K
 		WP_RO {
 			FMAP 4K
 			COREBOOT(CBFS)

From 4c985c1473b9c0bd0f145685b5f15048a932e9d0 Mon Sep 17 00:00:00 2001
From: Tim Crawford <tcrawford@system76.com>
Date: Mon, 23 Mar 2026 14:35:02 -0600
Subject: [PATCH 09/13] mb/system76/ptl: Configure eSPI IO Standby

Change-Id: Ie2222b0c3844b6cdbd4f9c090a8555a20093b6fc
Signed-off-by: Tim Crawford <tcrawford@system76.com>
---
 src/mainboard/system76/ptl/variants/lemp14/gpio.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/mainboard/system76/ptl/variants/lemp14/gpio.c b/src/mainboard/system76/ptl/variants/lemp14/gpio.c
index 7ee01909343..08d63e64f2b 100644
--- a/src/mainboard/system76/ptl/variants/lemp14/gpio.c
+++ b/src/mainboard/system76/ptl/variants/lemp14/gpio.c
@@ -4,13 +4,13 @@
 #include <soc/gpio.h>
 
 static const struct pad_config gpio_table[] = {
-	PAD_CFG_NF(GPP_A00, UP_20K, DEEP, NF1), // ESPI_IO0_EC
-	PAD_CFG_NF(GPP_A01, UP_20K, DEEP, NF1), // ESPI_IO1_EC
-	PAD_CFG_NF(GPP_A02, UP_20K, DEEP, NF1), // ESPI_IO2_EC
-	PAD_CFG_NF(GPP_A03, UP_20K, DEEP, NF1), // ESPI_IO3_EC
-	PAD_CFG_NF(GPP_A04, UP_20K, DEEP, NF1), // ESPI_CS_EC#
-	PAD_CFG_NF(GPP_A05, UP_20K, DEEP, NF1), // ESPI_CLK_EC
-	PAD_CFG_NF(GPP_A06, NONE, DEEP, NF1), // ESPI_RESET#
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A00, UP_20K, DEEP, NF1), // ESPI_IO0_EC
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A01, UP_20K, DEEP, NF1), // ESPI_IO1_EC
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A02, UP_20K, DEEP, NF1), // ESPI_IO2_EC
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A03, UP_20K, DEEP, NF1), // ESPI_IO3_EC
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A04, UP_20K, DEEP, NF1), // ESPI_CS_EC#
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A05, UP_20K, DEEP, NF1), // ESPI_CLK_EC
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A06, NONE, DEEP, NF1), // ESPI_RESET#
 	PAD_CFG_GPO(GPP_A07, 1, DEEP),
 	PAD_CFG_NF(GPP_A08, NONE, DEEP, NF1), // SD_PWR_EN
 	PAD_CFG_NF(GPP_A09, NONE, DEEP, NF1),

From 103c0513cb427734e67af555fd18d571d48e6f3a Mon Sep 17 00:00:00 2001
From: Tim Crawford <tcrawford@system76.com>
Date: Mon, 23 Mar 2026 17:27:44 -0600
Subject: [PATCH 10/13] mb/system76/ptl: Update GPIOs based on schematics

Signed-off-by: Tim Crawford <tcrawford@system76.com>
---
 .../system76/ptl/variants/lemp14/gpio.c       | 256 +++++++++---------
 1 file changed, 127 insertions(+), 129 deletions(-)

diff --git a/src/mainboard/system76/ptl/variants/lemp14/gpio.c b/src/mainboard/system76/ptl/variants/lemp14/gpio.c
index 08d63e64f2b..e8397bd1a0c 100644
--- a/src/mainboard/system76/ptl/variants/lemp14/gpio.c
+++ b/src/mainboard/system76/ptl/variants/lemp14/gpio.c
@@ -11,27 +11,27 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A04, UP_20K, DEEP, NF1), // ESPI_CS_EC#
 	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A05, UP_20K, DEEP, NF1), // ESPI_CLK_EC
 	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A06, NONE, DEEP, NF1), // ESPI_RESET#
-	PAD_CFG_GPO(GPP_A07, 1, DEEP),
+	//PAD_NC(GPP_A07, NONE),
 	PAD_CFG_NF(GPP_A08, NONE, DEEP, NF1), // SD_PWR_EN
-	PAD_CFG_NF(GPP_A09, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_A10, UP_20K, DEEP, NF1),
-	PAD_CFG_NF(GPP_A11, UP_20K, DEEP, NF1), // WLAN_RST#
-	PAD_NC(GPP_A12, NATIVE), // WLAN_WAKEUP#
+	PAD_NC(GPP_A09, NONE),
+	PAD_NC(GPP_A10, NONE),
+	PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), // WLAN_RST#
+	PAD_NC(GPP_A12, NONE), // WLAN_WAKEUP#
 	PAD_CFG_NF(GPP_A13, NATIVE, DEEP, NF2), // BODYSAR#
-	_PAD_CFG_STRUCT(GPP_A14, 0x40001300, 0x3c00),
-	PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1),
+	//PAD_NC(GPP_A14, NONE),
+	PAD_NC(GPP_A15, NONE),
 	PAD_CFG_NF(GPP_A16, UP_20K, DEEP, NF1), // PCH_BT_EN
 	PAD_CFG_NF(GPP_A17, UP_20K, DEEP, NF1), // WIFI_RF_EN
 
-	PAD_CFG_NF(GPP_B00, NONE, PWROK, NF1), // TBT_I2C_SCL
-	PAD_CFG_NF(GPP_B01, NONE, PWROK, NF1), // TBT_I2C_SDA
-	PAD_CFG_GPO(GPP_B02, 1, DEEP),
-	PAD_CFG_GPO(GPP_B03, 1, DEEP),
-	PAD_CFG_GPO(GPP_B04, 1, DEEP), // strap
-	PAD_CFG_GPO(GPP_B05, 1, DEEP),
-	PAD_CFG_GPO(GPP_B06, 0, PLTRST), // ROM_I2C_EN
-	PAD_CFG_GPO(GPP_B07, 1, DEEP),
-	PAD_CFG_GPO(GPP_B08, 1, DEEP),
+	PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1), // TBT_I2C_SCL
+	PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1), // TBT_I2C_SDA
+	PAD_NC(GPP_B02, NONE),
+	PAD_NC(GPP_B03, NONE),
+	PAD_CFG_GPO(GPP_B04, 0, RSMRST), // Flash Descriptor Security Override strap
+	PAD_NC(GPP_B05, NONE),
+	PAD_CFG_GPO(GPP_B06, 0, DEEP), // ROM_I2C_EN
+	PAD_NC(GPP_B07, NONE),
+	PAD_NC(GPP_B08, NONE),
 	PAD_CFG_GPO(GPP_B09, 1, PLTRST), // M2_SSD1_RST#
 	PAD_CFG_GPO(GPP_B10, 1, PLTRST), // SSD1_PWR_EN
 	PAD_NC(GPP_B11, NONE),
@@ -39,170 +39,168 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
 	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2), // CPU_HDMI_HPD
 	PAD_NC(GPP_B15, NONE), // USB_OC3#
-	PAD_CFG_GPO(GPP_B16, 1, DEEP),
+	PAD_NC(GPP_B16, NONE),
 	PAD_CFG_GPO(GPP_B17, 1, DEEP), // HDMI_EN
-	PAD_CFG_GPO(GPP_B18, 1, DEEP),
-	PAD_CFG_GPO(GPP_B19, 1, DEEP),
-	PAD_NC(GPP_B20, NONE), // LTE_RST_N
+	PAD_NC(GPP_B18, NONE),
+	PAD_NC(GPP_B19, NONE),
+	PAD_CFG_GPO(GPP_B20, 1, DEEP), // LTE_RST_N
 	PAD_CFG_GPO(GPP_B21, 0, PLTRST), // DG_FORCE_PWR
-	PAD_CFG_GPO(GPP_B22, 1, DEEP),
-	PAD_CFG_GPO(GPP_B23, 1, DEEP), // strap
-	PAD_CFG_GPO(GPP_B24, 1, DEEP),
-	PAD_CFG_GPO(GPP_B25, 1, DEEP),
+	PAD_NC(GPP_B22, NONE),
+	PAD_CFG_GPO(GPP_B23, 0, PLTRST), // strap
+	PAD_NC(GPP_B24, NONE),
+	PAD_NC(GPP_B25, NONE),
 
-	PAD_CFG_NF(GPP_C00, UP_20K, DEEP, NF1),
-	PAD_CFG_NF(GPP_C01, UP_20K, DEEP, NF1),
-	PAD_CFG_GPO(GPP_C02, 1, DEEP), // strap
+	PAD_NC(GPP_C00, NONE),
+	PAD_NC(GPP_C01, NONE),
+	PAD_CFG_GPO(GPP_C02, 1, PLTRST), // TLS confidentiality strap
 	PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1), // SML0_CLK
 	PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1), // SML0_DATA
-	PAD_CFG_GPO(GPP_C05, 1, DEEP), // strap
+	PAD_CFG_GPO(GPP_C05, 0, PLTRST), // eSPI disable strap
 	PAD_NC(GPP_C06, NONE),
 	PAD_NC(GPP_C07, NONE),
-	PAD_CFG_GPO(GPP_C08, 1, DEEP),
-	PAD_CFG_GPO(GPP_C09, 1, DEEP),
-	PAD_CFG_GPO(GPP_C10, 1, DEEP),
-	PAD_CFG_GPO(GPP_C11, 1, DEEP),
-	PAD_CFG_NF(GPP_C12, NONE, PLTRST, NF1), // CARD_CLKREQ#_N
-	PAD_CFG_NF(GPP_C13, NONE, PLTRST, NF1), // WLAN_CLKREQ#_N
-	PAD_CFG_NF(GPP_C14, NONE, PLTRST, NF1), // 5G_PCIE_CLKREQ#_N
-	PAD_CFG_GPO(GPP_C15, 1, DEEP), // strap
-	//TODO PAD_CFG_NF(GPP_C16, NONE, TODO_0xc4000700, NF1), // TBTA_LSX0_TXD
-	//TODO PAD_CFG_NF(GPP_C17, NONE, TODO_0xc4000700, NF1), // TBTA_LSX0_RXD
-	PAD_CFG_GPO(GPP_C18, 1, DEEP),
-	PAD_CFG_GPO(GPP_C19, 1, DEEP),
-	PAD_CFG_GPO(GPP_C20, 1, DEEP),
-	PAD_CFG_GPO(GPP_C21, 1, DEEP),
+	PAD_NC(GPP_C08, NONE),
+	PAD_NC(GPP_C09, NONE),
+	PAD_NC(GPP_C10, NONE),
+	PAD_NC(GPP_C11, NONE),
+	PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), // CARD_CLKREQ#_N
+	PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), // WLAN_CLKREQ#_N
+	PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), // 5G_PCIE_CLKREQ#_N
+	PAD_NC(GPP_C15, NONE), // Reserved strap
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // TBTA_LSX0_TXD
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // TBTA_LSX0_RXD
+	PAD_NC(GPP_C18, NONE),
+	PAD_NC(GPP_C19, NONE),
+	PAD_NC(GPP_C20, NONE),
+	PAD_NC(GPP_C21, NONE),
 	PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2), // HDMI_CTRLCLK
 	PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2), // HDMI_CTRLDATA
 
 	PAD_CFG_GPO(GPP_D00, 1, PLTRST), // SB_BLON
-	PAD_CFG_GPO(GPP_D01, 1, DEEP),
-	PAD_CFG_GPO(GPP_D02, 1, DEEP),
-	PAD_CFG_GPO(GPP_D03, 1, DEEP),
-	PAD_CFG_GPO(GPP_D04, 1, DEEP),
-	PAD_CFG_GPO(GPP_D05, 1, DEEP),
-	PAD_CFG_GPO(GPP_D06, 1, DEEP),
-	PAD_CFG_GPO(GPP_D07, 1, DEEP),
-	PAD_CFG_GPO(GPP_D08, 1, DEEP),
-	PAD_CFG_GPO(GPP_D09, 1, DEEP),
+	PAD_NC(GPP_D01, NONE),
+	PAD_NC(GPP_D02, NONE),
+	PAD_NC(GPP_D03, NONE),
+	PAD_NC(GPP_D04, NONE),
+	PAD_NC(GPP_D05, NONE),
+	PAD_NC(GPP_D06, NONE),
+	PAD_NC(GPP_D07, NONE),
+	PAD_NC(GPP_D08, NONE),
+	PAD_NC(GPP_D09, NONE),
 	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), // HDA_BITCLK
 	PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1), // HDA_SYNC
 	PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1), // HDA_SDOUT / strap
 	PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1), // HDA_SDIN0
-	PAD_CFG_GPO(GPP_D14, 1, DEEP),
+	PAD_NC(GPP_D14, NONE),
 	PAD_NC(GPP_D15, NONE), // CNVI_WAKE#
 	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), // HDA_RST#
-	PAD_CFG_GPO(GPP_D17, 1, DEEP),
+	PAD_NC(GPP_D17, NONE),
 	PAD_CFG_NF(GPP_D18, NONE, PLTRST, NF1), // SSD1_CLKREQ#_N
 	PAD_CFG_GPO(GPP_D19, 1, PLTRST), // SD_PCIE_RST_N
-	PAD_CFG_GPO(GPP_D20, 1, DEEP),
-	PAD_CFG_GPO(GPP_D21, 1, DEEP),
-	PAD_CFG_NF(GPP_D22, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(GPP_D23, NATIVE, DEEP, NF1),
-	PAD_CFG_GPO(GPP_D24, 1, DEEP),
-	PAD_CFG_GPO(GPP_D25, 1, DEEP),
+	PAD_NC(GPP_D20, NONE),
+	PAD_NC(GPP_D21, NONE),
+	PAD_NC(GPP_D22, NONE),
+	PAD_NC(GPP_D23, NONE),
+	PAD_NC(GPP_D24, NONE),
+	PAD_NC(GPP_D25, NONE),
 
 	_PAD_CFG_STRUCT(GPP_E01, 0x42880100, 0x0000), // TPM_PIRQ#
-	PAD_NC(GPP_E02, NONE), // VRALERT#
-	PAD_CFG_GPO(GPP_E03, 1, DEEP),
-	PAD_CFG_GPO(GPP_E04, 1, DEEP),
-	PAD_CFG_GPO(GPP_E05, 1, DEEP),
-	PAD_CFG_GPO(GPP_E06, 1, DEEP), // strap
-	PAD_CFG_GPO(GPP_E07, 1, DEEP),
+	PAD_CFG_NF(GPP_E02, NONE, DEEP, NF2), // VRALERT#
+	PAD_NC(GPP_E03, NONE),
+	//PAD_NC(GPP_E04, NONE),
+	PAD_NC(GPP_E05, NONE),
+	PAD_CFG_GPO(GPP_E06, 1, PLTRST), // JTAG ODT strap
+	PAD_NC(GPP_E07, NONE),
 	PAD_NC(GPP_E08, NONE), // WAKE_ON_WWAN_N
 	PAD_NC(GPP_E09, NONE), // USB_OC0#
-	PAD_CFG_GPO(GPP_E10, 1, DEEP),
+	PAD_NC(GPP_E10, NONE),
 	PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID1
 	_PAD_CFG_STRUCT(GPP_E12, 0x44002300, 0x0000), // AMP_SMB_CLK
 	_PAD_CFG_STRUCT(GPP_E13, 0x44002300, 0x0000), // AMP_SMB_DATA
 	PAD_CFG_GPI(GPP_E14, NONE, DEEP), // BOARD_ID2
 	PAD_CFG_GPI(GPP_E15, NONE, DEEP), // BOARD_ID3
-	PAD_CFG_GPO(GPP_E16, 1, DEEP),
+	PAD_NC(GPP_E16, NONE),
 	PAD_CFG_GPI(GPP_E17, NONE, DEEP), // BOARD_ID4
-	PAD_CFG_GPO(GPP_E18, 1, DEEP),
-	PAD_CFG_GPO(GPP_E19, 1, DEEP),
-	PAD_CFG_GPO(GPP_E20, 1, DEEP),
+	PAD_NC(GPP_E18, NONE),
+	PAD_NC(GPP_E19, NONE),
+	PAD_NC(GPP_E20, NONE),
 	PAD_CFG_NF(GPP_E21, NONE, PWROK, NF1), // TBT_I2C_INT
-	PAD_CFG_GPO(GPP_E22, 1, DEEP),
+	PAD_NC(GPP_E22, NONE),
 
 	PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1), // CNVI_BRI_DT
 	PAD_CFG_NF(GPP_F01, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
-	PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1), // CNVI_RGI_DT
+	PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1), // CNVI_RGI_DT / M.2 CNVi mode strap
 	PAD_CFG_NF(GPP_F03, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
 	PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1), // CNVI_RST#
 	PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3), // CNVI_CLKREQ
-	PAD_CFG_GPO(GPP_F06, 1, DEEP), // CNVI_GNSS_PA_BLANKING
-	PAD_CFG_GPO(GPP_F07, 1, DEEP),
-	PAD_CFG_GPO(GPP_F08, 1, DEEP),
+	PAD_NC(GPP_F06, NONE), // CNVI_GNSS_PA_BLANKING
+	PAD_NC(GPP_F07, NONE),
+	PAD_NC(GPP_F08, NONE),
 	PAD_CFG_GPI(GPP_F09, NONE, DEEP), // TPM_DET
-	PAD_CFG_GPO(GPP_F10, 1, DEEP),
-	PAD_CFG_GPO(GPP_F11, 1, DEEP),
+	PAD_NC(GPP_F10, NONE),
+	PAD_NC(GPP_F11, NONE),
 	_PAD_CFG_STRUCT(GPP_F12, 0x44002300, 0x0000), // I2C_SCL_TP
 	_PAD_CFG_STRUCT(GPP_F13, 0x44002300, 0x0000), // I2C_SDA_TP
-	PAD_CFG_GPO(GPP_F14, 1, DEEP),
-	PAD_CFG_GPO(GPP_F15, 1, DEEP),
-	PAD_CFG_GPO(GPP_F16, 1, PLTRST), // CCD_WP#
-	PAD_CFG_GPO(GPP_F17, 1, DEEP),
+	PAD_NC(GPP_F14, NONE),
+	PAD_NC(GPP_F15, NONE),
+	PAD_CFG_GPO(GPP_F16, 0, DEEP), // CCD_WP#
+	PAD_NC(GPP_F17, NONE),
 	_PAD_CFG_STRUCT(GPP_F18, 0x80800100, 0x0000), // TP_ATTN#_N
-	PAD_CFG_GPO(GPP_F19, 1, DEEP), // strap
-	PAD_CFG_GPO(GPP_F20, 1, DEEP),
-	PAD_CFG_GPO(GPP_F21, 1, DEEP),
-	PAD_CFG_GPO(GPP_F22, 1, DEEP),
-	PAD_CFG_GPO(GPP_F23, 1, DEEP),
+	PAD_CFG_GPO(GPP_F19, 1, DEEP), // Reserved strap
+	PAD_NC(GPP_F20, NONE),
+	//PAD_NC(GPP_F21, NONE),
+	PAD_NC(GPP_F22, NONE),
+	PAD_NC(GPP_F23, NONE),
 
-	PAD_CFG_NF(GPP_H00, NONE, DEEP, NF1), // strap
-	PAD_CFG_NF(GPP_H01, NONE, DEEP, NF1), // strap
-	PAD_CFG_NF(GPP_H02, NONE, DEEP, NF1), // strap
+	PAD_CFG_GPO(GPP_H00, 0, RSMRST), // MAFS strap
+	PAD_CFG_GPO(GPP_H01, 0, RSMRST), // Flash Descriptor Recovery strap
+	PAD_NC(GPP_H02, NONE), // Reserved strap
 	PAD_CFG_NF(GPP_H03, NONE, DEEP, NF1), // PCH_MUTE
-	PAD_CFG_NF(GPP_H04, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
-	PAD_CFG_NF(GPP_H05, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
-	PAD_CFG_NF(GPP_H06, UP_20K, DEEP, NF1),
-	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H04, NONE, DEEP, NF2), // CNVI_MFUART2_RXD
+	PAD_CFG_NF(GPP_H05, NONE, DEEP, NF2), // CNVI_MFUART2_TXD
+	PAD_NC(GPP_H06, NONE),
+	PAD_NC(GPP_H07, NONE),
 	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), // UART_RX
-	PAD_CFG_NF(GPP_H09, UP_20K, DEEP, NF1), // UART_TX
-	PAD_CFG_NF(GPP_H10, UP_20K, DEEP, NF1),
-	PAD_CFG_NF(GPP_H11, DN_20K, DEEP, NF1),
-	//TODO: PAD_CFG_NF(GPP_H12, TODO_0x2400, DEEP, NF1),
-	PAD_CFG_NF(GPP_H13, DN_20K, DEEP, NF1), // CPU_C10_GATE#
-	PAD_CFG_NF(GPP_H14, NONE, DEEP, NF1),
-	PAD_CFG_GPO(GPP_H15, 1, DEEP),
-	PAD_CFG_GPO(GPP_H16, 1, DEEP),
-	PAD_CFG_GPO(GPP_H17, 1, DEEP),
-	PAD_NC(GPP_H18, NONE),
-	_PAD_CFG_STRUCT(GPP_H19, 0x44000601, 0x0000),
-	_PAD_CFG_STRUCT(GPP_H20, 0x44000601, 0x0000),
-	PAD_CFG_GPO(GPP_H21, 1, DEEP), // PCH_I2C_SDA
-	PAD_CFG_GPO(GPP_H22, 1, DEEP), // PCH_I2C_SCL
-	PAD_NC(GPP_H23, NONE),
-	PAD_NC(GPP_H24, NONE),
+	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), // UART_TX
+	PAD_NC(GPP_H10, NONE),
+	PAD_NC(GPP_H11, NONE),
+	//PAD_CFG_NF(GPP_H12, NONE),
+	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), // CPU_C10_GATE#
+	PAD_NC(GPP_H14, NONE),
+	PAD_NC(GPP_H15, NONE),
+	PAD_NC(GPP_H16, NONE),
+	PAD_NC(GPP_H17, NONE),
+	//PAD_NC(GPP_H18, NONE),
+	PAD_NC(GPP_H19, NONE),
+	PAD_NC(GPP_H20, NONE),
+	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), // PCH_I2C_SDA
+	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), // PCH_I2C_SCL
 
-	PAD_CFG_GPO(GPP_S00, 1, DEEP),
-	PAD_CFG_GPO(GPP_S01, 1, DEEP),
-	PAD_CFG_GPO(GPP_S02, 1, DEEP), // DMIC_CLK
-	PAD_CFG_GPO(GPP_S03, 1, DEEP), // DMIC_DATA
-	PAD_CFG_GPO(GPP_S04, 1, DEEP), // BT_PCMCLK
-	PAD_CFG_GPO(GPP_S05, 1, DEEP), // BT_PCMFRM
-	PAD_CFG_GPO(GPP_S06, 1, DEEP), // BT_PCMOUT
-	PAD_CFG_GPO(GPP_S07, 1, DEEP), // BT_PCMIN
+	PAD_NC(GPP_S00, NONE),
+	PAD_NC(GPP_S01, NONE),
+	PAD_NC(GPP_S02, NONE), // DMIC_CLK
+	PAD_NC(GPP_S03, NONE), // DMIC_DATA
+	PAD_NC(GPP_S04, NONE), // BT_PCMCLK
+	PAD_NC(GPP_S05, NONE), // BT_PCMFRM
+	PAD_NC(GPP_S06, NONE), // BT_PCMOUT
+	PAD_NC(GPP_S07, NONE), // BT_PCMIN
 
-	PAD_CFG_NF(GPP_V00, UP_20K, DEEP, NF1),
-	PAD_CFG_NF(GPP_V01, NATIVE, DEEP, NF1), // AC_PRESENT
-	PAD_CFG_NF(GPP_V02, NATIVE, DEEP, NF1), // SOC_WAKE#
-	PAD_CFG_NF(GPP_V03, UP_20K, DEEP, NF1), // CPU_PWR_BTN#
+	PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1), // PM_BATLOW#
+	PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1), // AC_PRESENT
+	PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1), // SOC_WAKE#
+	PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1), // CPU_PWR_BTN#
 	PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), // SUSB#_PCH
 	PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1), // SUSC#_PCH
 	PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1), // SLP_A#
 	PAD_CFG_NF(GPP_V07, NONE, DEEP, NF1), // SUS_CLK
-	PAD_CFG_GPO(GPP_V08, 1, DEEP), // SLP_WLAN#
-	PAD_CFG_GPO(GPP_V09, 1, DEEP),
-	PAD_CFG_GPO(GPP_V10, 1, DEEP),
-	PAD_CFG_GPO(GPP_V11, 1, DEEP),
+	PAD_NC(GPP_V08, NONE), // SLP_WLAN#
+	PAD_NC(GPP_V09, NONE),
+	PAD_NC(GPP_V10, NONE),
+	PAD_NC(GPP_V11, NONE),
 	PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1), // PCH_WAKE#
-	_PAD_CFG_STRUCT(GPP_V13, 0x44000601, 0x0000),
-	_PAD_CFG_STRUCT(GPP_V14, 0x44000601, 0x0000),
-	_PAD_CFG_STRUCT(GPP_V15, 0x44000601, 0x0000),
+	//PAD_NC(GPP_V13, NONE),
+	//PAD_NC(GPP_V14, NONE),
+	//PAD_NC(GPP_V15, NONE),
 	PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1), // VCCST_EN
-	PAD_CFG_GPO(GPP_V17, 1, DEEP),
+	PAD_NC(GPP_V17, NONE),
 };
 
 void mainboard_configure_gpios(void)

From 924217625eb1dbedbcb5c4f3da1165d9f27efa6a Mon Sep 17 00:00:00 2001
From: Tim Crawford <tcrawford@system76.com>
Date: Tue, 24 Mar 2026 13:44:14 -0600
Subject: [PATCH 11/13] mb/system76/ptl: Use new verb table implementation

Change-Id: Ie29b9a0d30a3be317086739035a9cacade3e606c
Signed-off-by: Tim Crawford <tcrawford@system76.com>
---
 src/mainboard/system76/ptl/Kconfig             |  1 -
 .../system76/ptl/variants/lemp14/hda_verb.c    | 18 ++++++++++++------
 2 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/src/mainboard/system76/ptl/Kconfig b/src/mainboard/system76/ptl/Kconfig
index c8970a51310..ea890cbfb88 100644
--- a/src/mainboard/system76/ptl/Kconfig
+++ b/src/mainboard/system76/ptl/Kconfig
@@ -2,7 +2,6 @@
 
 config BOARD_SYSTEM76_PTL_COMMON
 	def_bool n
-	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_32768
 	select DRIVERS_GENERIC_BAYHUB_LV2
 	select DRIVERS_GENERIC_CBFS_SERIAL
diff --git a/src/mainboard/system76/ptl/variants/lemp14/hda_verb.c b/src/mainboard/system76/ptl/variants/lemp14/hda_verb.c
index 004c6fc6851..a6c6ebc04da 100644
--- a/src/mainboard/system76/ptl/variants/lemp14/hda_verb.c
+++ b/src/mainboard/system76/ptl/variants/lemp14/hda_verb.c
@@ -2,12 +2,7 @@
 
 #include <device/azalia_device.h>
 
-const u32 cim_verb_data[] = {
-	/* Realtek, ALC245 */
-	0x10ec0245, /* Vendor ID */
-	0x15582a00, /* Subsystem ID */
-	34, /* Number of entries */
-
+static const u32 realtek_alc245_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x15582a00),
 	AZALIA_RESET(1),
 	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
@@ -48,4 +43,15 @@ const u32 cim_verb_data[] = {
 
 const u32 pc_beep_verbs[] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name = "Realtek ALC245",
+		.vendor_id = 0x10ec0245,
+		.subsystem_id = 0x15582a00,
+		.address = 0,
+		.verbs = realtek_alc245_verbs,
+		.verb_count = ARRAY_SIZE(realtek_alc245_verbs),
+	}
+};
+
 AZALIA_ARRAY_SIZES;

From 4a42de348f6a6bbb305e1d9c5205d6e71f1ecbe1 Mon Sep 17 00:00:00 2001
From: Tim Crawford <tcrawford@system76.com>
Date: Thu, 26 Mar 2026 15:40:54 -0600
Subject: [PATCH 12/13] mb/system76/ptl: Use DRIVERS_GFX_GENERIC

Use instead of GMA_DEFAULT_PANEL(0), and move to variant override.

Change-Id: Iab1a54aee0d3fa0853c208902ddd8f23e9e1974d
Signed-off-by: Tim Crawford <tcrawford@system76.com>
---
 src/mainboard/system76/ptl/Kconfig            |  1 +
 src/mainboard/system76/ptl/devicetree.cb      | 10 ---------
 .../ptl/variants/lemp14/overridetree.cb       | 22 +++++++++++++++++++
 3 files changed, 23 insertions(+), 10 deletions(-)

diff --git a/src/mainboard/system76/ptl/Kconfig b/src/mainboard/system76/ptl/Kconfig
index ea890cbfb88..cc6de79460b 100644
--- a/src/mainboard/system76/ptl/Kconfig
+++ b/src/mainboard/system76/ptl/Kconfig
@@ -6,6 +6,7 @@ config BOARD_SYSTEM76_PTL_COMMON
 	select DRIVERS_GENERIC_BAYHUB_LV2
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_GENERIC_CBFS_UUID
+	select DRIVERS_GFX_GENERIC
 	select DRIVERS_I2C_HID
 	select EC_SYSTEM76_EC
 	select EC_SYSTEM76_EC_LOCKDOWN
diff --git a/src/mainboard/system76/ptl/devicetree.cb b/src/mainboard/system76/ptl/devicetree.cb
index 2c5189ca923..08d6443614f 100644
--- a/src/mainboard/system76/ptl/devicetree.cb
+++ b/src/mainboard/system76/ptl/devicetree.cb
@@ -20,16 +20,6 @@ chip soc/intel/pantherlake
 
 	device domain 0 on
 		device ref system_agent on end
-		device ref igpu on
-			# DDIA is eDP, TCP3 is HDMI
-			register "ddi_port_A_config" = "1"
-			register "ddi_ports_config" = "{
-				[DDI_PORT_A] = DDI_ENABLE_HPD,
-				[DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
-			}"
-
-			#TODO: not in pantherlake chip: register "gfx" = "GMA_DEFAULT_PANEL(0)"
-		end
 		device ref npu on end
 		device ref pmc_shared_sram on end
 		device ref cnvi_wifi on
diff --git a/src/mainboard/system76/ptl/variants/lemp14/overridetree.cb b/src/mainboard/system76/ptl/variants/lemp14/overridetree.cb
index 3193b169a71..4869203edb5 100644
--- a/src/mainboard/system76/ptl/variants/lemp14/overridetree.cb
+++ b/src/mainboard/system76/ptl/variants/lemp14/overridetree.cb
@@ -10,6 +10,28 @@ chip soc/intel/pantherlake
 	device domain 0 on
 		subsystemid 0x1558 0x2a00 inherit
 
+		device ref igpu on
+			# DDIA is eDP, TCP3 is HDMI
+			register "ddi_port_A_config" = "1"
+			register "ddi_ports_config" = "{
+				[DDI_PORT_A] = DDI_ENABLE_HPD,
+				[DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+			}"
+
+			chip drivers/gfx/generic
+				register "device_count" = "3"
+				# DDIA: eDP
+				register "device[0].name" = ""LCD0""
+				register "device[0].type" = "panel"
+				# TCP0: TBT
+				register "device[1].name" = ""DD01""
+				register "device[1].use_pld" = "true"
+				register "device[1].pld" = "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(1, 1))"
+				# TCP3: HDMI
+				register "device[2].name" = ""DD02""
+				device generic 0 on end
+			end
+		end
 		device ref tbt_pcie_rp0 on end
 		device ref tcss_xhci on
 			register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"

From 3ed118279647a4ab5eaaa262bdb3f66e7db089bc Mon Sep 17 00:00:00 2001
From: Tim Crawford <tcrawford@system76.com>
Date: Thu, 26 Mar 2026 15:46:03 -0600
Subject: [PATCH 13/13] mb/system76/ptl: Remove dt entries set by chipset

These devices are already enabled by the chipset devicetree, so remove
the overrides. The only change is P2SB from "on" to "hidden".

Change-Id: I4e3f103576bf9b9be37b4909f665f49855d3d21b
Signed-off-by: Tim Crawford <tcrawford@system76.com>
---
 src/mainboard/system76/ptl/devicetree.cb | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/src/mainboard/system76/ptl/devicetree.cb b/src/mainboard/system76/ptl/devicetree.cb
index 08d6443614f..d44bde71f39 100644
--- a/src/mainboard/system76/ptl/devicetree.cb
+++ b/src/mainboard/system76/ptl/devicetree.cb
@@ -19,7 +19,6 @@ chip soc/intel/pantherlake
 	device cpu_cluster 0 on end
 
 	device domain 0 on
-		device ref system_agent on end
 		device ref npu on end
 		device ref pmc_shared_sram on end
 		device ref cnvi_wifi on
@@ -31,8 +30,6 @@ chip soc/intel/pantherlake
 				device generic 0 on end
 			end
 		end
-
-		device ref heci1 on end
 		device ref soc_espi on
 			register "gen1_dec" = "0x00040069" # EC PM channel
 			register "gen2_dec" = "0x00fc0e01" # AP/EC command
@@ -41,7 +38,6 @@ chip soc/intel/pantherlake
 				device pnp 0c31.0 on end
 			end
 		end
-		device ref p2sb on end
 		device ref hda on
 			register "pch_hda_audio_link_hda_enable" = "1"
 			register "pch_hda_sdi_enable[0]" = "true"
@@ -50,6 +46,5 @@ chip soc/intel/pantherlake
 			register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
 		end
 		device ref smbus on end
-		device ref fast_spi on end
 	end
 end