Kernel itself is theoretically multicore-aware. There is an option to turn SMP support on and much of the kernel should, at least theoretically, be SMP capable.
The thread switching logic uses temporary storage used to plan the thread switch which only has one instance. This breaks SMP support in the kernel.
Kernel itself is theoretically multicore-aware. There is an option to turn SMP support on and much of the kernel should, at least theoretically, be SMP capable.
The thread switching logic uses temporary storage used to plan the thread switch which only has one instance. This breaks SMP support in the kernel.