diff --git a/Makefile b/Makefile
index 8fd80469..d89861c3 100644
--- a/Makefile
+++ b/Makefile
@@ -11,7 +11,7 @@ PATH := ${PATH}:/home/tim/.local/share/gem/ruby/3.2.0/bin
.DEFAULT_GOAL := help
# Phony targets
-.PHONY: help build serve clean install update verify dev production test
+.PHONY: help build serve clean install update verify dev production test prepimg
# Help target - shows available commands
help:
@@ -37,7 +37,7 @@ serve:
@echo "Starting Jekyll server..."
@echo "Site will be available at http://localhost:4000"
@echo "Press Ctrl+C to stop"
- @$(JEKYLL) serve --watch --incremental
+ @$(JEKYLL) serve --watch --incremental --future
# Alias for serve - development mode
dev: serve
@@ -107,4 +107,9 @@ test: build
@echo "✅ All tests passed"
# Quick build and serve (builds first, then serves)
-quick: build serve
\ No newline at end of file
+quick: build serve
+
+# Prepare image for website by stripping EXIF data and compressing it
+prepimg:
+ -exif --remove $(img) -o $(img)
+ convert -quality 90% $(img) $(img)
\ No newline at end of file
diff --git a/_authors/andrew-wingate.md b/_authors/andrew-wingate.md
new file mode 100644
index 00000000..bbd30672
--- /dev/null
+++ b/_authors/andrew-wingate.md
@@ -0,0 +1,10 @@
+---
+layout: author_page
+title: "Andrew Wingate"
+sub_title: "Guest Author"
+# avatar: "assets/images/people/andrew-wingate.jpg"
+social_accounts:
+ - icon: "jam jam-world"
+ url: "https://www.crowdsupply.com/evezor-inc"
+---
+**Andrew Wingate** is the founder of [Evezor Inc](https://www.crowdsupply.com/evezor-inc) and an active contributor to the [wafer.space](https://wafer.space) community. He has been instrumental in developing the chip-on-board (COB) packaging strategy that makes working with custom silicon accessible without specialised equipment.
diff --git a/_authors/hirosh-dabui.md b/_authors/hirosh-dabui.md
new file mode 100644
index 00000000..4187f35b
--- /dev/null
+++ b/_authors/hirosh-dabui.md
@@ -0,0 +1,10 @@
+---
+layout: author_page
+title: "Hirosh Dabui"
+sub_title: "Guest Author"
+avatar: "assets/images/people/hirosh-dabui.jpg"
+social_accounts:
+ - icon: "jam jam-github"
+ url: "https://github.com/splinedrive"
+---
+**Hirosh Dabui** is the creator of [KianV](https://github.com/splinedrive/kianRiscV), a custom RISC-V SoC capable of running Linux on open-source silicon. His work on the GF180MCU Run 1 demonstrates what is possible with fully open ASIC design flows, from RTL to packaged chips.
diff --git a/_includes/image.html b/_includes/image.html
new file mode 100644
index 00000000..f31d0b2f
--- /dev/null
+++ b/_includes/image.html
@@ -0,0 +1,11 @@
+
+ {% include image.html file="/assets/images/logo.webp" %}
+
Placeholder video box
+
+
+{% endif %}
\ No newline at end of file
diff --git a/_posts/2025-04-19-website.md b/_posts/2025-04-19-website.md
index 97037d30..6221b95b 100644
--- a/_posts/2025-04-19-website.md
+++ b/_posts/2025-04-19-website.md
@@ -2,16 +2,14 @@
layout: posts/post-boxed
title: "New wafer.space website"
date: 2025-04-19 04:00:00 +0000
-categories: [places]
-tags: [travel]
+excerpt: "The new wafer.space website has launched, bringing budget silicon manufacturing information and resources together in one place."
+categories: [news]
+tags: [wafer-space, website]
author: "Tim 'mithro' Ansell"
-# post_image: "/assets/images/art/tb1.webp"
+post_image: "/assets/images/news/gf180mcu-gelpack-dice.jpg"
badge_color: "bg-purple"
-slider_post: true
+slider_post: false
trending: false
-#meta_title: "The Best Moments in Venice"
-#meta_description: |
-# Snowlake Jekyll Theme is a perfectly crafted fast loading and SEO-friendly static site generator theme
sidebar: true
permalink: "/news/website"
---
diff --git a/_posts/2025-10-02-gf180mcu-run1-live.md b/_posts/2025-10-02-gf180mcu-run1-live.md
new file mode 100644
index 00000000..fcd659fe
--- /dev/null
+++ b/_posts/2025-10-02-gf180mcu-run1-live.md
@@ -0,0 +1,46 @@
+---
+layout: posts/post-boxed
+title: "GF180MCU Run 1 is Live!"
+date: 2025-10-02 12:00:00 +0000
+excerpt: "The wafer.space GF180MCU Run 1 campaign is live on Crowd Supply! $7k gets you 1,000 dies from GlobalFoundries' GF180MCU process."
+categories: [news]
+tags: [gf180mcu, run1, crowd-supply]
+author: "Tim 'mithro' Ansell"
+post_image: "/assets/images/news/gf180mcu-gelpack-dice.jpg"
+badge_color: "bg-purple"
+slider_post: false
+trending: false
+sidebar: true
+permalink: "/news/gf180mcu-run1-live"
+external_url: "https://www.crowdsupply.com/wafer-space/gf180mcu-run-1/updates/we-re-live"
+---
+
+Hey folks,
+
+The [wafer.space GF180MCU Run 1 campaign](https://www.crowdsupply.com/wafer-space/gf180mcu-run-1) just went live on Crowd Supply!
+
+For those who haven't been following along: [wafer.space](https://wafer.space) brings the [OSH Park](https://oshpark.com) model to silicon. $7k gets you 1,000 dies. That's $7 per chip from GlobalFoundries' [GF180MCU](https://gf180mcu-pdk.readthedocs.io/) process. Real production quantities, not just a handful of prototypes.
+
+Efabless shutting down earlier this year left the open silicon community without a clear path to fabrication. I started wafer.space to rebuild that infrastructure with transparent pricing, predictable timelines, and no gatekeeping - and it's even more affordable now!
+
+## [The timeline](https://www.crowdsupply.com/wafer-space/gf180mcu-run-1#schedule)
+
+- **November 28**: Last day to buy a slot
+- **December 3**: GDS submission deadline
+- **March 15, 2026**: Target ship date for dies to customers
+
+## What you're getting
+
+20mm² on [GF180MCU](https://gf180mcu-pdk.readthedocs.io/), replicated 1,000 times. This is the same mature 180nm mixed-signal process used for tons of production chips and the two [Google open MPW runs](https://developers.google.com/silicon). Five metal layers, MIM caps, poly resistors - all the basics you need for mixed-signal designs, MCUs, sensor interfaces, whatever.
+
+## Get involved
+
+Jump on our [Discord](https://discord.gg/43y2t53jpE) or [Matrix](https://matrix.to/#/#gf180mcu:fossi-chat.org) if you need help with pad rings, DRC issues, or just want to see what others are building.
+
+Subscribe for future updates including reference designs, highlights of projects being built on GF180MCU, interviews with community members, and technical deep-dives into how things work behind the scenes.
+
+This is about enabling open, community-driven silicon manufacturing to grow and expand. Let's make it happen.
+
+-Tim 'mithro' Ansell
+
+P.S. I was on [The Teardown Sessions](https://www.crowdsupply.com/crowd-supply/the-teardown-sessions) earlier today discussing wafer.space and open silicon - you can watch the recording at [http://youtu.be/tEOmnN8IAjs](http://youtu.be/tEOmnN8IAjs).
diff --git a/_posts/2025-10-23-librelane-template.md b/_posts/2025-10-23-librelane-template.md
new file mode 100644
index 00000000..f52cc35e
--- /dev/null
+++ b/_posts/2025-10-23-librelane-template.md
@@ -0,0 +1,177 @@
+---
+layout: "posts/post-boxed"
+title: "Easier Design Flow: LibreLane & the gf180mcu Project Template"
+date: "2025-10-23 12:00:00 +0000"
+excerpt: "Get started faster with the LibreLane gf180mcu template: ready-to-use tooling so you can focus on what your chip does, not build infrastructure."
+categories: [news]
+tags: [gf180mcu, run1, librelane, tooling]
+author: "Tim 'mithro' Ansell"
+badge_color: "bg-purple"
+slider_post: false
+trending: false
+sidebar: true
+permalink: "/news/librelane-template"
+post_image: "/assets/images/news/librelane-template/librelane-step1-design.svg"
+external_url: "https://www.crowdsupply.com/wafer-space/gf180mcu-run-1/updates/librelane-template"
+galleries:
+ librelane_steps:
+ caption: "Simple LibreLane Workflow: Design, Configure, Run, GDS"
+ images:
+ - img: "/assets/images/news/librelane-template/librelane-step1-design.svg"
+ alt: "LibreLane Step 1: Design your chip in Verilog"
+ - img: "/assets/images/news/librelane-template/librelane-step2-config.svg"
+ alt: "LibreLane Step 2: Configure the flow"
+ - img: "/assets/images/news/librelane-template/librelane-step3-run.svg"
+ alt: "LibreLane Step 3: Run the automated flow"
+ - img: "/assets/images/news/librelane-template/librelane-step4-gds.svg"
+ alt: "LibreLane Step 4: Get your GDS output"
+---
+
+Hey everyone,
+
+If you've been following open silicon over the past few years, you know the story: Google's [open PDK program](https://developers.google.com/silicon) changed everything, but when [Efabless](https://efabless.com/) shut down earlier this year, a lot of infrastructure disappeared. That's part of why [wafer.space](https://wafer.space/) exists - to rebuild accessible fabrication services.
+
+But fabrication is only half the equation. You also need tools to actually design your chip. That's where **[LibreLane](https://librelane.rtfd.io/)** comes in.
+
+Last month at [ORConf 2025](https://orconf.org/) in Valencia, Mohamed Gaber and Leo Moser presented LibreLane - the next-generation design flow for open silicon. And there's now a ready-to-use [gf180mcu project template](https://github.com/wafer-space/gf180mcu-project-template) that makes starting your wafer.space design even easier.
+
+{% include post-gallery.html gallery="librelane_steps" %}
+
+
+## What is LibreLane?
+
+LibreLane is a ground-up rewrite of [OpenLane](https://github.com/The-OpenROAD-Project/OpenLane) - the tool that made hundreds of open-source tapeouts possible through Google's MPW shuttles and Efabless programs. Originally developed as "OpenLane 2" at Efabless, it's now community-driven under the [FOSSi Foundation](https://fossi-foundation.org/) after being officially released in July 2025.
+
+If you used OpenLane 1, you know it works: you give it a Verilog file and a config, run one command, and get GDS ready for fabrication. LibreLane keeps that simplicity while fixing the pain points.
+
+### Why the Rewrite?
+
+OpenLane 1 was built under tight deadlines to enable the first Google MPW shuttles. It worked amazingly well for that goal, but had some limitations:
+
+- Written in Tcl, which made debugging and extending difficult
+- Hard to run individual steps or insert custom tools
+- No standard way to report design metrics
+- Difficult to integrate with other workflows
+
+LibreLane addresses all of this while maintaining backwards compatibility - your existing OpenLane 1 configs work with LibreLane.
+
+## What Makes LibreLane Better?
+
+- 🐍 **Python-Based Infrastructure**: Modern Python instead of Tcl means better tooling, clearer code, and a real API if you need programmatic control. No more fighting with "stringly-typed" scripts.
+
+- 🔧 **Modular Architecture**: Run individual steps (synthesis, placement, routing) independently. Insert custom tools into the flow. Debug specific stages without rerunning everything. The flow is a pipeline you can actually customize.
+
+- 📊 **Clear Error Reporting**: Standardized metrics and status reporting at every step. When something fails, you know exactly where and why.
+
+- 🎯 **Automated Padframe Generation**: LibreLane handles IO pad insertion and configuration automatically. This is huge - pad ring creation used to be one of the most error-prone manual steps. Now it just works.
+
+- 🌍 **Multi-PDK Support**: The same design can target different process design kits. [gf180mcu](https://gf180mcu-pdk.readthedocs.io/) is fully supported on the main branch, as is [sky130](https://skywater-pdk.readthedocs.io/), while [ihp-sg13g2](https://github.com/IHP-GmbH/IHP-Open-PDK) is supported in the dev branch. Write once, fabricate anywhere.
+
+- ↔ **Backwards Compatible**: Existing OpenLane 1 configurations work with LibreLane. Easy migration path if you've used OpenLane before.
+
+## Real-World Adoption
+
+LibreLane isn't experimental - it's already in production use:
+
+- **[Tiny Tapeout](https://tinytapeout.com/)** has adopted LibreLane for their automated tapeout service
+- **[ChipFoundry](https://chipfoundry.com/)** is using it for their fab pooling platform
+- **[wafer.space](https://wafer.space/)** uses it for their gf180mcu project template
+
+The shift from OpenLane 1 to LibreLane mirrors what happened in the fabrication world: when Efabless shut down, the community rebuilt better infrastructure. wafer.space rebuilt affordable fabrication access. LibreLane rebuilt the design flow. Both are about making open silicon sustainable.
+
+## The gf180mcu Project Template
+
+To make getting started even easier, there's now a [project template](https://github.com/wafer-space/gf180mcu-project-template) specifically configured for wafer.space designs targetting the gf180mcuD PDK variant.
+
+This template gives you a working starting point with everything included:
+
+- **LibreLane configuration** pre-configured for gf180mcuD and wafer.space requirements
+- **[Nix](https://nixos.org/)-based development environment** - `nix-shell` and you're ready to go, no manual tool installation
+- **[cocotb](https://www.cocotb.org/) testbench framework** - Python-based verification for your design
+- **Complete workflow** - from RTL to GDS, including LVS, DRC and gate-level simulation
+- **Example counter design** - shows the whole flow working
+
+### Getting Started
+
+```bash
+# Clone the template
+git clone https://github.com/wafer-space/gf180mcu-project-template
+cd gf180mcu-project-template
+
+# Set up environment (installs everything automatically)
+nix-shell
+
+# Add your design to src/
+# Update librelane/config.yaml with your design parameters
+
+# Run the flow
+make librelane
+
+# View the results
+# Opens in OpenROAD GUI or KLayout
+make librelane-openroad
+make librelane-klayout
+```
+
+That's it. Five steps from empty directory to GDS output.
+
+Everything is set up to work together. You focus on your design, the template handles the infrastructure.
+
+## Watch the ORConf Talk
+
+Want to see LibreLane in action? The full ORConf 2025 presentation by Mohamed Gaber and Leo Moser is on YouTube:
+
+**[LibreLane - ORConf 2025](https://youtu.be/GAEWpbXhhdg)**
+
+The talk covers:
+- Technical architecture and design decisions
+- Live demos of the flow
+- Advanced use cases and customization
+- Future development roadmap
+- Q&A with the community
+
+It's worth watching if you want to understand the full capabilities beyond just running `make librelane`.
+
+## Important Notes
+
+**This is a work in progress.** LibreLane and the template are actively developed and improving. If you use them:
+
+- Stay up to date with the latest changes
+- Report issues you encounter
+- Contribute improvements if you can
+- Join the community chat for help
+
+**The template is an example to help you get started**, not a mandatory requirement. You can use LibreLane directly, adapt the template to your needs, or build your own workflow entirely. It's there to make your life easier, not to constrain how you work.
+
+**Community support is available** through the [FOSSi Foundation chat](https://fossi-chat.org/) and the wafer.space [Discord](https://discord.gg/43y2t53jpE) / [Matrix](https://matrix.to/#/#gf180mcu:fossi-chat.org) channels. LibreLane has active developers and users who can help.
+
+## Resources
+
+**LibreLane**:
+- Documentation: [librelane.rtfd.io](https://librelane.rtfd.io/)
+- Announcement: [FOSSi Foundation Blog](https://fossi-foundation.org/blog/2025-08-17-librelane)
+- ORConf Talk: [YouTube](https://youtu.be/GAEWpbXhhdg)
+
+**gf180mcu Project Template**:
+- Repository: [github.com/wafer-space/gf180mcu-project-template](https://github.com/wafer-space/gf180mcu-project-template)
+- README with detailed instructions
+- Example designs showing best practices
+
+**Community**:
+- FOSSi Foundation: [fossi-chat.org](https://fossi-chat.org/)
+- wafer.space Discord: [discord.gg/43y2t53jpE](https://discord.gg/43y2t53jpE)
+- wafer.space Matrix: [#gf180mcu:fossi-chat.org](https://matrix.to/#/#gf180mcu:fossi-chat.org)
+
+## Why This Matters
+
+Open silicon has come a long way in just a few years. We went from "you need millions of dollars and proprietary tools" to "here's an affordable MPW run and free, open-source tools."
+
+But accessible doesn't mean easy. Chip design is inherently complex. Projects like LibreLane and templates like this one are about removing the incidental complexity - the tool installation headaches, the configuration mysteries, the "why doesn't this work" debugging sessions.
+
+Your time should go into designing your chip, not fighting your tools.
+
+LibreLane handles the flow. The template handles the setup. You handle the innovation.
+
+Whether you're targeting the December 3rd deadline or planning for a future run, these tools are here to help you go from idea to silicon faster and with less friction.
+
+\- Tim 'mithro' Ansell
\ No newline at end of file
diff --git a/_posts/2025-10-27-getting-help.md b/_posts/2025-10-27-getting-help.md
new file mode 100644
index 00000000..ba14ed77
--- /dev/null
+++ b/_posts/2025-10-27-getting-help.md
@@ -0,0 +1,153 @@
+---
+layout: "posts/post-boxed"
+title: "Professional Design Support: Your Options for GF180MCU Success"
+date: "2025-10-27 12:00:00 +0000"
+excerpt: "Professional paid engineering services are available if you want to accelerate your timeline, get expert review, or have someone handle parts (or all) of your design."
+categories: [news]
+tags: [gf180mcu, run1, design-help]
+author: "Tim 'mithro' Ansell"
+badge_color: "bg-purple"
+slider_post: false
+trending: false
+sidebar: true
+permalink: "/news/getting-help"
+post_image: "/assets/images/news/getting-help/timeline.svg"
+external_url: "https://www.crowdsupply.com/wafer-space/gf180mcu-run-1/updates/getting-help"
+galleries:
+ support_spectrum:
+ caption: "Professional support options: independent, hybrid, and full-service"
+ images:
+ - img: "/assets/images/news/getting-help/support-spectrum-independent.svg"
+ alt: "Independent design with community support"
+ - img: "/assets/images/news/getting-help/support-spectrum-hybrid.svg"
+ alt: "Hybrid approach with selective expert help"
+ - img: "/assets/images/news/getting-help/support-spectrum-fullservice.svg"
+ alt: "Full-service professional design support"
+---
+
+Hey everyone,
+
+With the **December 3rd GDS submission deadline** getting closer, I wanted to talk about something that might be on your mind: completing your design on time.
+
+Whether you've already [reserved a slot](https://buy.wafer.space/) or you're still on the fence because of timeline concerns, this update is for you. The short version: you have options. Professional paid engineering services are available if you want to accelerate your timeline, get expert review, or have someone handle parts (or all) of your design.
+
+{% include image.html file="/assets/images/news/getting-help/timeline.svg" description="Run 1 timeline" %}
+
+## Two Important Things Up Front
+
+**First**: Professional services are completely optional. You can absolutely complete your GF180MCU design independently using the open-source tools, documentation, and community resources. Many participants will do exactly that.
+
+**Second**: The following companies offer paid consulting and engineering services. They're not free support—they're professional partners you can hire to help ensure your success.
+
+## When Might Professional Services Make Sense?
+
+Different people have different needs and constraints. Here are some scenarios where bringing in professional help might accelerate your project or reduce risk:
+
+- ⏰ **Time-Constrained Projects**: Reserved a slot but juggling multiple priorities? Professional help can accelerate your timeline and ensure you meet the December 3rd deadline.
+
+- 🎓 **First-Time Fabrication**: Never taped out a design before? Expert review can catch issues before going to silicon - much cheaper than discovering problems after fabrication.
+
+- 💼 **Commercial Projects**: Building a product for market? Professional contracts establish clear responsibilities, deliverables, and recourse if things go wrong - important when your business depends on it.
+
+- 📊 **Complex Analog/Mixed-Signal**: Sensitive analog circuits or complex interfaces? Experienced designers can optimize performance and help avoid subtle issues that only show up in silicon.
+
+- 🔧 **Tool-Specific Challenges**: Stuck with OpenROAD configuration or hitting tool limitations? Get help from the tool developers themselves - Precision Innovations built OpenROAD.
+
+These are just examples. Maybe you're working on something unique, or you need the contractual accountability that comes with paid professional services. The point is: you get to choose the approach that works for your situation.
+
+## Meet the Companies Offering Design Services
+
+Four companies are offering paid professional services specifically for [wafer.space](https://wafer.space/) GF180MCU designs. They're listed here in alphabetical order:
+
+---
+
+
+
+#### [ChipFlow](https://wafer.space/design-help.html#chipflow) · *Spain*
+
+Full-service ASIC development platform with cloud-based design tools, collaborative workflows, and pre-verified reference designs.
+
+> ChipFlow is excited to help you succeed with your wafer.space projects using our powerful design tools.
+— Rob Taylor, CTO
+
+---
+
+
+
+#### [Mabrains](https://wafer.space/design-help.html#mabrains) · *Egypt*
+
+PDK development, analog & digital design, physical design & layout, design verification, and AMS modeling. Over 25 years of experience, with expertise in AI/ML integration.
+
+> We at Mabrains are truly excited to empower designers and innovators working with the wafer.space process. Our goal is to help you bring your ideas to life and succeed every step of the way.
+— Amro Tork, CEO
+
+---
+
+
+
+#### [Precision Innovations](https://wafer.space/design-help.html#precision-innovations) · *USA*
+
+Primary developers of OpenROAD, offering commercial support, custom development, training & education, and rapid turnaround design flows. If you're using OpenROAD and need expert tool support, these are the people who built it.
+
+> Precision Innovations Inc provides paid professional support for OpenROAD in Industrial Applications. We are here to ensure your success!
+— Tom Spyrou, CEO
+
+---
+
+
+
+#### [SLICE Semiconductor](https://wafer.space/design-help.html#slice-semiconductor) · *Ireland*
+
+Low-cost ASIC development, mixed-signal IC design contracting, and consulting across technology nodes from 180nm to 3nm.
+
+> SLICE Semiconductor is excited to take your project from initial concept, right through to final silicon, targeting the wafer.space process.
+— Diarmuid, CEO
+
+---
+
+## Your Design, Your Approach
+
+Think of professional services as part of a spectrum of options, not an all-or-nothing choice:
+
+{% include post-gallery.html gallery="support_spectrum" %}
+
+
+You might handle 90% of your design independently and bring in expert review for critical analog sections. Or maybe you want someone to handle the entire physical design while you focus on verification. The approach you choose depends on your timeline, budget, and where you want to spend your effort.
+
+**Important note about community resources**: The [Discord](https://discord.gg/43y2t53jpE) and [Matrix](https://matrix.to/#/#gf180mcu:fossi-chat.org) channels are great places to learn and get guidance from others in the community. However, remember that ultimately you're responsible for your own design—either doing the work directly or paying someone to do it for you. Community members can point you in the right direction, but they're not substitute engineers for your project.
+
+## What Should You Do Next?
+
+### If you haven't purchased a slot yet:
+
+Don't let timeline concerns stop you from [reserving your spot](https://buy.wafer.space/). Professional help is available if you need it, but the **purchase deadline is November 28th**. After that, you're waiting for Run 2.
+
+1. Reserve your slot at [buy.wafer.space](https://buy.wafer.space/)
+2. Assess your design timeline and needs
+3. Reach out for professional quotes if helpful
+
+### If you've already purchased a slot:
+
+If you're feeling time pressure or want expert assistance, reach out to companies sooner rather than later. The **December 3rd GDS submission deadline** is approaching.
+
+1. Visit [wafer.space/design-help.html](https://wafer.space/design-help.html) for full company details
+2. Contact companies directly for quotes and availability
+3. Be specific about what you need (review, partial help, full service)
+
+### Free community resources (always available):
+
+- **Discord**: [discord.gg/43y2t53jpE](https://discord.gg/43y2t53jpE)
+- **Matrix**: [#gf180mcu:fossi-chat.org](https://matrix.to/#/#gf180mcu:fossi-chat.org)
+- **Documentation**: [gf180mcu-pdk.readthedocs.io](https://gf180mcu-pdk.readthedocs.io/)
+
+Remember: community members can offer guidance and share their experiences, but you're responsible for executing your design—whether that's by doing the work yourself or hiring professional help.
+
+## Making Silicon Truly Accessible
+
+[wafer.space](https://wafer.space/) exists to make custom silicon affordable. At $7 per chip for production quantities, we've removed the cost barrier to fabrication.
+
+These professional service companies extend that mission by making silicon accessible in another way: offering the option to pay for expertise when you need it. Not everyone has unlimited time to climb the learning curve. Having professional engineering services available means more people can participate in open silicon manufacturing.
+
+Your idea deserves to become real silicon. Whether you get there independently, with community help, with targeted professional help, or through full-service design, what matters is that you get there.
+
+\- Tim 'mithro' Ansell
diff --git a/_posts/2025-10-31-recent-publicity.md b/_posts/2025-10-31-recent-publicity.md
new file mode 100644
index 00000000..80e725ac
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+---
+layout: posts/post-boxed
+title: "Understanding wafer.space: Resources to Learn More About Our Mission"
+date: 2025-10-31 12:00:00 +0000
+excerpt: "A collection of interviews, articles, and podcasts that explain the wafer.space mission."
+categories: [news]
+tags: [gf180mcu, run1, press]
+author: "Tim 'mithro' Ansell"
+badge_color: "bg-purple"
+slider_post: false
+trending: false
+sidebar: true
+permalink: "/news/recent-publicity"
+post_image: "/assets/images/news/recent-publicity/shiny_sticker.png"
+external_url: "https://www.crowdsupply.com/wafer-space/gf180mcu-run-1/updates/recent-publicity"
+---
+
+Hey everyone,
+
+When Efabless shut down earlier this year, it left a critical gap: affordable access to custom silicon disappeared overnight. [wafer.space](https://wafer.space/) exists to fill that gap by providing pooled fabrication services that make custom silicon accessible at $7 per chip.
+
+{% include image.html file="/assets/images/news/recent-publicity/shiny_sticker.png" description="wafer.space - Making custom silicon accessible" %}
+
+Since launching our campaign, we've had the opportunity to explain this mission across various platforms. Each conversation reveals different aspects of why accessible silicon matters and how we're making it happen. Here's your guide to learning more.
+
+## Quick Start: Understanding the Vision
+
+**Why does [wafer.space](https://wafer.space/) exist?** Start with these resources to quickly understand what we're building:
+
+### [Electronics-Lab Interview](https://www.electronics-lab.com/e-lab-interview-wafer-space-founder-aims-to-make-custom-silicon-accessible-again/) (Article - 10 min read)
+**What you'll learn:** Why Tim created wafer.space after Efabless collapsed, why GF180MCU was chosen (cost-optimized process from a major foundry), how the pricing works ($7k for 1,000 dies enables real product development), toolchain options (open source via LibreLane or proprietary), packaging choices, and the path from prototype to production. Covers the full journey from concept to manufactured chips.
+
+### [HackWare Singapore Talk](https://www.youtube.com/watch?v=0nqV9Eo17wA) (Video - 30 min)
+**What you'll learn:** The journey from requiring NDAs and expensive tools to accessible silicon design, how Tiny Tapeout demonstrated that anyone can create chips (5,000+ people have taped out), why [wafer.space](https://wafer.space/) uses GlobalFoundries' cost structure for better pricing, and making Arduino-like products with custom silicon at $7,000 for 1,000 parts.
+
+## Deep Dive: Technical & Business Details
+
+**How does it actually work?** These resources explore the mechanics, economics, and ecosystem:
+
+### [Teardown Session 56: wafer.space with Tim Ansell & Leo Moser](https://youtu.be/tEOmnN8IAjs) (Video - 45 min)
+**What you'll learn:** How silicon pooling works like PCB services (OSH Park for chips), the journey from Google's open PDK program through Efabless to [wafer.space](https://wafer.space/), why 1,000 chips for $7,000 ($7/chip) makes custom silicon accessible for small-scale production (100-1000 units), and how open-source tools (LibreLane) and open PDKs enable this infrastructure.
+
+### [The Amp Hour #703](https://theamphour.com/703-building-wafer-space-with-tim-ansell/) (Podcast - 90 min)
+**What you'll learn:** The economics of pooled fabrication ($7k for 1,000 dies vs eFabless $10k for 150-200 dies), packaging options (bare die, chip-on-board, wirebonding with secondhand equipment), design tools from Tiny Tapeout to Verilog to analog layout, post-eFabless ecosystem (IHP Europe, ChipFoundry US, [wafer.space](https://wafer.space/) Singapore), professional help options (ChipFlow, Mabrains), and honest discussion about what makes $7/chip sustainable. Essential listening for anyone considering their own silicon project.
+
+## Community Perspectives: Why This Matters
+
+The tech press and community discussions reveal something important—this isn't just about one company or service. It's about fundamental infrastructure:
+
+### What Resonates: Three Key Themes
+
+**"Like OSH Park for silicon"** - Writers keep making this comparison because it captures something essential: predictable pricing, regular runs, and community-driven infrastructure that just works. Read more in [Hackster.io's coverage](https://www.hackster.io/news/wafer-space-delivers-1-000-chips-of-your-own-design-starting-at-just-7-each-75bbf49fd8b0).
+
+**"Democratizing chip design"** - When [CNX Software](https://www.cnx-software.com/2025/10/07/wafer-space-lets-you-design-your-custom-silicon-just-for-7-per-die/) and [LinuxGizmos](https://linuxgizmos.com/wafer-space-launches-gf180mcu-run-1-for-custom-silicon-fabrication/) cover the $7/die pricing, they're recognizing a shift: different people with different budgets can now participate in hardware innovation.
+
+**"Post-Efabless infrastructure"** - The [Contextual Electronics forum discussion](https://forum.contextualelectronics.com/t/wafer-space-low-cost-silicon-manufacturing-7k-1-000-ics/7313) digs into what this means practically: continuing critical work that an existing community depends on.
+
+### Active Discussions & Questions
+
+Community conversations reveal the questions people are asking and projects they're planning:
+
+**[David Shadoff on Bluesky](https://bsky.app/profile/dshadoff.bsky.social/post/3m2ie2vm2ns2y)** explores retro-computer and console chip designs: "Most can be done on FPGA today, custom silicon could make assembly cheaper (reducing FPGA support)." This captures a key use case—when custom ASICs make more sense than FPGAs for production.
+
+**[Luke Wren on Mastodon](https://types.pl/@wren6991/115267990436492107)** does the math on what fits in 20mm²: "The smallest NAND2 is 11 square microns, so assuming 2/3rds of the die is non padding, that's 1.2 million gates. The densest SRAM macro they provide is 512 bytes in 0.21 mm², so if you fill the area with RAM that's around 31 kB. Enough for a small Linux SoC." Real calculations showing what's actually achievable.
+
+Other discussions across [Mastodon (#OpenSilicon)](https://mastodon.social/tags/OpenSilicon), [Reddit (/r/chipdesign)](https://www.reddit.com/r/chipdesign/), and [LinkedIn](https://www.linkedin.com/feed/hashtag/opensilicon/) explore:
+- Technical: "What's achievable in 20mm²?"
+- Practical: "Can this work for small production runs?"
+- Strategic: "How does this change who can design chips?"
+
+Join these discussions to learn from others exploring the same questions.
+
+## Your Learning Path Forward
+
+Whether you're curious or committed, here's how to engage:
+
+1. **Quick start** - Read the [Electronics-Lab interview](https://www.electronics-lab.com/e-lab-interview-wafer-space-founder-aims-to-make-custom-silicon-accessible-again/) or watch the [HackWare talk](https://www.youtube.com/watch?v=0nqV9Eo17wA) to grasp the mission
+2. **Deep dive** - Watch the [Teardown session](https://youtu.be/tEOmnN8IAjs) or listen to [The Amp Hour](https://theamphour.com/703-building-wafer-space-with-tim-ansell/) for technical and business insights
+3. **Connect with community** - Join [Discord](https://discord.gg/43y2t53jpE) or [Matrix](https://matrix.to/#/#gf180mcu:fossi-chat.org) to ask questions and learn from others
+4. **Evaluate your project** - Use the resources above to determine if Run 1 fits your needs
+
+**Ready to participate?** Campaign closes November 28th. Reserve your slot at [buy.wafer.space](https://buy.wafer.space/).
+
+**Still learning?** That's perfect. Use these resources to understand not just what we're offering, but why rebuilding accessible silicon infrastructure matters for the future of open hardware.
+
+## Coming Updates: Practical Guidance
+
+Future updates will provide hands-on learning:
+- Example designs - what fits in 20mm² with detailed analysis
+- Submission process - step-by-step guide for December 3rd deadline
+- Packaging options - understanding your choices from bare dies to chip on board option
+
+## The Bigger Picture
+
+When custom silicon costs $7 per chip instead of requiring $70,000 minimum orders, different people with different projects can participate. Students can learn chip design alongside programming. Hardware startups can prototype with custom ASICs instead of compromising with FPGAs. Retro computing enthusiasts can recreate vintage chips. Small production runs become viable.
+
+The conversations above explore this shift from multiple angles—technical, economic, and practical. They document not just what [wafer.space](https://wafer.space/) offers, but why rebuilding accessible fabrication infrastructure matters for hardware innovation.
+
+Thanks for taking the time to learn about this mission. Whether you join Run 1 or future runs, understanding why this infrastructure matters is the first step.
+
+\- Tim 'mithro' Ansell
diff --git a/_posts/2025-11-05-openfasoc-sensor.md b/_posts/2025-11-05-openfasoc-sensor.md
new file mode 100644
index 00000000..a317cdaa
--- /dev/null
+++ b/_posts/2025-11-05-openfasoc-sensor.md
@@ -0,0 +1,82 @@
+---
+layout: posts/post-boxed
+title: "Campaign Update: Building Real Sensors with GF180MCU — See What's Possible!"
+date: 2025-11-05 12:00:00 +0000
+excerpt: "Wonder what you can do with GF180MCU? Mehdi's OpenFASoC design creates a finger flex sensor, complete with an IEEE paper containing real silicon characteristics and analog blocks reusable for your own design!"
+categories: [news]
+tags: [gf180mcu, run1, openfasoc, analog]
+author: "Tim 'mithro' Ansell"
+badge_color: "bg-purple"
+slider_post: false
+trending: false
+sidebar: true
+permalink: "/news/openfasoc-sensor"
+post_image: "/assets/images/news/openfasoc-sensor/annotated_shot.png"
+external_url: "https://www.crowdsupply.com/wafer-space/gf180mcu-run-1/updates/openfasoc"
+---
+
+Hey everyone! 👋
+
+As we get closer to our **December 3rd tape-in deadline** (that's coming up fast!), I wanted to share something that really shows the power of what you can build with the [GF180MCU process](https://gf180mcu-pdk.readthedocs.io/) we're pooling together.
+
+## Real Silicon, Real Applications
+
+[Saligane](https://vivo.brown.edu/display/msaligan)'s group at the University of Michigan - now at Brown University - recently published [a paper in IEEE Solid-State Circuits Magazine](https://ieeexplore.ieee.org/document/10584418) showing off an analog front-end (AFE) chip they designed entirely with open-source tools on GF180MCU. And it's not just a test chip — they're using it to read out flexible laser-induced graphene sensors for wearables!
+
+{% include image.html file="/assets/images/news/openfasoc-sensor/annotated_shot.png" description="The fabricated GF180MCU chip showing OPAMP blocks, SAR ADC, and switched-capacitance circuits" %}
+
+([View high-resolution die photography on Silicon Prawn](https://siliconprawn.org/archive/doku.php?id=mcmaster:efabless:gf180mcu-mpw18h1-18100004))
+
+The chip integrates operational amplifiers, a 14-bit SAR ADC, and a capacitive DAC to create a complete sensor readout platform. They demonstrated it working with:
+
+- **Strain/flex sensors** (detecting finger bending in real-time)
+- **Temperature sensors** (tracking body temperature with 0.9989 R² accuracy)
+- **Multi-modal sensing** (combining different sensor types on one platform)
+
+{% include image.html file="/assets/images/news/openfasoc-sensor/test_setup.png" description="The fabricated chip wire-bonded to a PCB, ready to interface with flexible sensor patches" %}
+
+## The Open Source Flow Works!
+
+What's exciting is they used the exact same open-source toolchain you have access to:
+- [XSchem](https://xschem.sourceforge.io/stefan/index.html) for schematic capture
+- [Ngspice](https://ngspice.sourceforge.io/) for simulation
+- [KLayout](https://www.klayout.de/) and [Magic](https://github.com/RTimothyEdwards/magic) for layout
+- Standard DRC/LVS checks
+
+They've published their designs on GitHub in the [OpenFASoC-Tapeouts repository](https://github.com/idea-fasoc/openfasoc-tapeouts?tab=readme-ov-file#analog-front-end-and-mixed-signal), and the [final submission is available on foss-eda-tools](https://foss-eda-tools.googlesource.com/third_party/shuttle/gf180mcu/mpw-18h1/slot-004/+/refs/heads/main), which means you can actually look at exactly how they did it.
+
+{% include image.html file="/assets/images/news/openfasoc-sensor/analog_flow.png" description="The complete open-source analog design flow used for this project" %}
+
+## Reuse, Don't Reinvent!
+
+This is where it gets really interesting for your designs. The [OpenFASoC project](https://github.com/idea-fasoc/OpenFASOC) provides **building blocks you can directly reuse**:
+
+- **[Folded-cascode OPAMP](https://github.com/idea-fasoc/openfasoc-tapeouts/tree/main/mpw18h1/opamp-gen/Programmable_2stage)** with programmable bias for noise/power trade-offs
+- **[14-bit SAR ADC](https://github.com/idea-fasoc/openfasoc-tapeouts/tree/main/mpw18h1/adc-gen/comparator)** (asynchronous, monotonic switching)
+- **[Bootstrapper and switch circuits](https://github.com/idea-fasoc/openfasoc-tapeouts/tree/main/mpw18h1/cisar-gen/spice)** for high-performance sampling
+- **[Comparator circuits](https://github.com/idea-fasoc/openfasoc-tapeouts/tree/main/mpw18h1/adc-gen/comparator)** (double-tail latch and StrongArm topologies)
+
+You can literally take their [GDSII files](https://github.com/idea-fasoc/openfasoc-tapeouts/tree/main/mpw18h1/gds), study their layout techniques, and adapt their circuits for your own sensor applications. Need to read out a resistive sensor? Temperature probe? Custom transducer? The hard work of building reliable analog blocks is already done.
+
+{% include image.html file="/assets/images/news/openfasoc-sensor/testing.png" description="Real-time flex sensor demonstration showing finger bending detection with the AFE chip" %}
+
+## What Could You Build?
+
+Think about applications like:
+- Environmental monitoring devices
+- Biomedical wearables
+- Industrial sensor nodes
+- Custom instrumentation
+- IoT edge devices with analog sensing
+
+With [GF180MCU's](https://gf180mcu-pdk.readthedocs.io/) 5 metal layers, MIM capacitors, multiple resistor types, and mixed-signal capabilities, you have everything needed for serious analog and mixed-signal designs.
+
+## Get Inspired, Get Building
+
+Check out the [full paper](https://siliconprawn.org/archive/lib/exe/fetch.php?media=mcmaster:efabless:gf180mcu-mpw18h1-18100004:rapid-prototyping-of-laser-induced-graphene-sensors-with-open-source-silicon-paving-the-way-small.pdf) to see detailed schematics, measurement results, and their complete design flow. This is real silicon, designed with open tools, doing real work — exactly what we're enabling with this pooled run.
+
+Questions about the campaign or getting started with GF180MCU? Hit reply or join our community discussions!
+
+\- Tim "mithro" Ansell
+
+*P.S. — If you haven't reserved your slot yet, head over to [buy.wafer.space](https://buy.wafer.space/) before November 28th. After that, you'll be waiting for Run 2!*
diff --git a/_posts/2025-11-11-chip-on-board-strategy.md b/_posts/2025-11-11-chip-on-board-strategy.md
new file mode 100644
index 00000000..ca1795b7
--- /dev/null
+++ b/_posts/2025-11-11-chip-on-board-strategy.md
@@ -0,0 +1,262 @@
+---
+layout: "posts/post-boxed"
+title: "Community Progress on Chip-on-Board Packaging Strategy"
+date: "2025-11-11 12:00:00 +0000"
+excerpt: "The wafer.space community is developing a flexible chip-on-board packaging strategy, so you won't need specialised equipment or expensive packaging services to use your chips."
+categories: [news]
+tags: [gf180mcu, run1, packaging, chip-on-board]
+author: "Andrew Wingate"
+badge_color: "bg-purple"
+slider_post: false
+trending: false
+sidebar: true
+permalink: "/news/chip-on-board-strategy"
+post_image: "/assets/images/news/chip-on-board-strategy/padframes-cob-die-padring.png"
+external_url: "https://www.crowdsupply.com/wafer-space/gf180mcu-run-1/updates/chip-on-board"
+galleries:
+ mezzanine_views:
+ caption: "Mezzanine COB board design"
+ images:
+ - img: "/assets/images/news/chip-on-board-strategy/padframes-cob-mezzanine-front.png"
+ alt: "Mezzanine COB board - front view"
+ - img: "/assets/images/news/chip-on-board-strategy/padframes-cob-mezzanine-back.png"
+ alt: "Mezzanine COB board - back view"
+ mezzanine_panels:
+ caption: "Mezzanine panel for wirebonding assembly"
+ images:
+ - img: "/assets/images/news/chip-on-board-strategy/padframes-cob-mezzanine-panel-front.png"
+ alt: "Mezzanine panel - front view for wirebonding assembly"
+ - img: "/assets/images/news/chip-on-board-strategy/padframes-cob-mezzanine-panel-rear.png"
+ alt: "Mezzanine panel - rear view"
+ dip_designs:
+ caption: "DIP package designs"
+ images:
+ - img: "/assets/images/news/chip-on-board-strategy/padframes-cob-dip.png"
+ alt: "DIP package design - standard through-hole format"
+ - img: "/assets/images/news/chip-on-board-strategy/padframes-cob-dip1.png"
+ alt: "DIP package design - alternative layout"
+---
+
+Today we have a guest post from **[Andrew Wingate](https://www.crowdsupply.com/evezor-inc)** (of Evezor Inc), sharing his perspective on the progress the [wafer.space](https://wafer.space/) community has been making in developing a chip-on-board packaging strategy. This work includes contributions from **[Tiny Tapeout](https://tinytapeout.com/)**, **[MosBius](https://mosbius.org/)** ([Columbia University](https://peterkinget.github.io/)), and community members like **[@Tholin](https://github.com/AvalonSemiconductors)** and **@xianglin_pu**.
+
+---
+
+[**wafer.space**](https://wafer.space/) exists to make custom silicon affordable. At **$7 per chip** for production quantities, the cost barrier to fabrication has been removed, but that's only part of the story. Working with bare dies is challenging and typically requires specialized, expensive equipment.
+
+To make post-fabrication development more accessible, the community has been working on **COB (Chip on Board)** standard templates. Over the past months, various package options have been explored, including **DIP, LGA, castellated breakouts,** and **breadboardable** versions.
+
+The leading contender is currently a **mezzanine breakout board** using connectors similar to those found on the Raspberry Pi Compute Modules. This design allows wirebonding houses to mount and wirebond your dies directly onto the COB packages, which can then be shipped to you ready for integration into your own systems.
+
+When designing your motherboards, you'll be able to source compatible connectors like [this one](https://www.lcsc.com/product-detail/C19089262.html) and have your PCBA house assemble them. The community is also working on a range of breakout boards that follow a **community-developed standard digital padring**, to make development faster and more consistent.
+
+> **What This Means For You:** If you're backing this campaign or considering it, you won't need specialized equipment or expensive packaging services to use your chips. While the community continues developing these COB standards, [wafer.space is offering wire-bonded COB packaging at buy.wafer.space](https://buy.wafer.space) for this campaign run (1,000 dies mounted and wire-bonded to PCBs). Alternatively, you can work with your own wirebonding partner using these community-developed designs. Either way, you'll solder the connector to your custom PCB and plug them in just like adding any other component to your board.
+
+---
+
+### The Community-Developed Standard Padframe and COB Design
+
+While you're free to use any pad configuration you wish, adhering to the **community-developed standard** ensures compatibility with wirebonding partners and simplifies the fabrication process.
+
+**Key Details:**
+
+* **74-pad padframe** on your die
+
+* **20 pads** on the east and west sides
+
+* **17 pads** on the north and south sides
+
+* **74-pad wirebonding footprint**
+
+* **14 mm × 16 mm PCB**
+
+* **70-pin mezzanine connector:** [C19089236](https://www.lcsc.com/product-detail/C19089236.html) *or compatible*
+
+* **1 µF decoupling capacitors** on VDD_IO, VDD_CORE, and PWR_AUX pins
+
+Find most current designs on the [chip-on-board-wire-bonded-pcbs repo](https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs)
+
+## Why Standardize?
+
+With the technical details established, it's worth stepping back to consider why standardization matters for the open silicon ecosystem.
+
+### A Standard for the Broader Community
+
+While this standard emerged from the wafer.space community's needs, the goal is to create something that could benefit the broader open silicon ecosystem. By documenting the design openly and making the [KiCad](https://www.kicad.org/) symbols, PCB layouts, and specifications freely available, other projects and communities could adopt or adapt this approach for their own chip-on-board needs.
+
+The work you see here comes from contributors across the community: Discord members testing designs and providing feedback, Tiny Tapeout contributors sharing lessons from their COB runs, Columbia University students developing educational chips through the MosBius project, and veteran engineers refining the wirebonding footprints. Each brought different expertise: some from PCB design, others from silicon layout, still others from manufacturing and assembly experience.
+
+The hope is that as more projects use compatible footprints and connectors, the ecosystem benefits grow:
+- Wirebonding houses can optimize their processes for a common standard
+- More off-the-shelf breakout boards and adapters become available
+- Designers can share compatible motherboard designs across projects
+- The barrier to entry for COB assembly continues to decrease
+
+This isn't about mandating a single approach. Diversity in packaging solutions remains valuable. Rather, it's about establishing a well-documented baseline that communities can rally around when standardization helps everyone. If this standard proves useful beyond wafer.space, that would represent exactly the kind of collaborative progress that makes open silicon compelling.
+
+This design hopefully meets the needs of a majority of projects on wafer.space. If your project needs something different, other open source packaging options are available to explore, such as the University of Washington's **[BaseJump project](https://bjump.org/)**, which offers **[BGA packaging standards](https://github.com/bespoke-silicon-group/bsg_packaging)** including their 352-pin BaseJump Socket for designs requiring hundreds of I/O pins or more complex integration.
+
+## The Implementation: From Concept to Physical Boards
+
+So what does this standard look like in practice? Let's walk through the actual hardware, tools, and resources the community has developed.
+
+### 70-Pin Mezzanine COB
+
+The centerpiece of the standard is a 70-pin mezzanine COB board that connects your wirebonded die to a standard connector.
+
+{% include post-gallery.html gallery="mezzanine_views" %}
+
+
+Panelized for efficient handling and assembly by wirebonding partners:
+
+{% include post-gallery.html gallery="mezzanine_panels" %}
+
+
+The standard configuration can be found in the [GitHub repository](https://github.com/wafer-space/gf180mcu-project-template/blob/main/librelane/config.yaml). For easier viewing, it's also available as a [Google Sheet](https://docs.google.com/spreadsheets/d/1pI2BAEWEexXcXN3vah3SR85zPIV6eAXPGXc2bcvoSGU/edit?gid=0#gid=0) that shows the complete pad mapping.
+
+{% include image.html file="/assets/images/news/chip-on-board-strategy/padframes-cob-die-padring.png" description="Die padring layout with 74-pad configuration" class="img-fluid rounded" %}
+
+To help visualize your own pad layouts, Discord user **@Tholin** has developed a Python-based pad viewer that generates an image of the pad layout defined in your template. This is useful for verifying your configuration matches your design intent. You can find the tool [here](https://github.com/AvalonSemiconductors/ws-submission-2025/blob/main/padout_gen.py).
+
+---
+
+## Design Tools and Ecosystem
+
+Having the physical COB boards is only part of the picture. To actually use them, designers need schematic symbols, footprints, and integration tools. Here's what the community has built to support the full design workflow.
+
+### Default KiCad Symbols
+
+The community has developed several **[KiCad](https://www.kicad.org/) symbols** to support design and integration with COB layouts.
+
+The **pad mapping symbol** corresponds to the default 74-pad wirebonding padframe and [default configuration](https://github.com/wafer-space/gf180mcu-project-template/blob/main/librelane/config.yaml) from the [**GF180MCU Project Template**](https://github.com/wafer-space/gf180mcu-project-template).
+
+> Some users have suggested reducing the number of ground and power pads. If there is sufficient demand, an alternate default configuration will be created.
+> Join the discussion on our [**Discord server**](https://discord.gg/43y2t53jpE).
+
+{% include image.html file="/assets/images/news/chip-on-board-strategy/padframes-cob-default-74pad-wirebond-symbol.png" description="Default 74-pad wirebonding padframe symbol" %}
+
+---
+
+### 70-Pin Mezzanine Connector Symbol
+
+The **mezzanine connector symbol** provides a 1:1 pin mapping to the 70-pin default layout.
+All pins are aliased to match [Tiny Tapeout](https://tinytapeout.com/) naming conventions, useful for those familiar with the TT ecosystem who are designing custom chips for this wafer.space run.
+
+{% include image.html file="/assets/images/news/chip-on-board-strategy/padframes-cob-default-70pin-mezzanine-symbol.png" description="Default 70-pin mezzanine COB breakout symbol" %}
+
+An alternate version is also available that organizes pins by signal type. This version is particularly useful for Tiny Tapeout-style breakout motherboard designs where grouping by function makes routing clearer.
+
+{% include image.html file="/assets/images/news/chip-on-board-strategy/padframes-cob-tinytapeout-kicad-symbols.png" description="70-pin mezzanine COB symbol organized by signal type (Tiny Tapeout version)" %}
+
+### KiCad Resources for COB Design
+
+While the initial symbols are in KiCad, the community welcomes contributions of symbols and libraries for other PCB design tools. If you use Altium, Eagle, or another tool, please submit a pull request to the [chip-on-board-wire-bonded-pcbs repo](https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs)!
+
+For those new to KiCad or looking to deepen their PCB design skills, **Pat Deegan** (developer of the **[Tiny Tapeout demo board](https://github.com/TinyTapeout/tt-demo-pcb)**) offers **[KiCad:Unlocked](https://inductive-kickback.com/2024/07/kicadunlocked-a-course-for-deep-kicad/)**, a comprehensive free course that covers everything from basic circuit design to advanced PCB layout techniques. The community hopes to work with Pat in the future on a tutorial specifically focused on wire bonding integration and designing motherboards for wafer.space COB packages.
+
+If you want to quickly review KiCad designs without installing software, **[KiCanvas](https://kicanvas.org/)** provides a browser-based viewer for KiCad files. You can use it to inspect the standard COB layouts, verify connector pinouts, and review community-contributed designs, all directly in your browser.
+
+---
+
+### Beyond the Standard: Expanding Options
+
+While the 70-pin mezzanine connector serves as the standard, the community recognizes that different projects have different needs.
+
+#### Castellated and Breadboardable Breakouts
+
+The community is developing a series of breakout boards designed to make it easier to prototype, experiment, and integrate your dies into existing systems.
+
+{% include image.html file="/assets/images/news/chip-on-board-strategy/padframes-cob-breakouts.png" description="Castellated and breadboardable breakout board designs" %}
+
+---
+
+## Real-World Adoption
+
+The real test of any standard is whether people actually use it. Here's how the community is already building on this work.
+
+### Derivative Designs
+
+It's exciting to see others building on the [wafer.space](https://wafer.space/) platform!
+**[Professor Peter Kinget](https://peterkinget.github.io/)** and his students at **[Columbia University](https://peterkinget.github.io/)** are developing educational chips using [wafer.space](https://wafer.space/) for their [**MosBius Project**](https://mosbius.org/0_front_matter/intro.html).
+
+MosBius provides students and designers the opportunity to explore MOS circuit topologies through a unique **analog switch matrix**, where each pin can connect to any of ten on-chip buses. This enables flexible on-chip circuit wiring and simplifies testing setups.
+
+{% include image.html file="/assets/images/news/chip-on-board-strategy/padframes-cob-mosbius.png" description="MosBius Project chip design from Columbia University" %}
+
+*Image and design by @xianglin_pu on [wafer.space Discord](https://discord.gg/43y2t53jpE)*
+
+---
+
+### The Path Not (Yet) Taken
+
+Before settling on the mezzanine connector as the standard, the community explored several alternative packaging approaches. While these didn't become the primary standard, they represent valuable experiments that informed the final design and may still serve specialized use cases.
+
+#### LGA (Land Grid Array)
+
+{% include image.html file="/assets/images/news/chip-on-board-strategy/padframes-cob-lga-cob.png" description="LGA (Land Grid Array) COB package design" %}
+
+#### DIP
+
+{% include post-gallery.html gallery="dip_designs" %}
+
+
+#### Castellated
+
+{% include image.html file="/assets/images/news/chip-on-board-strategy/padframes-cob-castellated.png" description="Castellated edge COB package design" %}
+
+---
+
+## Learning from Pioneers
+
+The wafer.space COB work doesn't exist in isolation. Other projects have tackled similar challenges, and their experiences directly inform this effort.
+
+{% include image.html file="/assets/images/news/chip-on-board-strategy/padframes-cob-tt-cob.jpg" description="Tiny Tapeout chip-on-board implementation" %}
+
+Tiny Tapeout recently [published an update](https://www.zerotoasiccourse.com/post/cob/) on their first successful Chip-on-Board (COB) implementation, highlighting their bare-die submission on the Zero to ASIC Course "MPW-7" run.
+
+{% include youtube.html id="XJmWoBJjvlI" autoplay=0 mute=0 controls=1 loop=0 caption="Tiny Tapeout 9 - First COB samples!" %}
+
+While Tiny Tapeout achieved a significant milestone, they also noted limitations: the long bonding wires increased inductance and degraded performance, and securing small-volume wire-bonding services remains difficult.
+
+For those interested in understanding the wire bonding process in detail, Stephan Bökelmann's talk at Kicon 2025 provides an excellent introduction to the practical challenges and techniques.
+
+{% include youtube.html id="dNBwY7L6niI" autoplay=0 mute=0 controls=1 loop=0 caption="Poor man's intro to Wire-Bonding @ Kicon 2025" %}
+
+The [wafer.space](https://wafer.space/) community views these learnings as a springboard. By introducing standardized COB templates, the goal is to make COB packaging more accessible, more scalable, and better optimized. The objective is to build upon the success of Tiny Tapeout and improve their future runs by reducing parasitics, streamlining the supply chain, and enabling anyone to pick up a COB-mounted die and integrate it into their system with ease.
+
+---
+
+## Join the Effort
+
+This community-developed standard is exactly that: community-developed. The designs, symbols, and approaches documented here represent months of collaborative work, but they're far from finished.
+
+The community is exploring multiple **COB packaging varieties** and would love your contribution:
+
+**If you're designing a chip for this run:**
+- Share your I/O requirements in the **#cob** Discord channel. Your needs help refine future designs
+- Test the pad viewer tool and report any issues or feature requests
+
+**If you have COB or wirebonding experience:**
+- Share vendor recommendations or tips for small-volume runs
+- Provide feedback on the wirebonding footprint design
+- Help identify potential manufacturing issues before they become problems
+
+**If you use other PCB design tools:**
+- Contribute symbols and footprints for Altium, Eagle, or other platforms
+- Submit pull requests to the [chip-on-board-wire-bonded-pcbs repo](https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs)
+
+**If you're curious or have questions:**
+- Ask in Discord. The community includes experienced designers happy to help
+- Review the designs using KiCanvas and suggest improvements
+- Help test breakout board designs and report what works (or doesn't)
+
+Join the community and help shape the future of accessible silicon design:
+
+* **Discord:** [discord.gg/43y2t53jpE](https://discord.gg/43y2t53jpE) (see **#cob** channel)
+
+* **Matrix:** [#gf180mcu.org](https://matrix.to/#/#gf180mcu:fossi-chat.org)
+
+Together, the community can make custom silicon as easy and affordable as PCB design.
+
+---
+
+**Thanks to Andrew Wingate for this guest post!** If you're interested in chip-on-board packaging, join the **#cob channel** on the [wafer.space Discord](https://discord.gg/43y2t53jpE) to discuss designs, share feedback, and help contribute to making COB packaging accessible for everyone.
diff --git a/_posts/2025-11-14-tholin-feature.md b/_posts/2025-11-14-tholin-feature.md
new file mode 100644
index 00000000..f09b15dd
--- /dev/null
+++ b/_posts/2025-11-14-tholin-feature.md
@@ -0,0 +1,148 @@
+---
+layout: "posts/post-boxed"
+title: "We Have Some Amazing Projects This Run"
+date: "2025-11-14 12:00:00 +0000"
+excerpt: "Our first shuttle run includes incredible projects. We highlight Tholin and Avalon Semiconductors: an open reimplementation of the historic Signetics 2650 microprocessor."
+categories: [news]
+tags: [gf180mcu, run1, featured-project, tholin]
+author: "Tim 'mithro' Ansell"
+badge_color: "bg-purple"
+slider_post: false
+trending: false
+sidebar: true
+permalink: "/news/tholin-feature"
+post_image: "/assets/images/news/tholin-feature/ic1.png"
+external_url: "https://www.crowdsupply.com/wafer-space/gf180mcu-run-1/updates/tholin-feature"
+galleries:
+ multi_project:
+ caption: "Multi-project die strategy"
+ images:
+ - img: "/assets/images/news/tholin-feature/multidie.png"
+ alt: "Multi-project die layout combining multiple designs on one die"
+ - img: "/assets/images/news/tholin-feature/multilayout.png"
+ alt: "Multi-project die floorplan showing design placement"
+ dip40_breakout:
+ caption: "DIP40 breakout board and wirebonding"
+ images:
+ - img: "/assets/images/news/tholin-feature/dip40.png"
+ alt: "DIP40 breakout board for custom silicon"
+ - img: "/assets/images/news/tholin-feature/dip40_wirebond.png"
+ alt: "DIP40 wirebonding setup connecting die pads to package pins"
+---
+
+Our first shuttle run includes a number of incredible projects, and we wanted to take a moment to highlight one of them.
+
+---
+
+## Tholin & Avalon Semiconductors
+
+{% include image.html file="/assets/images/news/tholin-feature/ic1.png" description="Tholin's custom silicon designs showcase what's possible with open tooling" %}
+
+[Tholin](https://tholin.dev/) — the hardware designer behind [**Avalon Semiconductors**](https://github.com/AvalonSemiconductors) — has been exploring what's possible when open tooling meets personal silicon. Their journey, chronicled through detailed blog posts like [*Custom Silicon*](https://tholin.dev/custom_silicon/) and [*Custom Silicon Two: Electric Boogaloo*](https://tholin.dev/custom_silicon_two_electric_boogaloo/), shows how a single engineer can go from HDL to packaged chips using open-source flows, patience, and a healthy dose of curiosity.
+
+---
+
+### AS2650 and AS2650-2
+
+{% include image.html file="/assets/images/news/tholin-feature/as2650.png" description="The AS2650(-2) is inspired by retro CPUs like the Signetics 2650" %}
+
+Tholin's flagship projects are the **AS2650** and **AS2650-2**, re-implementations and extensions of the historic [Signetics 2650](https://en.wikipedia.org/wiki/Signetics_2650) microprocessor, recreated from the ground up using open EDA tools.
+You can explore the repositories here:
+
+* [AS2650 GitHub Repository](https://github.com/AvalonSemiconductors/AS2650)
+* [AS2650 Documentation](https://avalonsemiconductors.github.io/AS2650/)
+
+These chips aren’t just nostalgic exercises — they’re fully functional processors that have been designed, simulated, taped-out, and brought back to life with custom test boards and firmware. The AS2650-2 introduces expanded peripherals, enhanced bus control, and improved debug accessibility. All implemented with a custom cell library for GF180MCU.
+
+---
+
+### Porting the AS2650v2 to wafer.space
+
+**Tholin** is currently porting the **AS2650v2** to the [**wafer.space**](https://wafer.space) template.
+This serves as a **reference design**, demonstrating a complete CPU implementation, a multi-macro layout, and new methodologies for **instantiating SRAMs** within the wafer.space framework.
+
+The project also makes use of **high-performance dynamic D-type flip-flop circuits (DFFs)** from the
+[**gf180mcu_as_ex_mcu7t5v0**](https://github.com/AvalonSemiconductors/gf180mcu_as_ex_mcu7t5v0) library.
+
+Tholin notes that the wafer.space padframe provides **more pads than the Efabless Caravel design**, resulting in a number of unused pins during this initial port. She suggests that future revisions may take advantage of these additional pads to support **expanded peripherals** and system features.
+
+You can explore the design and accompanying documentation on GitHub:
+👉 [**AvalonSemiconductors/as2650-ws**](https://github.com/AvalonSemiconductors/as2650-ws)
+
+---
+
+### wafer.space Submissions
+
+Tholin has also created a companion repository,
+[**ws-submission-2025**](https://github.com/AvalonSemiconductors/ws-submission-2025), documenting her submission for the current wafer.space fabrication run.
+
+True to her style, the project includes **artwork integrated directly into the silicon layout**, reflecting the creative potential unlocked when advanced design tools are accessible and open.
+
+{% include image.html file="/assets/images/news/tholin-feature/logo_bw.png" description="Tholin's logo, adapted for silicon artwork" %}
+
+Additionally, Tholin developed a [**Python script**](https://github.com/AvalonSemiconductors/ws-submission-2025/blob/main/padout_gen.py) that **automatically generates padout diagrams** from a [LibreLane](https://librelane.rtfd.io/) configuration file thereby simplifying visualization and documentation of pad assignments.
+
+{% include image.html file="/assets/images/news/tholin-feature/padout.png" description="Padout diagram generated from Python and LibreLane configuration" %}
+
+
+---
+
+### Multi-Project Die Exploration
+
+{% include post-gallery.html gallery="multi_project" %}
+
+
+Tholin is also pioneering **multi-project die (MPD)** strategies, maximizing wafer area by integrating multiple small designs onto a single die.
+Projects such as [`gfmpw-1-multi`](https://github.com/AvalonSemiconductors/gfmpw1-multi) and [`AS2650-bring-up`](https://github.com/AvalonSemiconductors/AS2650-bring-up) demonstrate how careful planning and padframe reuse make it possible to test multiple subsystems in one run.
+
+Tholin has also written thorough documentation on this project [here](https://avalonsemiconductors.github.io/GFMPW-1-MULTI/index.html)
+
+This approach reflects the open ethos of wafer.space — making silicon exploration more accessible, modular, and repeatable for small teams and individuals.
+
+---
+
+### Open Flow & LibreLane Experience
+
+Tholin has been an early adopter of [**LibreLane**](https://librelane.rtfd.io/), the open-source ASIC flow used by wafer.space. Their feedback and experiments with padframes, padrings, and packaging have helped refine the ecosystem for everyone.
+From RTL through layout and DRC, to bonding and board testing, Tholin's work demonstrates that open tooling can now carry a chip from idea to reality — no closed vendor stack required.
+
+{% include image.html file="/assets/images/news/tholin-feature/3d_view.png" description="Standard cells are a key component of RTL to GDSII flows" %}
+
+---
+
+### Other Avalon Semiconductors Projects
+
+Tholin has also created a number of fun and technically rich designs through **Tiny Tapeout**, showcasing creativity across digital design, display drivers, and compact CPUs:
+
+| Name | Description | GitHub Link |
+| ------------------------ | ------------------------------------------------------------------------------------ | --------------------------------------------------------------------------------------------------------------- |
+| **AS5401** | 4-bit CPU | [AvalonSemiconductors/tt2-AvalonSemi-5401](https://github.com/AvalonSemiconductors/tt2-AvalonSemi-5401) |
+| **TT02 Logisim Example** | Example and documentation on submitting Tiny Tapeout designs using Logisim Evolution | [AvalonSemiconductors/tt02-logisim-example](https://github.com/AvalonSemiconductors/tt02-logisim-example) |
+| **Diceroll** | Animates a random number rolling on a 7-segment display | [AvalonSemiconductors/tt2-diceroll](https://github.com/AvalonSemiconductors/tt2-diceroll) |
+| **TBB143** | Programmable sound generator using a ring oscillator as a faster internal clock | [AvalonSemiconductors/tt2-avalonsemi-TBB1143](https://github.com/AvalonSemiconductors/tt2-avalonsemi-TBB1143) |
+| **Multiplexed Counter** | Drives 4 multiplexed 7-segment displays to count time up to 99 min 59 sec | [AvalonSemiconductors/tt2-multiplexed-counter](https://github.com/AvalonSemiconductors/tt2-multiplexed-counter) |
+| **4-bit Multiplier** | Multiplies two 4-bit numbers into an 8-bit result | [AvalonSemiconductors/tt2-4x4-multiply](https://github.com/AvalonSemiconductors/tt2-4x4-multiply) |
+| **LCD Namebadge** | Experiment with character LCD interfacing | [AvalonSemiconductors/tt2-lcd-namebadge](https://github.com/AvalonSemiconductors/tt2-lcd-namebadge) |
+
+Each of these designs exemplifies the open-hardware spirit: compact, educational, and fully reproducible — proof that anyone can design real silicon with today's open tools.
+
+---
+
+### Beyond Silicon
+
+Beyond her silicon designs, **Tholin** has also developed a range of PCB projects and breakout boards that make working with custom dies more accessible.
+
+{% include post-gallery.html gallery="dip40_breakout" %}
+
+
+Tholin has also contributed extensively to the **wafer.space standard padframe**, helping shape the mechanical and electrical layout used across multiple projects.
+
+---
+
+### Why We’re Excited to Have Tholin Aboard
+
+Tholin represents the kind of creative, self-driven engineering that wafer.space exists to empower. Her work with the AS2650 family, open flows, and multi-project dies captures the spirit of the growing open-silicon movement — one where innovation comes from curiosity, not corporate budgets.
+
+We’re thrilled to have **Tholin & Avalon Semiconductors** among the first wave of wafer.space participants and can’t wait to see what they build next.
+
+
diff --git a/_posts/2025-11-19-mosbius-feature.md b/_posts/2025-11-19-mosbius-feature.md
new file mode 100644
index 00000000..182907de
--- /dev/null
+++ b/_posts/2025-11-19-mosbius-feature.md
@@ -0,0 +1,77 @@
+---
+layout: "posts/post-boxed"
+title: "We Have Some Amazing Projects This Run: MOSbius"
+date: "2025-11-19 12:00:00 +0000"
+excerpt: "This week we highlight MOSbius, an educational platform from Columbia University bringing hands-on silicon learning to students worldwide."
+categories: [news]
+tags: [gf180mcu, run1, featured-project, mosbius]
+author: "Tim 'mithro' Ansell"
+badge_color: "bg-purple"
+slider_post: false
+trending: false
+sidebar: true
+permalink: "/news/mosbius-feature"
+post_image: "/assets/images/news/mosbius-feature/mosbius_flow.png"
+external_url: "https://www.crowdsupply.com/wafer-space/gf180mcu-run-1/updates/mosbius"
+galleries:
+ cob_design:
+ caption: "MOSbius custom COB package design"
+ images:
+ - img: "/assets/images/news/mosbius-feature/mos_pcb.png"
+ alt: "MOSbius custom COB PCB layout"
+ - img: "/assets/images/news/mosbius-feature/mos_3d.png"
+ alt: "MOSbius custom COB 3D board visualisation"
+---
+
+Our first shuttle run spans from solo makers like Tholin to universities. This week we highlight [MOSbius](https://mosbius.org/), an educational platform from Columbia University bringing hands-on silicon learning to students worldwide.
+
+Through wafer.space, MOSbius gains 3.3V compatible I/Os, high part counts, and COB packaging—all for a low cost. What was once an expensive demonstration can now equip every student in a classroom with their own chip, for less than the cost of a textbook.
+
+## [MOSbius](https://mosbius.org/)
+
+{% include image.html file="/assets/images/news/mosbius-feature/mosbius_flow.png" description="MOSbius platform enables hands-on exploration of transistor-level MOS circuits on breadboard" %}
+
+**[MOSbius](https://mosbius.org/)**, developed by **[Professor Peter Kinget](https://peterkinget.github.io/)** and his students at **[Columbia University](http://www.cisl.columbia.edu/kinget_group/)**, is an innovative educational platform that helps students and designers explore **MOS circuit topologies** typically found on silicon and now accessible on a breadboard.
+
+The goal of [MOSbius](https://mosbius.org/) is to give learners hands-on experience with **transistor-level design**, including circuit debugging, measurement, and the full "chip bring-up" process. The platform allows users to compare calculations, simulations, and real measurements using provided **[LTspice](https://wiki.analog.com/resources/tools-software/ltspice) models**, bridging the gap between theory and silicon.
+
+{% include youtube.html id="abu3u6UX6wE" autoplay=0 mute=0 controls=1 loop=0 caption="MOSbius - A Field Programmable Transistor Array for Chip Designers (Interview with Peter Kinget)" %}
+
+### Building on Previous Success
+
+MOSbius isn't new to custom silicon. Previous generations of the MOSbius chip demonstrated the educational value of hands-on transistor exploration, but faced a significant barrier: cost. At $50 per packaged chip, widespread educational deployment remained challenging.
+
+The project's educational impact extends beyond the classroom. The [IEEE SSCS Chipathon 2025](https://github.com/mosbiuschip/chipathon2025) featured a MOSbius track where students learned chip design using GF180MCU—the same process used by wafer.space. This gave Chipathon participants hands-on experience with the same technology they could use for future fabrication runs.
+
+### Their Own COB Format
+
+Given the unique requirements of the MOSbius project, the team is designing their own version of a **Chip-on-Board (COB)** package based on the [wafer.space standard padframe](https://www.crowdsupply.com/wafer-space/gf180mcu-run-1/updates/chip-on-board).
+
+Their application prioritizes **a high number of I/O connections** over power and ground pads, allowing for the maximum number of accessible signals from their transistor array.
+
+{% include post-gallery.html gallery="cob_design" %}
+
+
+**Peter's student, @xianglin_pui**, has taken the lead on this effort and developed derivative designs that extend the wafer.space COB standard for MOSbius's specialized needs.
+
+### wafer.space and MOSbius
+
+We're thrilled to have **MOSbius** as part of this shuttle run and proud to support a project that aligns so perfectly with wafer.space's mission.
+
+Their current board design requires numerous passive components due to varying pin voltage levels, and each packaged chip can cost upwards of **$50**. With their new design on the **[wafer.space](https://wafer.space/)** platform, all pins will be **3.3 V tolerant**, eliminating the need for numerous passive components and dramatically simplifying their demo board, while wafer.space's affordable pricing and **COB packaging** reduce costs.
+
+## Don't Miss Your Chance to Join the First Shuttle
+
+{% include image.html file="/assets/images/news/mosbius-feature/rainbow_narrow2.png" description="wafer.space - Accessible custom silicon fabrication" %}
+
+MOSbius is part of this run because accessible silicon enables their educational mission. What becomes possible at $7/chip? Whether you're building educational tools, [exploring new architectures](https://www.crowdsupply.com/wafer-space/gf180mcu-run-1/updates/openfasoc), or [bringing vintage designs back to life](https://www.crowdsupply.com/wafer-space/gf180mcu-run-1/updates/tholin-feature) - this is your opportunity.
+
+We're rapidly approaching the final milestones for this shuttle run, and now is the time to secure your spot:
+
+- **November 28, 2025** - Last day to purchase a slot / [Crowd Supply campaign](https://www.crowdsupply.com/wafer-space/gf180mcu-run-1) closes
+
+- **December 3, 2025** - [Final GDS submission deadline](https://wafer.space/how)
+
+If you’ve been thinking about getting your own silicon made — whether it’s your first chip or your fiftieth — this is your moment. The tools are ready, the ecosystem is growing, and we’re here to help you every step of the way.
+
+[Reserve your slot](https://www.crowdsupply.com/wafer-space/gf180mcu-run-1), finish your design, and join us in shaping the future of accessible custom silicon.
diff --git a/_posts/2025-11-22-tinytapeout-feature.md b/_posts/2025-11-22-tinytapeout-feature.md
new file mode 100644
index 00000000..967e9917
--- /dev/null
+++ b/_posts/2025-11-22-tinytapeout-feature.md
@@ -0,0 +1,121 @@
+---
+layout: "posts/post-boxed"
+title: "Tiny Tapeout"
+date: "2025-11-22 12:00:00 +0000"
+excerpt: "wafer.space is excited to have a Tiny Tapeout test design on our first shuttle! Tiny Tapeout has enabled thousands of people to create their own digital and analog designs."
+categories: [news]
+tags: [gf180mcu, run1, featured-project, tiny-tapeout]
+author: "Tim 'mithro' Ansell"
+badge_color: "bg-purple"
+slider_post: false
+trending: false
+sidebar: true
+permalink: "/news/tinytapeout-feature"
+post_image: "/assets/images/news/tinytapeout-feature/tinytapeout-logo.png"
+external_url: "https://www.crowdsupply.com/wafer-space/gf180mcu-run-1/updates/tiny-tapeout"
+galleries:
+ gds_renders:
+ caption: "GDS renders from Tiny Tapeout shuttles"
+ images:
+ - img: "/assets/images/news/tinytapeout-feature/tt03-gds.png"
+ alt: "GDS render of Tiny Tapeout TT03"
+ - img: "/assets/images/news/tinytapeout-feature/tt05-gds.png"
+ alt: "GDS render of Tiny Tapeout TT05"
+ - img: "/assets/images/news/tinytapeout-feature/tt06-gds.png"
+ alt: "GDS render of Tiny Tapeout TT06"
+ - img: "/assets/images/news/tinytapeout-feature/tt07-gds.png"
+ alt: "GDS render of Tiny Tapeout TT07"
+ - img: "/assets/images/news/tinytapeout-feature/tt09-gds.png"
+ alt: "GDS render of Tiny Tapeout TT09"
+ - img: "/assets/images/news/tinytapeout-feature/ttihp0p1-gds.png"
+ alt: "GDS render of Tiny Tapeout IHP 0.1"
+ - img: "/assets/images/news/tinytapeout-feature/ttsky25a-gds.png"
+ alt: "GDS render of Tiny Tapeout Sky130 25a"
+ - img: "/assets/images/news/tinytapeout-feature/ttsky25b-gds.png"
+ alt: "GDS render of Tiny Tapeout Sky130 25b"
+ sponsors:
+ caption: "Sponsored by Tillitis and WIT.com"
+ images:
+ - img: "/assets/images/news/tinytapeout-feature/tillitis-logo-std.png"
+ alt: "Tillitis logo"
+ - img: "/assets/images/news/tinytapeout-feature/witcom-logo-std.png"
+ alt: "WIT.com logo"
+---
+
+[wafer.space](https://wafer.space/) is excited to collaborate with [Tiny Tapeout](https://tinytapeout.com/) to port their infrastructure to GF180MCU. Founded by [Matt Venn](https://zerotoasiccourse.com/), Tiny Tapeout has become a cornerstone of the open-silicon movement, empowering students, hobbyists, and even industry professionals to design and fabricate their own ASICs through approachable tools and collaborative workflows. Our collaboration provides an easy and affordable pathway from initial ideas and prototyping to building real products.
+
+{% include image.html file="/assets/images/news/tinytapeout-feature/previous-tt-version.jpeg" description="With Tiny Tapeout, you get a ready-to-go development board" %}
+
+Tiny Tapeout has already proven that accessible chip design works. By dramatically lowering the barrier to entry, they've enabled thousands of participants to bring their digital and analog designs to life. Now, our collaboration aims to take that further, helping designs move from prototype to product. The track record speaks for itself:
+
+{% include post-gallery.html gallery="gds_renders" %}
+
+
+Building on this experience, **Tiny Tapeout** now joins wafer.space to bring GF180MCU into the mix. Our collaboration has enabled Tiny Tapeout to get exactly what they need from the [standard wafer.space padframe](https://www.crowdsupply.com/wafer-space/gf180mcu-run-1/updates/chip-on-board), ensuring full compatibility, consistent manufacturability, and reliable integration with COB-based packaging workflows.
+
+## What's Being Built on [GF0p2](https://app.tinytapeout.com/shuttles/ttgf0p2)
+
+Both Tiny Tapeout and wafer.space have been thrilled by the community response. The [GF0p2 shuttle](https://app.tinytapeout.com/shuttles/ttgf0p2) already has dozens of projects submitted, and more are coming in every day. Here are just a few of the designs being built:
+
+### Modern Free and Open Source Silicon Clone of Zilog's Z80
+
+[Rejunity](https://github.com/rejunity) is recreating [Zilog's Z80](https://app.tinytapeout.com/projects/3434) with the goal to develop a drop-in replacement for 8-bit home computers such as the ZX Spectrum and recent DIY computer kits such as the [RC2014](https://rc2014.co.uk/).
+
+
+### Tiny-QV: A RISC-V SoC for Tiny Tapeout
+
+[Tiny-QV](https://github.com/MichaelBell/tinyQV/) is a 4-bit-at-a-time RV32 processor, optimized for use on Tiny Tapeout with QSPI RAM and Flash. The aim is to make a small microcontroller that is as fast as practical given the Tiny Tapeout constraints.
+
+### Zedulo Test Chip
+
+[Zedulo TestChip1](https://github.com/ZeduloTech/ttgf-zed_tc1) is a UART-to-SPI bridge built using two IP blocks from the [OpenTitan](https://opentitan.org/) project (an open-source Root of Trust). By porting these OpenTitan components to GF180MCU, Zedulo demonstrates that verified, trustworthy hardware IP can be reused across different processes and platforms.
+
+### And Many More
+
+| Project | Description / Notes |
+| ---------------------------------------------------------------------------------------------- | ------------------------------------------------------------------------------------------------------------------------------- |
+| **[2x2 MAC Systolic array with DFT](https://app.tinytapeout.com/projects/3441)** | ASIC design for a 2x2 systolic matrix multiplier supporting multiply and accumulate operations on int8 data. |
+| **[WaferSpace VGA Screensaver](https://github.com/TinyTapeout/tt-waferspace-vga-screensaver)** | A classic animated VGA demo that prominently features the **wafer.space** logo — great for verifying display output and timing. |
+| **[Asicle v2 (2×2 tiles)](https://app.tinytapeout.com/projects/3248)** | A compact, tile-based modular layout design that explores reconfigurable logic or array instantiation. |
+| **[ROM / Memory Block (1×1)](https://app.tinytapeout.com/projects/3119)** | A read-only memory block intended for basic data storage — ideal for boot code or test vectors. |
+| **[Ring Oscillator (5-inverter, 1×1)](https://app.tinytapeout.com/projects/3125)** | A simple analog / digital hybrid circuit that toggles signal through five inverters to create a ring oscillator. |
+| **[Simon Says Logic Game](https://app.tinytapeout.com/projects/3121)** | Implements the classic “Simon Says” memory game in hardware logic — the chip will reproduce user-input sequences. |
+| **[Sound Generator (TBB143)](https://app.tinytapeout.com/projects/3430)** | A programmable sound generator that uses a ring oscillator to generate tones or effects. |
+
+The project tiles are filling up fast:
+
+{% include image.html file="/assets/images/news/tinytapeout-feature/current-run.png" description="Project tiles already allocated on the GF0p2 run" %}
+
+## Join Us!
+
+We're thrilled to have **Tiny Tapeout** and **Matt Venn** on board for our first wafer.space shuttle, but the most exciting part is having **you** join us too! Whether you're a complete beginner or an experienced designer, now is the perfect time to get started.
+
+Explore the [Tiny Tapeout website](https://tinytapeout.com/) for project ideas and tutorials, and watch the [YouTube channel](https://www.youtube.com/@ZeroToASICcourse) for walkthroughs and interviews. If you need something more structured, Matt's excellent [Zero to ASIC course](https://zerotoasiccourse.com/) will give you the knowledge and confidence to bring your ideas to silicon.
+
+Even if you haven't done a tapeout yet, join the community and start learning! Connect with us on the [wafer.space Discord](https://discord.gg/43y2t53jpE) and join the **#tinytapeout** channel, or the [Tiny Tapeout Discord](https://discord.gg/rPK2nSjxy8) and join the **#ttgf0p2-tapeout** channel. (You can also find us on [Matrix at #gf180mcu](https://matrix.to/#/#gf180mcu:fossi-chat.org).)
+
+With Tiny Tapeout, anyone can get started with just a web browser and a few hours. [Why not give it a try?](https://tinytapeout.com/)
+
+---
+
+## Don't Miss Your Chance to Join the First Shuttle
+
+{% include image.html file="/assets/images/news/tinytapeout-feature/waferspace-rainbow-open.png" description="wafer.space bringing open accessible custom silicon fabrication" %}
+We’re rapidly approaching the final milestones for this shuttle run, and now is the time to secure your spot:
+
+- **November 28, 2025** - Last day to purchase a slot (Crowd Supply campaign closes)
+
+- **December 3, 2025** - Final GDS submission deadline. Your design must be submitted to wafer.space by this date to be included in the run.
+
+If you've been thinking about getting your own silicon made, whether it's your first chip or your fiftieth, this is your moment. The tools are ready, the ecosystem is growing, and we’re here to help you every step of the way.
+
+Reserve your slot, finish your design, and join us in shaping the future of accessible custom silicon.
+
+---
+
+### Special Thanks
+
+{% include post-gallery.html gallery="sponsors" %}
+
+
+[Tillitis](https://www.tillitis.se/) and [WIT.com](https://wit.com/) generously sponsored the work to bring Tiny Tapeout to GF180MCU, its third process technology. This funding is enabling the [improved multiplexer](https://www.youtube.com/watch?v=30emLKLpq50), [power gating, analog support](https://www.youtube.com/watch?v=_m_jK7twymM), and [more](https://www.youtube.com/watch?v=cCbTyfewaCw) (designed by [Sylvain "tnt" Munaut](https://github.com/smunaut)) to be ported to GF180MCU. Thank you for making this happen!
diff --git a/_posts/2025-11-27-final-reminder.md b/_posts/2025-11-27-final-reminder.md
new file mode 100644
index 00000000..41741eae
--- /dev/null
+++ b/_posts/2025-11-27-final-reminder.md
@@ -0,0 +1,34 @@
+---
+layout: posts/post-boxed
+title: "Less than 48 hours to go!"
+date: 2025-11-27 12:00:00 +0000
+excerpt: "Less than 48 hours remain in the first shuttle campaign! If you hope to be on this shuttle, place your order now."
+categories: [news]
+tags: [gf180mcu, run1, deadline]
+author: "Tim 'mithro' Ansell"
+badge_color: "bg-purple"
+slider_post: false
+trending: false
+sidebar: true
+permalink: "/news/final-reminder"
+post_image: "/assets/images/news/final-reminder/waferspace-rainbow-open.png"
+external_url: "https://www.crowdsupply.com/wafer-space/gf180mcu-run-1/updates/less-than-48-hours"
+---
+
+Less than 48 hours remain in the first shuttle campaign! If you hope to be on this shuttle, place your order now. If you're facing purchasing obstacles, please don't hesitate to [get in touch](https://www.crowdsupply.com/wafer-space/gf180mcu-run-1/ask-question).
+
+**The Deadline: 28th November 2025 @ 11:59 PM [AoE](https://en.wikipedia.org/wiki/Anywhere_on_Earth)** ([see in your timezone](https://www.timeanddate.com/worldclock/fixedtime.html?iso=20251128T2359&p1=3399)) — After this deadline you'll be waiting until next year for the next shuttle run.
+
+## After You Purchase
+
+Once you've purchased your slot, you have until **3rd December 2025 @ 11:59 PM [AoE](https://en.wikipedia.org/wiki/Anywhere_on_Earth)** ([see in your timezone](https://www.timeanddate.com/worldclock/fixedtime.html?iso=20251203T2359&p1=3399)) to submit your GDS files.
+
+Run [gf180mcu-precheck](https://github.com/wafer-space/gf180mcu-precheck) locally to verify your design before submitting. The precheck has been and will continue to be updated, so join the [Discord](https://discord.gg/43y2t53jpE) to get notified of changes. This is the same DRC check that [platform.wafer.space](https://platform.wafer.space/) will run, so catching issues locally saves time.
+
+**Submit early!** The DRC queue will get busy as the deadline approaches. If you find problems at the last minute, you may not have time to fix them.
+
+If you run into issues, join the [wafer.space Discord](https://discord.gg/43y2t53jpE). Many people are putting the finishing touches on their designs right now, and problems you encounter have likely been solved by others who can offer guidance.
+
+{% include image.html file="/assets/images/news/final-reminder/waferspace-rainbow-open.png" description="wafer.space bringing open accessible custom silicon fabrication" %}
+
+**— Tim 'mithro' Ansell and the wafer.space Team**
diff --git a/_posts/2026-03-01-run2-coming-soon.md b/_posts/2026-03-01-run2-coming-soon.md
new file mode 100644
index 00000000..4386077d
--- /dev/null
+++ b/_posts/2026-03-01-run2-coming-soon.md
@@ -0,0 +1,70 @@
+---
+layout: posts/post-boxed
+title: "GF180MCU Run 2 is Coming!"
+date: 2026-03-01 12:00:00 +0000
+excerpt: "GF180MCU Run 2 is coming! Multiple slot sizes, improved DRC, better tooling, and early-bird pricing for Run 1 backers."
+categories: [news]
+tags: [gf180mcu, run2, crowd-supply]
+author: "Tim 'mithro' Ansell"
+post_image: "/assets/images/news/gf180mcu-gelpack-dice.jpg"
+badge_color: "bg-purple"
+slider_post: false
+trending: false
+sidebar: true
+permalink: "/news/run2-coming-soon"
+---
+
+Hey folks,
+
+We're pleased to announce that Run 2 is coming soon! Whether you followed Run 1 or this is your first time hearing about wafer.space, we are glad you are here.
+
+## What is wafer.space?
+
+[wafer.space](https://wafer.space/) is pooled silicon fabrication. Think [OSH Park](https://oshpark.com), but for custom chips instead of PCBs. You design a chip using GlobalFoundries' open [GF180MCU](https://gf180mcu-pdk.readthedocs.io/) PDK, submit your layout, and we handle fabrication, dicing, and delivery. $7 per chip, 1,000 chips per slot.
+
+The tools are open source. The PDK is open source. Your design can be open or closed. No NDAs required to get started.
+
+## Run 1: Designs on Silicon
+
+Run 1 closed in late November 2025 and the wafers are currently in production at GlobalFoundries. We filled the reticle with **many designs** from individuals, universities, startups, and community groups. 29 of those designs are public and available for you to study at [github.com/wafer-space/ws-run1](https://github.com/wafer-space/ws-run1).
+
+Some highlights from the run:
+
+- **KianV**: A 32-bit RISC-V SoC (RV32IMA with SV32 MMU) capable of running mainline Linux, built entirely with open-source tools.
+- **FABulous**: An open-source FPGA fabric with 480 LUT4s, programmable via Yosys and nextpnr. Yes, an FPGA implemented as an ASIC on an open PDK.
+- **Z80 Open Silicon**: A pin-compatible, open-source reimplementation of the classic Zilog Z80, targeting drop-in compatibility with vintage 8-bit computers.
+- **Tiny Tapeout GF**: The Tiny Tapeout multi-project chip ported to GF180MCU, with dozens of community designs packed onto a single die.
+- **ISHI-KAI**: 14 novice designers from the Japanese ISHI-KAI community submitted their first silicon designs together, creating analog circuits from inverters to PLLs.
+
+The range of projects was incredible: from production-ready SoCs to first-time tapeouts, from retro computing to cutting-edge research. That is exactly what accessible fabrication enables.
+
+## What is New in Run 2
+
+Run 2 builds on everything we learned from Run 1, with some significant improvements:
+
+- **Multiple slot sizes**: We are introducing quarter, half, and full slot options. Not every design needs 20 mm2. Smaller slots mean a lower cost of entry for simpler designs, while full slots remain available for larger projects.
+- **Improved DRC and submission platform**: The [platform.wafer.space](https://platform.wafer.space/) submission system has been refined based on Run 1 experience. Faster checks, clearer error messages, smoother workflow.
+- **Better tooling**: LibreLane, the project template, and the precheck tools all continue to improve. Every run makes the process smoother for the next one.
+- **Early-bird pricing**: Early supporters will be able to lock in discounted pricing. Stay subscribed for details.
+
+Things get better with every run. That is the whole point of building sustainable infrastructure.
+
+## Timeline
+
+The current target is a **2 July 2026 GDS submission deadline**, with the campaign closing on 30 June 2026. The campaign will go live well before that, giving you plenty of time to design, verify, and submit. Bare dies are expected to ship by mid-October 2026.
+
+Pricing details are coming soon. Subscribe to this campaign to be notified the moment we have them.
+
+## Get Involved Now
+
+You do not need to wait for the campaign to launch to start designing. The tools and PDK are available today:
+
+- **Start designing**: Clone the [gf180mcu-project-template](https://github.com/wafer-space/gf180mcu-project-template) and start experimenting. It includes a complete Nix environment with all the tools you need.
+- **Join the community**: The [wafer.space Discord](https://discord.gg/43y2t53jpE) is where designers help each other with pad rings, DRC issues, floorplanning, and everything in between. It is also the fastest way to get answers from the wafer.space team.
+- **Study Run 1 designs**: Browse the [29 public designs from Run 1](https://github.com/wafer-space/ws-run1) to see what fits in the die area and how others approached their layouts.
+
+The earlier you start, the more time you have to iterate. The best designs from Run 1 were the ones that started early and took advantage of community feedback.
+
+More updates coming soon with pricing details, slot sizes, and timeline specifics. Stay tuned.
+
+\- Tim 'mithro' Ansell
diff --git a/_posts/2026-04-17-run2-early-bird-warning.md b/_posts/2026-04-17-run2-early-bird-warning.md
new file mode 100644
index 00000000..d732eca7
--- /dev/null
+++ b/_posts/2026-04-17-run2-early-bird-warning.md
@@ -0,0 +1,47 @@
+---
+layout: posts/post-boxed
+title: "Two Weeks Left for Early Bird Pricing"
+date: 2026-04-17 12:00:00 +0000
+excerpt: "Early bird pricing for GF180MCU Run 2 ends on 30 April 2026. After that, prices go up."
+categories: [news]
+tags: [gf180mcu, run2, pricing]
+author: "Tim 'mithro' Ansell"
+post_image: "/assets/images/news/gf180mcu-gelpack-dice.jpg"
+badge_color: "bg-purple"
+slider_post: false
+trending: false
+sidebar: true
+permalink: "/news/run2-early-bird-warning"
+published: false
+---
+
+Quick reminder: early bird pricing for [wafer.space](https://wafer.space) GF180MCU Run 2 ends on **30 April 2026**. That is two weeks from now.
+
+After that, prices go up:
+
+| Slot | Early Bird | Standard |
+|------|-----------|----------|
+| 1x1 (full) | $7,000 ($7/die) | $7,500 ($7.50/die) |
+| 0.5x1 (half width) | $4,000 ($4/die) | $4,500 ($4.50/die) |
+| 1x0.5 (half height) | $4,000 ($4/die) | $4,500 ($4.50/die) |
+
+Every slot includes 1,000 dies.
+
+## Run 1 Status
+
+Run 1 bare dies are being sorted and prepared for shipping. We expect to start shipping soon and will share more details in the next update.
+
+## Getting Started with Run 2
+
+If you are considering a slot, now is the time to start:
+
+* Clone the [gf180mcu-project-template](https://github.com/wafer-space/gf180mcu-project-template) to start designing
+* Browse [29 open-source Run 1 designs](https://github.com/wafer-space/ws-run1) for reference
+* Join the [Discord](https://discord.gg/43y2t53jpE) to ask questions and connect with other designers
+* Check the [slot specifications](https://mithro.github.io/gf180mcu-project-template/) for padframe layouts and constraints
+
+The final deadline to purchase a slot and submit your GDS is **30 June 2026**.
+
+[Purchase your slot on Crowd Supply](https://www.crowdsupply.com/wafer-space/gf180mcu-run-2) before early bird pricing ends on 30 April.
+
+\- Tim 'mithro' Ansell
diff --git a/_posts/2026-05-07-run2-announcement.md b/_posts/2026-05-07-run2-announcement.md
new file mode 100644
index 00000000..c65f42ce
--- /dev/null
+++ b/_posts/2026-05-07-run2-announcement.md
@@ -0,0 +1,69 @@
+---
+layout: posts/post-boxed
+title: "GF180MCU Run 2 is Here!"
+date: 2026-05-17 12:00:00 +0000
+excerpt: "Run 2 is finally here with major improvements and early-bird pricing."
+categories: [news]
+tags: [gf180mcu, run1, run2]
+author: "Tim 'mithro' Ansell"
+post_image: "/assets/images/news/gf180mcu-gelpack-dice.jpg"
+badge_color: "bg-purple"
+slider_post: false
+trending: false
+sidebar: true
+permalink: "/news/run2-announcement"
+---
+
+Hey folks,
+
+Quick update from [wafer.space](https://wafer.space) with some news about what comes next.
+
+## Run 1 Status
+
+First things first: we've received your Run 1 wafers and have been hard at work at picking and sorting everyone's die.
+We've already shipped some bare die, and others have gotten a few packaged parts, so make sure to keep an eye on your
+inbox regarding any shipping notifications! While you're waiting, be sure to check out the behind the scenes pictures
+in our [update post](https://www.crowdsupply.com/wafer-space/gf180mcu-run-1/updates/wafers-received-sorting-robot-progress).
+
+## Run 2 is Here
+
+We have launched our second GF180MCU production run, building on everything we learned from Run 1. The submission
+platform, DRC tooling, and overall flow have all been improved based on real experience from this first shuttle. The
+goal is a smoother process for everyone.
+
+For those who are new here: we're on a mission to bring you affordable silicon. 1,000 dies now starting from just $4,500.
+That's $4.50 per die using GlobalFoundries' [GF180MCU](https://gf180mcu-pdk.readthedocs.io/) process. Real production
+quantities, not just a handful of prototypes.
+
+### What is New
+
+The biggest change for Run 2 is **multiple slot sizes**. In Run 1, every slot was the same size. For Run 2, we are
+introducing half and full slot options. Smaller slots mean a lower cost of entry, so if your design does not need the
+full 20 mm², you will not have to pay for it. This opens the door for more people to participate and for experienced
+designers to run smaller test structures alongside larger projects.
+
+We have also been working on improvements to the DRC checks, the submission platform, and the overall documentation.
+Many of these improvements came directly from feedback and issues that Run 1 participants encountered, so thank you for
+helping us make the process better.
+
+## Timeline
+
+The campaign closes on **30 June 2026**, with delivery of bare dies in Q4 2026. More details will be announced as we finalize things.
+
+## Get Involved
+
+If you are interested in Run 2, or if you want to share it with someone who missed Run 1, here is how to stay in the loop:
+
+- **Run 2 Launch Page**: [Visit our Crowd Supply page](https://www.crowdsupply.com/wafer-space/gf180mcu-run-2) for more information about Run 2 and how you can get started
+- **Discord**: [discord.gg/43y2t53jpE](https://discord.gg/43y2t53jpE)
+- **Matrix**: [#gf180mcu:fossi-chat.org](https://matrix.to/#/#gf180mcu:fossi-chat.org)
+
+## Thank You
+
+Run 1 would not exist without the people who backed it. You made the first [wafer.space](https://wafer.space) shuttle
+real, and that matters. The designs you submitted, the bugs you reported, the feedback you shared in Discord, the
+problems you solved for each other - all of it is what makes Run 2 possible and better.
+
+Whether you are planning to come back for Run 2 or just waiting for your Run 1 silicon to arrive, we appreciate you being part of this.
+
+\- Tim 'mithro' Ansell
diff --git a/_posts/2026-05-15-hackaday-2026.md b/_posts/2026-05-15-hackaday-2026.md
new file mode 100644
index 00000000..721d46d6
--- /dev/null
+++ b/_posts/2026-05-15-hackaday-2026.md
@@ -0,0 +1,23 @@
+---
+layout: posts/post-boxed
+title: "wafer.space @ Hackaday Europe 2026"
+date: 2026-05-15 12:00:00 +0000
+excerpt: "We're coming to Hackaday Europe 2026!"
+categories: [news]
+tags: [wafer-space, announcement]
+author: "Tim 'mithro' Ansell"
+post_image: "/assets/images/news/hackaday2026/thumbnail.jpg"
+badge_color: "bg-purple"
+slider_post: false
+trending: false
+sidebar: true
+permalink: "/news/wafer-space-at-hackaday-europe-2026"
+---
+
+Hey everybody, nice short announcement today.
+
+The [wafer.space](https://wafer.space) and [Tiny Tapeout](https://tinytapeout.com) teams will be attending [Hackaday
+Europe 2026](https://hackaday.io/europe2026/) in Lecco, Italy. If you're attending too, we'd love for you to come say hi
+and have a chat!
+
+That's all for now, talk soon.
\ No newline at end of file
diff --git a/_posts/2026-05-27-run1-wafers-arrived.md b/_posts/2026-05-27-run1-wafers-arrived.md
new file mode 100644
index 00000000..f4614d42
--- /dev/null
+++ b/_posts/2026-05-27-run1-wafers-arrived.md
@@ -0,0 +1,63 @@
+---
+layout: posts/post-boxed
+title: "Run 1 Wafers Have Arrived"
+date: 2026-05-27 12:00:00 +0000
+excerpt: "After 12 weeks at GlobalFoundries, the Run 1 wafers have been manufactured and returned. Your designs are now real silicon."
+categories: [news]
+tags: [gf180mcu, run1, manufacturing]
+author: "Tim 'mithro' Ansell"
+post_image: "/assets/images/news/run1-wafers-arrived/thumbnail.jpg"
+badge_color: "bg-purple"
+slider_post: false
+trending: false
+sidebar: true
+permalink: "/news/run1-wafers-arrived"
+galleries:
+ wafer-first-look:
+ caption: First look at the wafers
+ images:
+ - img: "/assets/images/news/run1-wafers-arrived/wafer-first-look.jpg"
+ alt: "Undiced Run 1 wafers"
+ - img: "/assets/images/news/run1-wafers-arrived/wafer-second-look.jpg"
+ alt: "Diced Run 1 wafers"
+ - img: "/assets/images/news/run1-wafers-arrived/wafer-closeup.jpg"
+ alt: "Close up of a diced wafer"
+---
+
+The wafers are here.
+
+After 12 weeks at GlobalFoundries, the Run 1 wafers have been manufactured and returned to us. This is the moment where
+your designs stop being GDSII files and start being real silicon.
+
+{% include image.html file="/assets/images/news/run1-wafers-arrived/tim-wafer-box.jpg" description="Tim 'mithro' Ansell
+with the box containing Run 1 wafers fresh from GlobalFoundries" %}
+
+## What Happens Next
+
+Each wafer is cut into individual dies, and those dies are sorted by our robot before being packed for shipping (we'll
+have a separate update about this robot out soon!). We've already started shipping bare dies and chip-on-board parts,
+so if you submitted a design on Run 1 then you should have already received some first samples. Keep an eye out for any
+shipping notifications.
+
+{% include post-gallery.html gallery="wafer-first-look" %}
+
+## Run 2 is Open
+
+If you missed Run 1 or want another slot, [Run 2 is now open on Crowd Supply](https://www.crowdsupply.com/wafer-space/gf180mcu-run-2). Run 2 slots are available until **30 June 2026**. Standard pricing is now in effect:
+
+* **1x1 (full) slot**: $7,500 ($7.50/die)
+* **0.5x1 (half width) slot**: $4,500 ($4.50/die)
+* **1x0.5 (half height) slot**: $4,500 ($4.50/die)
+
+Chip-on-board packaging is available as an add-on for $1,500 ($1.50/die).
+
+Every slot includes 1,000 dies. Half slots are new for Run 2.
+
+## Stay in Touch
+
+* **Discord**: [discord.gg/43y2t53jpE](https://discord.gg/43y2t53jpE)
+* **Matrix**: [#gf180mcu:fossi-chat.org](https://matrix.to/#/#gf180mcu:fossi-chat.org)
+
+Tune back in later for more updates.
+
+\- Tim 'mithro' Ansell
diff --git a/_posts/2026-05-29-sorting-bare-dies.md b/_posts/2026-05-29-sorting-bare-dies.md
new file mode 100644
index 00000000..3f55a92c
--- /dev/null
+++ b/_posts/2026-05-29-sorting-bare-dies.md
@@ -0,0 +1,67 @@
+---
+layout: posts/post-boxed
+title: "Die Sorting with Robots"
+date: 2026-05-29 12:00:00 +0000
+excerpt: "The Run 1 wafers are diced and the individual dies can now be sorted. Here is a look at the process."
+categories: [news]
+tags: [gf180mcu, run1, manufacturing]
+author: "Tim 'mithro' Ansell"
+post_image: "/assets/images/news/sorting-bare-dies/thumbnail.jpg"
+badge_color: "bg-purple"
+slider_post: false
+trending: false
+sidebar: true
+permalink: "/news/sorting-bare-dies"
+galleries:
+ wafer_progress:
+ caption: "Steady die picking progress"
+ images:
+ - img: "/assets/images/news/sorting-bare-dies/wafer-progress-0.jpg"
+ alt: "A few dies picked from each sector of the wafer"
+ - img: "/assets/images/news/sorting-bare-dies/wafer-progress-1.jpg"
+ alt: "More dies picked - this time forming Tetris-shaped L gaps"
+ - img: "/assets/images/news/sorting-bare-dies/wafer-progress-2.jpg"
+ alt: "A line of dies picked from each sector"
+ - img: "/assets/images/news/sorting-bare-dies/wafer-progress-3.jpg"
+ alt: "Progressing to the entire sector being picked clean"
+ - img: "/assets/images/news/sorting-bare-dies/wafer-progress-4.jpg"
+ alt: "A wafer fully picked - die test structures left behind in a skeleton-like grid structure"
+---
+
+The Run 1 wafers are diced and the individual dies can now be sorted. Here is a look at the process.
+
+{% include image.html file="/assets/images/news/run1-wafers-arrived/wafer-closeup.jpg" description="A diced wafer - note
+the score marks visible on the lower half"%}
+
+{% include image.html file="/assets/images/news/sorting-bare-dies/robot-picking-up-die.png" description="The die sorting
+robot picking up individual dies from the diced wafer" %}
+
+## How Die Sorting Works
+
+After the wafers are cut into individual dies, each die needs to be picked up, inspected, and placed into a tape-and-reel
+for shipping. This is handled by the sorting robot which works through the diced wafer one die at a time.
+
+Note the white layer of material under the wafer - this is tape. It holds the wafer together and the dies in place,
+since the wafer loses all rigidity after the dicing.
+
+{% include youtube.html id="ZBQ0eKzSZ8o" autoplay=true %}
+
+Eventually your die will end up in one of these reels.
+
+{% include youtube.html id="9acyV8S0Q74" autoplay=true %}
+
+{% include post-gallery.html gallery="wafer_progress" %}
+
+## Shipping Timeline
+
+We have started shipping bare dies and chip-on-board packaged dies. Some of you may have received shipping notifications, but be
+sure to keep an eye out.
+
+## Run 2 Reminder
+
+Run 2 is open until **30 June 2026**.
+
+* [Run 2 on Crowd Supply](https://www.crowdsupply.com/wafer-space/gf180mcu-run-2)
+* [Discord](https://discord.gg/43y2t53jpE)
+
+\- Tim 'mithro' Ansell
diff --git a/_posts/2026-06-03-chip-on-board-progress.md b/_posts/2026-06-03-chip-on-board-progress.md
new file mode 100644
index 00000000..fbf107a3
--- /dev/null
+++ b/_posts/2026-06-03-chip-on-board-progress.md
@@ -0,0 +1,167 @@
+---
+layout: posts/post-boxed
+title: "Chip-on-Board Packaging Progress"
+date: 2026-06-03 12:00:00 +0000
+excerpt: "Run 1 bare dies have shipped. Now we are working through chip-on-board packaging for customers who ordered that add-on."
+categories: [news]
+tags: [gf180mcu, run1, packaging, chip-on-board]
+author: "Tim 'mithro' Ansell"
+post_image: "/assets/images/news/chip-on-board-progress/thumbnail.jpg"
+badge_color: "bg-purple"
+slider_post: false
+trending: false
+sidebar: true
+permalink: "/news/chip-on-board-progress"
+galleries:
+ cob_panels:
+ caption: "Blank COB boards waiting for their die"
+ images:
+ - img: "/assets/images/news/chip-on-board-progress/cob-panel-front-back-view.jpg"
+ alt: "Two panels held side-by-side"
+ - img: "/assets/images/news/chip-on-board-progress/cob-single-top.jpg"
+ alt: "Top view of the board"
+ - img: "/assets/images/news/chip-on-board-progress/cob-single-bottom.jpg"
+ alt: "Bottom view of the board"
+ cob_bonds:
+ caption: "Tiny Tapeout's TTGF0p2 die fully wirebonded and ready for epoxy"
+ images:
+ - img: "/assets/images/news/chip-on-board-progress/cob-bonded-top-view.jpg"
+ alt: "Top view of TTGF0p2 on a black COB PCB"
+ - img: "/assets/images/news/chip-on-board-progress/cob-bonded-side-view.jpg"
+ alt: "Side view of TTGF0p2 on a black COB PCB"
+ cob_finished:
+ caption: "Finished COBs: wirebonded and epoxied, ready for your project"
+ images:
+ - img: "/assets/images/news/chip-on-board-progress/closeup-multiple-cobs.jpg"
+ alt: "Four COBs next to each other"
+ - img: "/assets/images/news/chip-on-board-progress/closeup-single-cob.jpg"
+ alt: "A single COB"
+ cloneless1_showcase:
+ caption: "Thorben Moos' Cloneless1 die in a ceramic package"
+ images:
+ - img: "/assets/images/news/chip-on-board-progress/cloneless1-closeup.jpg"
+ alt: "Closeup image of the Cloneless1 die"
+ - img: "/assets/images/news/chip-on-board-progress/cloneless1-breadboard.jpg"
+ alt: "Cloneless1 mounted in a ceramic package on a breadboard, wired to a microcontroller"
+
+---
+
+Run 1 bare dies and chips-on-board (COBs) have shipped - join us to have a look into the process.
+
+{% include image.html file="/assets/images/news/chip-on-board-progress/closeup-single-cob.jpg" description="A wafer.space die wirebonded to a PCB, covered in protective epoxy" %}
+
+## The Chip-on-Board Boards
+
+If you've been following along, you may remember a [previous update](/news/chip-on-board-strategy)
+where we discussed different potential strategies for chip-on-board packaging. In this update we will see all that hard
+work come to fruition, as we wirebond some of the very first dies from this run.
+
+The top-level view of the process is that each die is placed onto a small PCB and wirebonded to connect the die to the board.
+Then, an epoxy glob-top is applied to protect the sensitive die and wires. The result is a packaged part that you can
+plug into your own board and start testing immediately, no specialized equipment needed.
+
+Wirebonding is inaccessible for most people, and traditional packaging solutions remain cost prohibitive due to the low
+volume nature of the manufacturing runs. The COB boards were designed as an accessible way for people to use their
+wafer.space dies.
+
+These boards use an easily sourceable mezzanine connector for you to make your own motherboard. As always, the design
+of this COB is available on [GitHub](https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs).
+
+{% include post-gallery.html gallery="cob_panels" %}
+
+## Preparing for Wirebonding
+
+The COB boards arrive as a panel of 20 from the PCB house, but these are too large to fit onto the vacuum chuck used by
+the wirebonders. The solution is simple: snap the panels in half!
+
+{% include image.html file="/assets/images/news/chip-on-board-progress/cob-on-vacuum-chuck.jpg" description="Half-a-panel of COBs fixed to the vacuum chuck" %}
+
+Components moving during the wirebonding process is a concern. Tiny pads on the die and sharp movements caused by the
+wirebonder mean that any misalignment could result in a failed bond (or multiple). These failed bonds could prevent
+the chip from working properly, so our goal is to minimize any excessive movement.
+
+The PCB itself is affixed to the chuck using a vacuum, and the die is physically glued to the PCB.
+
+{% include image.html file="/assets/images/news/chip-on-board-progress/die-glueing-to-cob.jpg" description="wafer.space dies being glued to a COB board" %}
+
+{% include image.html file="/assets/images/news/chip-on-board-progress/cob-empty-vs-populated.jpg" description="An unpopulated COB (left) next to one with a die (right)" %}
+
+## Performing the Wirebonding
+
+Everything so far has been quite hands-on, and this is no different with the wirebonding machine. Before any bonding
+can take place, the machine must first be programmed with the desired locations and settings, and only then can it
+proceed. The machine operator is provided with a diagram showing all of our requested bonds, which they will interpret
+and configure the machine with.
+
+{% include image.html file="/assets/images/news/chip-on-board-progress/BTAP-wirebond-diagram.png" description="Example wirebonding diagram showcasing visual landmarks and bond locations" %}
+
+Since the die is mounted by hand, the machine uses a computer vision system to readjust the bond based on the visual
+location.
+
+{% include image.html file="/assets/images/news/chip-on-board-progress/wirebonder-operator.jpg" description="Wirebond operator configuring the bond path visually using a high-power microscope" %}
+
+{% include youtube.html id="TODO" caption="Wirebond operator programming the bonds the machine needs to perform" autoplay=true %}
+
+Now we're ready for the fun part! Once programmed, the machine will begin performing the wirebonding - all 74 pins.
+
+{% include post-gallery.html gallery="cob_bonds" %}
+
+We're not finished yet - the die and bonds are extremely fragile, so for them to survive the journey back to you, we must
+first cover them with an epoxy resin and bake them in the oven to harden.
+
+{% include post-gallery.html gallery="cob_finished" %}
+
+## Final Steps
+
+_Do they work?_
+
+...
+
+**Yes!!**
+
+We've been able to successfully run Tiny Tapeout's own factory test on their TTGF0p2 shuttle, and can confirm that it
+works as expected. We'd love to hear about your testing successes when you get your hands on your COBs, so please
+come join our community on [Discord](https://discord.gg/43y2t53jpE)!
+
+{% include youtube.html id="TODO" caption="Tiny Tapeout's TTGF0p2 factory test counting up (in binary, as shown on the LEDs)" autoplay=true %}
+
+
+That's not all though - check out this scrolling VGA screensaver with the [wafer.space](https://wafer.space) logo. You can
+view the source code for this on [GitHub](https://github.com/TinyTapeout/tt-waferspace-vga-screensaver), or experiment
+with it on [VGA Playground](https://vga-playground.com/?repo=https://github.com/TinyTapeout/tt-waferspace-vga-screensaver).
+
+{% include youtube.html id="TODO" caption="An animated wafer.space logo screensaver output over VGA" autoplay=true %}
+
+[Sylvain "tnt" Munaut](https://github.com/smunaut) has also been hard at work testing several designs onboard the TTGF0p2
+shuttle and reporting their status. You can view these on Tiny Tapeout's "Silicon Proven Projects" page - head to
+[tinytapeout.com/chips/silicon-proven/#ttgf0p2](https://tinytapeout.com/chips/silicon-proven/#ttgf0p2) to view the
+currently tested projects on TTGF0p2.
+
+If you'd like to see some more packaging goodness, Tiny Tapeout recently uploaded a video with some more behind the scenes
+footage for their TT08 shuttle.
+
+{% include youtube.html id="okJ7NFNJdfs" caption="Behind the scenes footage of TT08 being wirebonded" autoplay=false mute=false controls=true fs=true %}
+
+Of course, COBs aren't the only way to package your chip. Community member [Thorben Moos](https://www.thorbenmoos.de/)
+bonded their die to a stunning ceramic DIP, with others doing (or planning to do) their own bonding too.
+
+{% include post-gallery.html gallery="cloneless1_showcase" %}
+
+## Shipping Timeline
+
+COB packaged parts have started to ship. You will receive a notification from Crowd Supply when your order is on its way.
+
+## Run 2: Slots Still Available
+
+Run 2 slots are available on Crowd Supply until **30 June 2026**. Standard pricing is now in effect:
+
+* **1x1 (full) slot**: $7,500 ($7.50/die)
+* **0.5x1 (half width) slot**: $4,500 ($4.50/die)
+* **1x0.5 (half height) slot**: $4,500 ($4.50/die)
+
+Chip-on-board packaging is available as an add-on for $1,500 ($1.50/die).
+
+* [Run 2 on Crowd Supply](https://www.crowdsupply.com/wafer-space/gf180mcu-run-2)
+* [Discord](https://discord.gg/43y2t53jpE)
+
+\- Tim 'mithro' Ansell
diff --git a/_posts/2026-06-05-kianv-riscv-soc.md b/_posts/2026-06-05-kianv-riscv-soc.md
new file mode 100644
index 00000000..c9e78712
--- /dev/null
+++ b/_posts/2026-06-05-kianv-riscv-soc.md
@@ -0,0 +1,165 @@
+---
+layout: "posts/post-boxed"
+title: "Taping Out KianV - a Linux/XV6-capable RISC-V SoC"
+date: "2026-06-05 12:00:00 +0000"
+excerpt: "KianV is a RISC-V SoC capable of running µLinux, Linux, and XV6. Taped out using a fully open-source ASIC flow."
+categories: [news]
+tags: [gf180mcu, run1, featured-project, risc-v, kianv]
+author: "Hirosh Dabui"
+badge_color: "bg-purple"
+slider_post: false
+trending: false
+sidebar: true
+permalink: "/news/kianv-riscv-soc"
+post_image: "/assets/images/news/kianv-riscv-soc/thumbnail.jpg"
+galleries:
+ pcb_views:
+ caption: "KianV bring-up PCB"
+ images:
+ - img: "/assets/images/news/kianv-riscv-soc/pcb_top.png"
+ alt: "Bring-up PCB - top view"
+ - img: "/assets/images/news/kianv-riscv-soc/pcb_bottom.png"
+ alt: "Bring-up PCB - bottom view"
+---
+
+Hi everybody!
+
+In this update we'll be exploring a homegrown SoC which is capable of booting Linux, µLinux and XV6. It
+implements the RISC-V RV32IMA ISA alongside additional extensions for more functionality.
+
+If you'd like to explore the design, the source is available on the author's GitHub: [github.com/splinedrive/kianRiscV](https://github.com/splinedrive/kianRiscV)
+
+In addition to the ASIC, a compact bring-up PCB was designed to enable hardware validation and early software development.
+
+## SoC Overview
+
+The KianV SoC is built around an RV32IMA core - that's a 32-bit base with integer multiplication & division (`M`) and
+atomic instructions (`A`) extensions. In addition to those, it has support for [Zicntr](https://docs.riscv.org/reference/isa/unpriv/counters.html#7-1-1-zicntr-extension-for-base-counters-and-timers), [Zicsr](https://docs.riscv.org/reference/isa/unpriv/zicsr.html#csrinsts),
+[Zifencei](https://docs.riscv.org/reference/isa/unpriv/zifencei.html#zifencei), [SSTC](https://docs.riscv.org/reference/isa/priv/sstc.html#Sstc) and
+[Sv32](https://docs.riscv.org/reference/isa/priv/supervisor.html#sv32).
+
+
+The Sv32 extension allows KianV to access memory - this is done using a page-based 32-bit virtual memory system,
+which then interacts with 32MiB of external memory through an on-board SDRAM controller.
+
+The CPU itself includes a 2-way set-associative instruction cache, a direct-mapped data cache, and 4-way associative
+instruction and data TLBs, sufficient for MMU-based operating systems.
+
+Furthermore, KianV integrates a minimal peripheral set connected via an internal system bus. The peripherals are listed below:
+
+- SDRAM controller (interacting with 32 MiB external memory)
+- UART
+- 2× SPI interfaces
+- GPIO
+- NOR flash controller
+
+With these peripherals, the system is capable of booting from an external SD card and accessing networked resources via
+an SPI-based Ethernet connection. A system like this may find uses in a variety of situations: industrial, IoT or educational.
+
+{% include image.html file="/assets/images/news/kianv-riscv-soc/soc-overview.svg" description="Block diagram of the KianV RV32 SV32-capable RISC-V SoC" %}
+
+## Pinout
+
+The pinout is designed around a strict 58 external IO signal limit, all divided between the peripherals mentioned
+beforehand. The [wafer.space template](https://github.com/wafer-space/gf180mcu-project-template) provides access to 74
+pads, however these also include power and ground connections.
+
+{% include image.html file="/assets/images/news/kianv-riscv-soc/chip_symbol.png" description="KianV SoC external IO pinout" %}
+
+| Interface | Signals | Dir | Description |
+|:---------:|-------------------------------|:---:|--------------------|
+| **UART** | `RX`, `TX` | I/O | Serial console |
+| **SPI0** | `CS#`, `SCLK`, `MOSI`, `MISO` | I/O | SD card |
+| **SPI1** | `CS#`, `SCLK`, `MOSI`, `MISO` | I/O | Ethernet |
+| **Flash** | `CS#`, `SCLK`, `MOSI`, `MISO` | I/O | SPI NOR flash |
+| **SDRAM** | `CLK`, `CKE` | Out | Clocking |
+| | `ADDR[12:0]` | Out | Address bus |
+| | `BA[1:0]` | Out | Bank select |
+| | `DQ[15:0]` | I/O | Data bus |
+| | `DQM[1:0]` | Out | Byte mask |
+| | `CS#`, `RAS#`, `CAS#`, `WE#` | Out | Control signals |
+| **GPIO** | `GPIO0` | I/O | General-purpose IO |
+
+*Signals are grouped by function; directions are given from the SoC perspective.*
+
+---
+
+## Design Philosophy
+
+The RISC-V processor in this SoC is a multi-cycle RV32 core, optimized for area. The architecture was validated
+prior to taping out on FPGA platforms, where SV32-capable mainline Linux and network connectivity were demonstrated.
+
+Likewise, a µLinux (no-MMU) version of the KianV SoC was fabricated on multiple shuttles run by Tiny Tapeout, providing
+silicon validation of the core and peripheral subsystems. You can view these submissions online on the Tiny Tapeout
+website: [TTSky25a](https://tinytapeout.com/chips/ttsky25a/tt_um_kianV_rv32ima_uLinux_SoC), [TTIHP25b](https://tinytapeout.com/chips/ttihp25b/tt_um_kianV_rv32ima_uLinux_SoC),
+[TTSky25b](https://tinytapeout.com/chips/ttsky25b/tt_um_kianV_rv32ima_uLinux_SoC) and [TTIHP26a](https://tinytapeout.com/chips/ttihp26a/tt_um_kianv_sv32_soc).
+
+KianV is also mentioned in a [FOSSi Foundation article](https://fossi-foundation.org/blog/2025-01-14-ecl82) and
+referenced in an [IEEE Solid-State Circuits Magazine publication](https://ieeexplore.ieee.org/document/10584359).
+
+{% include image.html file="/assets/images/news/kianv-riscv-soc/tt_ulinux_soc_kianv.png" description="SkyWater 130 nm die layout of the Tiny Tapeout KianV uLinux (no-MMU) SoC" %}
+
+## Design Flow
+
+KianV was brought to life using **LibreLane** and the **[wafer.space GF180MCU project template](https://github.com/wafer-space/gf180mcu-project-template)**,
+which was then submitted to Run 1, and manufactured using the GlobalFoundries 180 nm PDK.
+
+The flow provided by the project template covers everything you'd need to produce and successfully tapeout a design. It
+contains software for RTL synthesis, floorplanning, place-and-route, clock tree synthesis and physical verification
+using known open-source tools.
+
+## Implementation Results
+
+Linux was booted in a gate-level simulation which painstakingly ran for an entire month before reaching the login prompt.
+This was using the mainline 6.19 version of the Linux kernel, and was validated against a Micron SDRAM simulation model
+driven by the author's SDRAM controller.
+
+Run 1 silicon is being shipped as we speak, so why not join our [Discord](https://discord.gg/43y2t53jpE) or [Matrix](https://matrix.to/#/#gf180mcu:fossi-chat.org)
+channels to see some silicon validation?
+
+KianV was taped out onto a full-sized die (20.1 mm²), with an approximate core utilization of 65% and an estimated
+~13 mW of power consumption.
+
+{% include image.html file="/assets/images/news/kianv-riscv-soc/chip_top_white.png" description="KianV chip layout: cache SRAM blocks surround the central core, with peripherals and IO placed around the perimeter" %}
+
+## Design Validation PCB
+
+As mentioned in the introduction, a small bring-up PCB was designed to support validation and software bring-up.
+
+The board provides a number of supporting components, such as the 32 MiB of SDRAM, an SPI-based Ethernet connection,
+SPI flash, SPI SD card interface, UART access and a power supply.
+
+This PCB is available to view on GitHub too: [github.com/splinedrive/gf180mcu-kianv-pcb](https://github.com/splinedrive/gf180mcu-kianv-pcb)
+
+{% include post-gallery.html gallery="pcb_views" %}
+
+## Software Status
+
+KianV uses a custom bootloader, followed by [OpenSBI](https://github.com/riscv-software-src/opensbi), and then boots
+the Linux kernel. Only minimal driver adaptations were required to boot mainline Linux with Sv32 MMU support on the SoC.
+
+In addition to Linux, the system also runs µLinux and XV6 on the same hardware platform.
+
+{% include image.html file="/assets/images/news/kianv-riscv-soc/console.png" description="Linux 6.19.0-rc1 booting on KianV, with the wafer.space logo being drawn to the terminal" %}
+
+## Acknowledgments
+
+- **Andrew Wingate** - Board design review (wafer.space)
+- **Christian Stredicke** - Voida PBX
+- **Goran Maholvic** - Board design support and SDRAM routing
+- **Leo Moser** - ASIC flow and PDK support (wafer.space)
+- **Marcelo Samsoniuk** - For the technical and personal exchange over the past few years (DarkRiscV)
+- **Matt Venn** - Tiny Tapeout
+- **Sylvain Munaut** - Tiny Tapeout
+- **Tim Ansell** - Founder of wafer.space
+- **Uri Shaked** - Tiny Tapeout
+
+## Additional Resources
+
+- KianV SoC Design: [github.com/splinedrive/gf180mcu-kianv-rv32ima-sv32](https://github.com/splinedrive/gf180mcu-kianv-rv32ima-sv32)
+- Bring-up PCB Design: [github.com/splinedrive/gf180mcu-kianv-pcb](https://github.com/splinedrive/gf180mcu-kianv-pcb)
+- Carl Karsten - Online access to FPGAs (with ASICs coming soon): [https://ps1.fpgas.online/](https://ps1.fpgas.online/)
+- Matt Venn - RISC-V/Open Source Silicon Stream updates: [linkedin.com/posts/matt-venn_riscv-opensourcesiliconstream-activity-7290765655132274690-Hfgw](https://www.linkedin.com/posts/matt-venn_riscv-opensourcesiliconstream-activity-7290765655132274690-Hfgw)
+- Matt Venn - Tiny Tapeout ASIC/Open Source development: [linkedin.com/posts/matt-venn_asic-opensource-riscv-activity-7279556029233704960-d5ZO](https://www.linkedin.com/posts/matt-venn_asic-opensource-riscv-activity-7279556029233704960-d5ZO)
+- Uri Shaked - Tiny Tapeout project update: [linkedin.com/feed/update/urn:li:activity:7312742011252490240/](https://www.linkedin.com/feed/update/urn:li:activity:7312742011252490240/)
+- Zero to ASIC Course 2024 Highlights: [zerotoasiccourse.com/post/year_update_2024/#2024-highlights](https://www.zerotoasiccourse.com/post/year_update_2024/#2024-highlights)
diff --git a/assets/css/custom.css b/assets/css/custom.css
index a49c7ede..891a71a6 100644
--- a/assets/css/custom.css
+++ b/assets/css/custom.css
@@ -428,6 +428,40 @@
font-size: 1.1rem;
}
+/* ── News listing grid: equal card heights ── */
+/* Constrain hero image thumbnails to consistent aspect ratio */
+.blog.grid .post figure.main {
+ height: 200px;
+ overflow: hidden;
+}
+
+.blog.grid .post figure.main img {
+ width: 100%;
+ height: 100%;
+ object-fit: cover;
+}
+
+/* Ensure isotope grid items stretch to equal row height */
+.blog.grid .item.post {
+ display: flex;
+ flex-direction: column;
+}
+
+.blog.grid .item.post > .box {
+ display: flex;
+ flex-direction: column;
+ flex: 1;
+}
+
+.blog.grid .item.post .post-content {
+ flex: 1;
+}
+
+/* ── News listing: prevent author byline from wrapping mid-phrase ── */
+.blog.grid .meta .author {
+ white-space: nowrap;
+}
+
/* Footnote styling for tables */
.table-footnote {
font-size: 0.8rem;
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