SimpleOp.vhd.bak

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY RealControlUnit IS
	GENERIC (
		FUNCTION_SIZE : INTEGER := 4;
		REGISTER_SIZE : INTEGER := 16
	);
	PORT (
		CLOCK : IN STD_LOGIC;
		ENABLE : IN STD_LOGIC;
		RESET : IN STD_LOGIC;
		FUNCTION_IN : IN STD_LOGIC_VECTOR(FUNCTION_SIZE + 5 DOWNTO 0);
		
		R_IN : STD_LOGIC_VECTOR(7 DOWNTO 0);
		A_IN, G_IN : STD_LOGIC;
		
		D_OUT : STD_LOGIC;
		R_OUT : STD_LOGIC_VECTOR(7 DOWNTO 0)
	);
END RealControlUnit;

ARCHITECTURE dataflow OF RealControlUnit IS

	-- FUNCTION CACHE
	COMPONENT FunctionCache IS
	GENERIC (
		SIZE : INTEGER := FUNCTION_SIZE + REGISTER_SIZE + 3
	);
	PORT (
		CLOCK : IN STD_LOGIC;
		FUNCTION_IN : IN STD_LOGIC_VECTOR(SIZE - 1 DOWNTO 0);
		FLUSH_FUNCTION : IN STD_LOGIC;
		FUNCTION_OUT : OUT STD_LOGIC_VECTOR(SIZE - 1 DOWNTO 0)
	);
	END COMPONENT;
	
	-- PROGRAM COUNTER
	COMPONENT ProgramCounter IS
	PORT (
		CLOCK : IN STD_LOGIC;
		CLEAR : IN STD_LOGIC;
		COUNT_NOW : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
	);
	END COMPONENT;
	
	-- 2 TO 4 DECODER
	COMPONENT Det2To4 IS
	PORT (
		ENABLE : IN STD_LOGIC;
		DATA_IN : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
		DATA_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
	);
	END COMPONENT;
	
	-- 3 TO 8 DECODER
	COMPONENT Det3To8 IS
	PORT (
		ENABLE : IN STD_LOGIC;
		DATA_IN : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
		DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
	);
	END COMPONENT;
	
	-- 4 TO 16 DECODER
	COMPONENT Det3To8 IS
	PORT (
		ENABLE : IN STD_LOGIC;
		DATA_IN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
		DATA_OUT : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
	);
	END COMPONENT;
	
	------------------
	-- SIGNAL START --
	------------------
	
	-- FLUSH DATA SIGNAL
	SIGNAL FLUSH_FUNCTION : STD_LOGIC;
	-- FUNCTION SIGNAL
	SIGNAL CACHE_FUNCTION, FINAL_FUNCTION : STD_LOGIC_VECTOR(FUNCTION_SIZE + 5 DOWNTO 0);
	-- PROGRAM COUNTER CLEAR SIGNAL
	SIGNAL CLEAR : STD_LOGIC;
	-- PROGRAM COUNTER STEP
	SIGNAL STEP_NUM : STD_LOGIC_VECTOR(1 DOWNTO 0);
	SIGNAL STEP : STD_LOGIC_VECTOR(3 DOWNTO 0);
	-- PROCESS DOWN SIGNAL
	SIGNAL DONE : STD_LOGIC;
	
	-- FUNCTION SIGNAL
	SIGNAL COMMAND_NUM : STD_LOGIC_VECTOR(3 DOWNTO 0);
	SIGNAL X_NUM : STD_LOGIC_VECTOR(2 DOWNTO 0);
	SIGNAL Y_NUM : STD_LOGIC_VECTOR(2 DOWNTO 0);
	
	SIGNAL COMMAND : STD_LOGIC_VECTOR(15 DOWNTO 0);
	SIGNAL X : STD_LOGIC_VECTOR(7 DOWNTO 0);
	SIGNAL Y : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
	
	-- DETECT WHTHER CLEAR PROGRAM COUNTER
	CLEAR <= DONE OR (NOT(ENABLE) AND STEP(0));
	
	-- DETECT WHTHER ASSIGN NEW FUNCTION CACHE DATA
	FLUSH_FUNCTION <= DONE AND STEP(0);
	
	-- CHOOSE NEW FUNCTION OR CACHE FUNCTION
	FINAL_FUNCTION <= FUNCTION_IN WHEN STEP(0) ELSE CACHE_FUNCTION;
	
	-- SET COMMAND SIGNAL
	COMMAND_NUM <= FINAL_FUNCTION(FUNCTION_SIZE + 5 DOWNTO 6);
	X_NUM <= FUNCTION_SIZE(5 DOWNTO 3);
	Y_NUM <= FUNCTION_SIZE(2 DOWNTO 0);
	
	-- FUNCTION CACHE INSTANCE
	FUNCTION_CACHE_ENTITY : FunctionCache
	GENERIC MAP (
		SIZE => FUNCTION_SIZE + REGISTER_SIZE + 2
	)
	PORT MAP (
		CLOCK,
		FUNCTION_IN,
		FLUSH_DATA,
		CACHE_FUNCTION
	);	
	
	-- PROGRAM COUNTER INSTANCE
	PRO_COUNTER : ProgramCounter PORT MAP (CLOCK, CLEAR, STEP_NUM);
	
	-- PROGRAM COUNTER DECODER
	COUNTER_DECODER : Det2To4 PORT MAP ('1', STEP_NUM, STEP);
END dataflow;