Bug in SPI Clock Pin Configuration for the nrf

[T-joma]

Hello,
I assume that there is a bug in the SPI clock pin configuration for the nrf MCUs. The following pictures show the SPi settings and recorded transmission. The settings for the transmission are SPI_MODE_HIGH_FIRST = active High and Leading Edge = CPOL 0 and CPHA 0

You can see that there is a high on the clock pin before and after the transmission that should not be there.
I assume that the pin configuration in line 58 and 62 in the file "wm-sdk/mcu/nrf/common/hal/spi.c" needs to be swapped.

wm-sdk/mcu/nrf/common/hal/spi.c

Lines 55 to 63 in 1c16d46

	// Configure clock pin (depending on mode)
	if (mode == SPI_MODE_LOW_FIRST || mode == SPI_MODE_LOW_SECOND)
	{
	nrf_gpio_pin_clear(BOARD_SPI_SCK_PIN);
	}
	else
	{
	nrf_gpio_pin_set(BOARD_SPI_SCK_PIN);
	}

The picture below shows the recording of the SPI transmission with fixed clock pin configuration.

[electrokean]

Encountered the same issue.

The incorrect initial pin state causes an extra clock pulse because we are not currently using chip select.