From 73f7f92218ff8329660413798aae280259c44d7d Mon Sep 17 00:00:00 2001 From: alexyiuxmos Date: Thu, 16 Jul 2026 14:44:47 +0100 Subject: [PATCH 1/9] change the TEST_LEVEL to default in jenkinsfile --- Jenkinsfile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Jenkinsfile b/Jenkinsfile index 01b1718..553c82a 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -24,7 +24,7 @@ pipeline { description: 'The infr_apps version' ) choice( - name: 'TEST_LEVEL', choices: ['smoke', 'default', 'extended'], + name: 'TEST_LEVEL', choices: ['default', 'smoke', 'extended'], description: 'The level of test coverage to run' ) } @@ -85,6 +85,7 @@ pipeline { stage('Tests') { steps { + echo "TEST_LEVEL: ${params.TEST_LEVEL}" dir("${REPO_NAME}/tests") { withTools(params.TOOLS_VERSION) { createVenv(reqFile: "requirements.txt") From 782873b462437b1dc438b7f44a187d91f414d3d4 Mon Sep 17 00:00:00 2001 From: alexyiuxmos Date: Mon, 20 Jul 2026 08:09:40 +0100 Subject: [PATCH 2/9] added xcore_ai_sdram_test_board xn file --- examples/app_sdram_demo/CMakeLists.txt | 4 +- examples/app_sdram_demo/src/sdram_demo.xc | 3 +- .../xcore_ai_sdram_test_board.xn | 55 +++++++++++++++++++ tests/sdram_benchmark/CMakeLists.txt | 4 +- tests/sdram_benchmark/src/sdram_bench.xc | 4 +- .../xcore_ai_sdram_test_board.xn | 55 +++++++++++++++++++ tests/sdram_multi_client_test/CMakeLists.txt | 4 +- .../src/sdram_multi_client_test.xc | 4 +- .../xcore_ai_sdram_test_board.xn | 55 +++++++++++++++++++ tests/sdram_testbench/CMakeLists.txt | 4 +- tests/sdram_testbench/src/sdram_testbench.xc | 4 +- .../xcore_ai_sdram_test_board.xn | 55 +++++++++++++++++++ 12 files changed, 243 insertions(+), 8 deletions(-) create mode 100644 examples/app_sdram_demo/xcore_ai_sdram_test_board.xn create mode 100644 tests/sdram_benchmark/xcore_ai_sdram_test_board.xn create mode 100644 tests/sdram_multi_client_test/xcore_ai_sdram_test_board.xn create mode 100644 tests/sdram_testbench/xcore_ai_sdram_test_board.xn diff --git a/examples/app_sdram_demo/CMakeLists.txt b/examples/app_sdram_demo/CMakeLists.txt index 87b044e..82ce4f4 100644 --- a/examples/app_sdram_demo/CMakeLists.txt +++ b/examples/app_sdram_demo/CMakeLists.txt @@ -2,7 +2,9 @@ cmake_minimum_required(VERSION 3.21) include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) project(sdram_demo) -set(APP_HW_TARGET SLICEKIT-XC200-X1.xn) +# set(APP_HW_TARGET SLICEKIT-XC200-X1.xn) +set(APP_HW_TARGET xcore_ai_sdram_test_board.xn) +set(APP_XSCOPE_SRCS "") set(APP_DEPENDENT_MODULES "lib_sdram") set(APP_COMPILER_FLAGS -g -O2) diff --git a/examples/app_sdram_demo/src/sdram_demo.xc b/examples/app_sdram_demo/src/sdram_demo.xc index 2942b09..7ceb266 100644 --- a/examples/app_sdram_demo/src/sdram_demo.xc +++ b/examples/app_sdram_demo/src/sdram_demo.xc @@ -9,7 +9,8 @@ //For XS2 (xCORE200) put an SDRAM slice into the 'triangle' slot of tile 0 of the XP-SKC-X200 slice kit //If using 256Mb slice, then define USE_256Mb below, otherwise leave commented out -#define USE_256Mb 1 //Else will assume 64Mb +#define USE_256Mb 0//1 //Else will assume 64Mb +#define JTAG_TO_PRINT 1 void application(streaming chanend c_server) { #define BUF_WORDS (16) diff --git a/examples/app_sdram_demo/xcore_ai_sdram_test_board.xn b/examples/app_sdram_demo/xcore_ai_sdram_test_board.xn new file mode 100644 index 0000000..1eac885 --- /dev/null +++ b/examples/app_sdram_demo/xcore_ai_sdram_test_board.xn @@ -0,0 +1,55 @@ + + + Board + xcore-ai SDRAM Test Board + + + tileref tile[2] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/tests/sdram_benchmark/CMakeLists.txt b/tests/sdram_benchmark/CMakeLists.txt index 7968d21..0009a71 100644 --- a/tests/sdram_benchmark/CMakeLists.txt +++ b/tests/sdram_benchmark/CMakeLists.txt @@ -2,7 +2,9 @@ cmake_minimum_required(VERSION 3.21) include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) project(sdram_benchmark) -set(APP_HW_TARGET SLICEKIT-XC200-X1.xn) +# set(APP_HW_TARGET SLICEKIT-XC200-X1.xn) +set(APP_HW_TARGET xcore_ai_sdram_test_board.xn) +set(APP_XSCOPE_SRCS "") set(APP_DEPENDENT_MODULES "lib_sdram") set(APP_INCLUDES src) diff --git a/tests/sdram_benchmark/src/sdram_bench.xc b/tests/sdram_benchmark/src/sdram_bench.xc index 40ccc43..ac9d5a5 100644 --- a/tests/sdram_benchmark/src/sdram_bench.xc +++ b/tests/sdram_benchmark/src/sdram_bench.xc @@ -8,7 +8,7 @@ //For XS2 (xCORE200) put an SDRAM slice into the 'triangle' slot of tile 0 of the XP-SKC-X200 slice kit //If using 256Mb slice, then define USE_256Mb below, otherwise leave commented out -#define SDRAM_256Mb 1 //Use IS42S16160D 256Mb or similar +#define SDRAM_256Mb 0//1 //Use IS42S16160D 256Mb or similar #define SDRAM_128Mb 0 //Use IS42S16800D 128Mb //othewise IS42S16400D 64Mb which is default on XMOS boards #define CAS_LATENCY 2 @@ -16,6 +16,8 @@ #define CLOCK_DIV 4 //Note clock div 4 gives (500/ (4*2)) = 62.5MHz #define DATA_BITS 16 +#define JTAG_TO_PRINT 1 + #if SDRAM_256Mb #define REFRESH_CYCLES 8192 #define COL_ADDRESS_BITS 9 diff --git a/tests/sdram_benchmark/xcore_ai_sdram_test_board.xn b/tests/sdram_benchmark/xcore_ai_sdram_test_board.xn new file mode 100644 index 0000000..1eac885 --- /dev/null +++ b/tests/sdram_benchmark/xcore_ai_sdram_test_board.xn @@ -0,0 +1,55 @@ + + + Board + xcore-ai SDRAM Test Board + + + tileref tile[2] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/tests/sdram_multi_client_test/CMakeLists.txt b/tests/sdram_multi_client_test/CMakeLists.txt index b78805c..0f71061 100644 --- a/tests/sdram_multi_client_test/CMakeLists.txt +++ b/tests/sdram_multi_client_test/CMakeLists.txt @@ -2,7 +2,9 @@ cmake_minimum_required(VERSION 3.21) include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) project(sdram_multi_client_test) -set(APP_HW_TARGET SLICEKIT-XC200-X1.xn) +# set(APP_HW_TARGET SLICEKIT-XC200-X1.xn) +set(APP_HW_TARGET xcore_ai_sdram_test_board.xn) +set(APP_XSCOPE_SRCS "") set(APP_DEPENDENT_MODULES "lib_sdram") set(APP_INCLUDES src) diff --git a/tests/sdram_multi_client_test/src/sdram_multi_client_test.xc b/tests/sdram_multi_client_test/src/sdram_multi_client_test.xc index 1f0376e..f382697 100644 --- a/tests/sdram_multi_client_test/src/sdram_multi_client_test.xc +++ b/tests/sdram_multi_client_test/src/sdram_multi_client_test.xc @@ -7,9 +7,11 @@ //For XS2 (xCORE200) put an SDRAM slice into the 'triangle' slot of tile 0 of the XP-SKC-X200 slice kit //If using 256Mb slice, then define USE_256Mb below, otherwise leave commented out -#define SDRAM_256Mb 1 //Use IS42S16160D 256Mb +#define SDRAM_256Mb 0//1 //Use IS42S16160D 256Mb #define SDRAM_128Mb 0 //Use IS42S16800D 128Mb //othewise IS42S16400D 64Mb which is default on XMOS boards +#define JTAG_TO_PRINT 1 + #define CAS_LATENCY 2 #define REFRESH_MS 64 #define CLOCK_DIV 4 //Note clock div 4 gives (500/ (4*2)) = 62.5MHz diff --git a/tests/sdram_multi_client_test/xcore_ai_sdram_test_board.xn b/tests/sdram_multi_client_test/xcore_ai_sdram_test_board.xn new file mode 100644 index 0000000..1eac885 --- /dev/null +++ b/tests/sdram_multi_client_test/xcore_ai_sdram_test_board.xn @@ -0,0 +1,55 @@ + + + Board + xcore-ai SDRAM Test Board + + + tileref tile[2] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/tests/sdram_testbench/CMakeLists.txt b/tests/sdram_testbench/CMakeLists.txt index 66e8a48..9837768 100644 --- a/tests/sdram_testbench/CMakeLists.txt +++ b/tests/sdram_testbench/CMakeLists.txt @@ -2,7 +2,9 @@ cmake_minimum_required(VERSION 3.21) include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) project(sdram_testbench) -set(APP_HW_TARGET SLICEKIT-XC200-X1.xn) +# set(APP_HW_TARGET SLICEKIT-XC200-X1.xn) +set(APP_HW_TARGET xcore_ai_sdram_test_board.xn) +set(APP_XSCOPE_SRCS "") set(APP_DEPENDENT_MODULES "lib_sdram") set(APP_INCLUDES src) diff --git a/tests/sdram_testbench/src/sdram_testbench.xc b/tests/sdram_testbench/src/sdram_testbench.xc index cf98adc..23ce60d 100644 --- a/tests/sdram_testbench/src/sdram_testbench.xc +++ b/tests/sdram_testbench/src/sdram_testbench.xc @@ -12,9 +12,11 @@ #define VERBOSE_MSG 1 -#define SDRAM_256Mb 1 //Use IS42S16160D 256Mb +#define SDRAM_256Mb 0//1 //Use IS42S16160D 256Mb #define SDRAM_128Mb 0 //Use IS42S16800D 128Mb //othewise IS42S16400D 64Mb which is default on XMOS boards +#define JTAG_TO_PRINT 1 + #define FAST_TEST 1 //Simplify read and wait only 12 seconds instead of 120 for refresh tests #define CAS_LATENCY 2 diff --git a/tests/sdram_testbench/xcore_ai_sdram_test_board.xn b/tests/sdram_testbench/xcore_ai_sdram_test_board.xn new file mode 100644 index 0000000..1eac885 --- /dev/null +++ b/tests/sdram_testbench/xcore_ai_sdram_test_board.xn @@ -0,0 +1,55 @@ + + + Board + xcore-ai SDRAM Test Board + + + tileref tile[2] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file From ca78559a89534edd63715816e9a012d5893487e5 Mon Sep 17 00:00:00 2001 From: alexyiuxmos Date: Tue, 21 Jul 2026 12:39:40 +0100 Subject: [PATCH 3/9] updated the port settings --- Jenkinsfile | 10 +++-- examples/app_sdram_demo/src/sdram_demo.xc | 13 +++--- lib_sdram/src/io.S | 6 +-- lib_sdram/src/server.xc | 4 +- tests/sdram_benchmark/config.xscope | 4 +- tests/sdram_benchmark/src/sdram_bench.xc | 42 ++++++++++++------- tests/sdram_multi_client_test/config.xscope | 4 +- .../src/sdram_multi_client_test.xc | 42 +++++++++++++++---- tests/sdram_testbench/src/sdram_testbench.xc | 16 ++++--- .../xcore_ai_sdram_test_board.xn | 2 +- 10 files changed, 96 insertions(+), 47 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index 553c82a..e0bdb07 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -38,7 +38,7 @@ pipeline { stages { stage('🏗️ Build and test') { agent { - label 'x86_64 && linux && documentation' + label 'ah05-sdram0' } stages { @@ -91,8 +91,12 @@ pipeline { createVenv(reqFile: "requirements.txt") withVenv { xcoreBuild(archiveBins: false) - // Use the TEST_LEVEL parameter to control the test coverage - runPytest("--level=${params.TEST_LEVEL}") + dir("sdram_testbench") { + sh "xrun --xscope bin/sdram_testbench.xe" + } + dir("sdram_multi_client_test") { + sh "xrun --xscope bin/sdram_multe_client_test.xe" + } } } } diff --git a/examples/app_sdram_demo/src/sdram_demo.xc b/examples/app_sdram_demo/src/sdram_demo.xc index 7ceb266..be2f7e8 100644 --- a/examples/app_sdram_demo/src/sdram_demo.xc +++ b/examples/app_sdram_demo/src/sdram_demo.xc @@ -77,14 +77,14 @@ on tile[SERVER_TILE] : out buffered port:8 sdram_we = XS1_ on tile[SERVER_TILE] : out port sdram_clk = XS1_PORT_1L; on tile[SERVER_TILE] : clock sdram_cb = XS1_CLKBLK_2; #else -//Square slot on A16 slicekit +//Uses IS42S16400D 64Mb part supplied on AH05_SDRAM board #define SERVER_TILE 1 on tile[SERVER_TILE] : out buffered port:32 sdram_dq_ah = XS1_PORT_16A; -on tile[SERVER_TILE] : out buffered port:32 sdram_cas = XS1_PORT_1B; -on tile[SERVER_TILE] : out buffered port:32 sdram_ras = XS1_PORT_1G; -on tile[SERVER_TILE] : out buffered port:8 sdram_we = XS1_PORT_1C; +on tile[SERVER_TILE] : out buffered port:32 sdram_cas = XS1_PORT_1A; +on tile[SERVER_TILE] : out buffered port:32 sdram_ras = XS1_PORT_1P; +on tile[SERVER_TILE] : out buffered port:8 sdram_we = XS1_PORT_1M; on tile[SERVER_TILE] : out port sdram_clk = XS1_PORT_1F; -on tile[SERVER_TILE] : clock sdram_cb = XS1_CLKBLK_2; +on tile[SERVER_TILE] : clock sdram_cb = XS1_CLKBLK_1; #endif int main() { @@ -100,7 +100,8 @@ int main() { #if USE_256Mb 2, 256, 16, 9, 13, 2, 64, 8192, 4); //IS45S16160D 256Mb option or similar #else - 2, 128, 16, 8, 12, 2, 64, 4096, 4); //Uses IS42S16400D 64Mb part supplied on SDRAM slice + // 2, 128, 16, 8, 12, 2, 64, 4096, 4); //Uses IS42S16400D 64Mb part supplied on SDRAM slice + 2, 128, 16, 8, 12, 2, 64, 4096, 5); //Uses IS42S16400D 64Mb part supplied on AH05_SDRAM board #endif //Note clock div 4 gives (500/ (4*2)) = 62.5MHz diff --git a/lib_sdram/src/io.S b/lib_sdram/src/io.S index 71fcb27..67acafe 100644 --- a/lib_sdram/src/io.S +++ b/lib_sdram/src/io.S @@ -1,7 +1,7 @@ // Copyright 2014-2026 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. .text -#ifdef __XS2A__ +#if defined (__XS2A__) || defined (__XS3A__) //xCore 200 optimised version with support for >8bit row addresses .cc_top sdram_block_write.function .align 4 @@ -202,7 +202,7 @@ sdram_block_read: //r2 t0 - start time //r3 word_count //sp[1] row_words - //sp[2] cas_latency + //sp[2] read_time_offset #define ras r0 #define dq_ah r1 @@ -339,7 +339,7 @@ sdram_block_read: ldaw temp, r0[-temp] set dp, temp - ldw temp, sp[READ_STACK_WORDS+2] //cas_latency + ldw temp, sp[READ_STACK_WORDS+2] //read_time_offset add start_time, r2, temp //calculate the time to issue the terminate cmd diff --git a/lib_sdram/src/server.xc b/lib_sdram/src/server.xc index 9c072eb..b628b98 100644 --- a/lib_sdram/src/server.xc +++ b/lib_sdram/src/server.xc @@ -85,7 +85,7 @@ static unsigned sdram_init( case 5: // 500 / (5 * 2) = 50.00MHz. ~2.1ns margin read_delay_whole_clocks = 1; set_port_sample_delay(dq_ah); - set_pad_delay(dq_ah, 1); + set_pad_delay(dq_ah, 1); break; case 6: // 500 / (6 * 2) = 41.67MHz. ~4.1ns margin read_delay_whole_clocks = 1; @@ -459,7 +459,7 @@ void sdram_server(streaming chanend c_client[client_count], while (running) { #pragma ordered select { - case t when timerafter(time) :> unsigned handle_time :{ + case t when timerafter(time) :> unsigned handle_time :{ unsigned diff = handle_time - time; unsigned bursts = diff>>bits; refresh(MINIMUM_REFRESH_COUNT*bursts, cas, ras); diff --git a/tests/sdram_benchmark/config.xscope b/tests/sdram_benchmark/config.xscope index 29ab652..fd50384 100644 --- a/tests/sdram_benchmark/config.xscope +++ b/tests/sdram_benchmark/config.xscope @@ -1,2 +1,2 @@ - - + + diff --git a/tests/sdram_benchmark/src/sdram_bench.xc b/tests/sdram_benchmark/src/sdram_bench.xc index ac9d5a5..04162cf 100644 --- a/tests/sdram_benchmark/src/sdram_bench.xc +++ b/tests/sdram_benchmark/src/sdram_bench.xc @@ -13,10 +13,14 @@ //othewise IS42S16400D 64Mb which is default on XMOS boards #define CAS_LATENCY 2 #define REFRESH_MS 64 +#if defined (__XS2A__) #define CLOCK_DIV 4 //Note clock div 4 gives (500/ (4*2)) = 62.5MHz +#else +#define CLOCK_DIV 5 //Note clock div 5 gives (600/ (5*2)) = 60.0MHz +#endif #define DATA_BITS 16 -#define JTAG_TO_PRINT 1 +#define JTAG_IO_PRINT 1 #if SDRAM_256Mb #define REFRESH_CYCLES 8192 @@ -49,10 +53,10 @@ void application(streaming chanend c_server, s_sdram_state sdram_state) { #define BUF_WORDS (240) - unsigned buffer_0[ROW_WORDS]; - unsigned buffer_1[ROW_WORDS]; - unsigned buffer_2[ROW_WORDS]; - unsigned buffer_3[ROW_WORDS]; + unsigned buffer_0[BUF_WORDS]; + unsigned buffer_1[BUF_WORDS]; + unsigned buffer_2[BUF_WORDS]; + unsigned buffer_3[BUF_WORDS]; unsigned * movable buffer_pointer_0 = buffer_0; unsigned * movable buffer_pointer_1 = buffer_1; @@ -64,19 +68,19 @@ void application(streaming chanend c_server, s_sdram_state sdram_state) { #define SECONDS 2 unsigned words_since_timeout = 0; t :> time; - sdram_read(c_server, sdram_state, 0, ROW_WORDS, move(buffer_pointer_0)); - sdram_read(c_server, sdram_state, 0, ROW_WORDS, move(buffer_pointer_1)); - sdram_read(c_server, sdram_state, 0, ROW_WORDS, move(buffer_pointer_2)); - sdram_read(c_server, sdram_state, 0, ROW_WORDS, move(buffer_pointer_3)); - while(1){ + sdram_read(c_server, sdram_state, 0, BUF_WORDS, move(buffer_pointer_0)); + sdram_read(c_server, sdram_state, 0, BUF_WORDS, move(buffer_pointer_1)); + sdram_read(c_server, sdram_state, 0, BUF_WORDS, move(buffer_pointer_2)); + sdram_read(c_server, sdram_state, 0, BUF_WORDS, move(buffer_pointer_3)); + while(1){ select { case t when timerafter(time + SECONDS*100000000) :> time: printintln(words_since_timeout*4/SECONDS); words_since_timeout = 0; break; case sdram_complete(c_server, sdram_state, buffer_pointer_0):{ - words_since_timeout += ROW_WORDS; - sdram_read(c_server, sdram_state, 0, ROW_WORDS, move(buffer_pointer_0)); + words_since_timeout += BUF_WORDS; + sdram_read(c_server, sdram_state, 0, BUF_WORDS, move(buffer_pointer_0)); break; } } @@ -97,7 +101,17 @@ void sdram_client(streaming chanend c_server) { sdram_init_state(c_server, sdram_state); application(c_server, sdram_state); } - +#if defined(__XS3A__) +// SDRAM test board for XU316 +#define CLOCK_DIV 5 // (600/ (5*2)) = 60.0MHz +#define SERVER_TILE 1 +on tile[SERVER_TILE] : out buffered port:32 sdram_dq_ah = XS1_PORT_16A; +on tile[SERVER_TILE] : out buffered port:32 sdram_cas = XS1_PORT_1A; +on tile[SERVER_TILE] : out buffered port:32 sdram_ras = XS1_PORT_1P; +on tile[SERVER_TILE] : out buffered port:8 sdram_we = XS1_PORT_1M; +on tile[SERVER_TILE] : out port sdram_clk = XS1_PORT_1F; +on tile[SERVER_TILE] : clock sdram_cb = XS1_CLKBLK_1; +#else //Triangle slot tile 0 for XU216 #define SERVER_TILE 0 on tile[SERVER_TILE] : out buffered port:32 sdram_dq_ah = XS1_PORT_16B; @@ -106,7 +120,7 @@ on tile[SERVER_TILE] : out buffered port:32 sdram_ras = XS1_ on tile[SERVER_TILE] : out buffered port:8 sdram_we = XS1_PORT_1K; on tile[SERVER_TILE] : out port sdram_clk = XS1_PORT_1L; on tile[SERVER_TILE] : clock sdram_cb = XS1_CLKBLK_2; - +#endif int main() { streaming chan c_sdram[1]; par { diff --git a/tests/sdram_multi_client_test/config.xscope b/tests/sdram_multi_client_test/config.xscope index 29ab652..fd50384 100644 --- a/tests/sdram_multi_client_test/config.xscope +++ b/tests/sdram_multi_client_test/config.xscope @@ -1,2 +1,2 @@ - - + + diff --git a/tests/sdram_multi_client_test/src/sdram_multi_client_test.xc b/tests/sdram_multi_client_test/src/sdram_multi_client_test.xc index f382697..f6e86be 100644 --- a/tests/sdram_multi_client_test/src/sdram_multi_client_test.xc +++ b/tests/sdram_multi_client_test/src/sdram_multi_client_test.xc @@ -14,7 +14,11 @@ #define CAS_LATENCY 2 #define REFRESH_MS 64 +#if defined (__XS2A__) #define CLOCK_DIV 4 //Note clock div 4 gives (500/ (4*2)) = 62.5MHz +#else +#define CLOCK_DIV 5 //Note clock div 4 gives (600/ (5*2)) = 60.0MHz +#endif #define DATA_BITS 16 #if SDRAM_256Mb @@ -76,12 +80,14 @@ static int test(streaming chanend c_server, s_sdram_state &sdram_state, int n){ } void sdram_client(streaming chanend c_server, int n) { + printf("client %d\n", n); set_thread_fast_mode_on(); s_sdram_state sdram_state; sdram_init_state(c_server, sdram_state); test(c_server, sdram_state, n); } +#if defined (__XS2A__) //Triangle slot tile 0 for XU216 #define SERVER_TILE 0 on tile[SERVER_TILE] : out buffered port:32 sdram_dq_ah = XS1_PORT_16B; @@ -90,7 +96,16 @@ on tile[SERVER_TILE] : out buffered port:32 sdram_ras = XS1_ on tile[SERVER_TILE] : out buffered port:8 sdram_we = XS1_PORT_1K; on tile[SERVER_TILE] : out port sdram_clk = XS1_PORT_1L; on tile[SERVER_TILE] : clock sdram_cb = XS1_CLKBLK_2; +#else +#define SERVER_TILE 1 +on tile[SERVER_TILE] : out buffered port:32 sdram_dq_ah = XS1_PORT_16A; +on tile[SERVER_TILE] : out buffered port:32 sdram_cas = XS1_PORT_1A; +on tile[SERVER_TILE] : out buffered port:32 sdram_ras = XS1_PORT_1P; +on tile[SERVER_TILE] : out buffered port:8 sdram_we = XS1_PORT_1M; +on tile[SERVER_TILE] : out port sdram_clk = XS1_PORT_1F; +on tile[SERVER_TILE] : clock sdram_cb = XS1_CLKBLK_1; +#endif int main() { streaming chan c_sdram[7]; par { @@ -106,14 +121,25 @@ int main() { } printf("Success\n"); } - on tile[SERVER_TILE]:sdram_server(c_sdram, 1, - sdram_dq_ah, - sdram_cas, - sdram_ras, - sdram_we, - sdram_clk, - sdram_cb, - 2, 128, 16, 8,12, 2, 64, 4096, 4); + on tile[SERVER_TILE]:{ + set_thread_fast_mode_on(); + sdram_server(c_sdram, 7, + sdram_dq_ah, + sdram_cas, + sdram_ras, + sdram_we, + sdram_clk, + sdram_cb, + CAS_LATENCY, + ROW_WORDS, + DATA_BITS, + COL_ADDRESS_BITS, + ROW_ADDRESS_BITS, + BANK_ADDRESS_BITS, + REFRESH_MS, + REFRESH_CYCLES, + CLOCK_DIV); + } } return 0; } diff --git a/tests/sdram_testbench/src/sdram_testbench.xc b/tests/sdram_testbench/src/sdram_testbench.xc index 23ce60d..ea2d284 100644 --- a/tests/sdram_testbench/src/sdram_testbench.xc +++ b/tests/sdram_testbench/src/sdram_testbench.xc @@ -10,7 +10,7 @@ //For XS2 (xCORE200) put an SDRAM slice into the 'triangle' slot of tile 0 of the XP-SKC-X200 slice kit //If using 256Mb slice, then define USE_256Mb below, otherwise leave commented out -#define VERBOSE_MSG 1 +#define VERBOSE_MSG 0 #define SDRAM_256Mb 0//1 //Use IS42S16160D 256Mb #define SDRAM_128Mb 0 //Use IS42S16800D 128Mb @@ -21,7 +21,11 @@ #define CAS_LATENCY 2 #define REFRESH_MS 64 +#ifdef __XS2A__ #define CLOCK_DIV 4 //Note clock div 4 gives (500 / (4*2)) = 62.5MHz +#else +#define CLOCK_DIV 5 // 600 / (5*2) = 60.0MHz +#endif #define DATA_BITS 16 #if SDRAM_256Mb @@ -413,14 +417,14 @@ on tile[SERVER_TILE] : out buffered port:8 sdram_we = XS1_ on tile[SERVER_TILE] : out port sdram_clk = XS1_PORT_1L; on tile[SERVER_TILE] : clock sdram_cb = XS1_CLKBLK_2; #else -//Square slot on A16 slicekit +//on AH05_SDRAM board #define SERVER_TILE 1 on tile[SERVER_TILE] : out buffered port:32 sdram_dq_ah = XS1_PORT_16A; -on tile[SERVER_TILE] : out buffered port:32 sdram_cas = XS1_PORT_1B; -on tile[SERVER_TILE] : out buffered port:32 sdram_ras = XS1_PORT_1G; -on tile[SERVER_TILE] : out buffered port:8 sdram_we = XS1_PORT_1C; +on tile[SERVER_TILE] : out buffered port:32 sdram_cas = XS1_PORT_1A; +on tile[SERVER_TILE] : out buffered port:32 sdram_ras = XS1_PORT_1P; +on tile[SERVER_TILE] : out buffered port:8 sdram_we = XS1_PORT_1M; on tile[SERVER_TILE] : out port sdram_clk = XS1_PORT_1F; -on tile[SERVER_TILE] : clock sdram_cb = XS1_CLKBLK_2; +on tile[SERVER_TILE] : clock sdram_cb = XS1_CLKBLK_1; #endif int main() { diff --git a/tests/sdram_testbench/xcore_ai_sdram_test_board.xn b/tests/sdram_testbench/xcore_ai_sdram_test_board.xn index 1eac885..a71690d 100644 --- a/tests/sdram_testbench/xcore_ai_sdram_test_board.xn +++ b/tests/sdram_testbench/xcore_ai_sdram_test_board.xn @@ -52,4 +52,4 @@ - \ No newline at end of file + From f327577a241c6badf39a0005482db87a5d8df378 Mon Sep 17 00:00:00 2001 From: alexyiuxmos Date: Tue, 21 Jul 2026 13:52:48 +0100 Subject: [PATCH 4/9] correct the Jenkins agent --- Jenkinsfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Jenkinsfile b/Jenkinsfile index e0bdb07..b2659d2 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -38,7 +38,7 @@ pipeline { stages { stage('🏗️ Build and test') { agent { - label 'ah05-sdram0' + label 'ah05-sdram' } stages { From baf5319025ecfb5a630bb0bf966fc501640b1ccf Mon Sep 17 00:00:00 2001 From: alexyiuxmos Date: Tue, 21 Jul 2026 15:24:49 +0100 Subject: [PATCH 5/9] exit loop from multi client test --- Jenkinsfile | 2 +- tests/sdram_multi_client_test/src/sdram_multi_client_test.xc | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/Jenkinsfile b/Jenkinsfile index b2659d2..7e0364b 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -95,7 +95,7 @@ pipeline { sh "xrun --xscope bin/sdram_testbench.xe" } dir("sdram_multi_client_test") { - sh "xrun --xscope bin/sdram_multe_client_test.xe" + sh "xrun --xscope bin/sdram_multi_client_test.xe" } } } diff --git a/tests/sdram_multi_client_test/src/sdram_multi_client_test.xc b/tests/sdram_multi_client_test/src/sdram_multi_client_test.xc index f6e86be..01c9e48 100644 --- a/tests/sdram_multi_client_test/src/sdram_multi_client_test.xc +++ b/tests/sdram_multi_client_test/src/sdram_multi_client_test.xc @@ -120,6 +120,7 @@ int main() { sdram_client(c_sdram[6], 6); } printf("Success\n"); + _Exit(0); } on tile[SERVER_TILE]:{ set_thread_fast_mode_on(); From 2cb04eccea7f638d6f979ed2ab11c28e6585886e Mon Sep 17 00:00:00 2001 From: alexyiuxmos Date: Tue, 21 Jul 2026 15:31:57 +0100 Subject: [PATCH 6/9] exit loop for multi client --- tests/sdram_multi_client_test/src/sdram_multi_client_test.xc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tests/sdram_multi_client_test/src/sdram_multi_client_test.xc b/tests/sdram_multi_client_test/src/sdram_multi_client_test.xc index 01c9e48..7b80134 100644 --- a/tests/sdram_multi_client_test/src/sdram_multi_client_test.xc +++ b/tests/sdram_multi_client_test/src/sdram_multi_client_test.xc @@ -2,6 +2,8 @@ // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include +#include +#include #include "sdram.h" //For XS2 (xCORE200) put an SDRAM slice into the 'triangle' slot of tile 0 of the XP-SKC-X200 slice kit @@ -85,6 +87,7 @@ void sdram_client(streaming chanend c_server, int n) { s_sdram_state sdram_state; sdram_init_state(c_server, sdram_state); test(c_server, sdram_state, n); + _Exit(0); } #if defined (__XS2A__) @@ -120,7 +123,6 @@ int main() { sdram_client(c_sdram[6], 6); } printf("Success\n"); - _Exit(0); } on tile[SERVER_TILE]:{ set_thread_fast_mode_on(); From 66a1f8fb9cf4fb39506e3ba45c2c291c7e066292 Mon Sep 17 00:00:00 2001 From: alexyiuxmos Date: Tue, 21 Jul 2026 18:08:13 +0100 Subject: [PATCH 7/9] updated Jenkinsfile --- Jenkinsfile | 41 ++++++++++++++++++++++++++++++++--------- 1 file changed, 32 insertions(+), 9 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index 7e0364b..2bd8cee 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -24,7 +24,7 @@ pipeline { description: 'The infr_apps version' ) choice( - name: 'TEST_LEVEL', choices: ['default', 'smoke', 'extended'], + name: 'TEST_LEVEL', choices: ['smoke', 'default', 'extended'], description: 'The level of test coverage to run' ) } @@ -36,6 +36,37 @@ pipeline { } stages { + stage('🏗️ Build doc') { + agent { + label 'x86_64 && linux && documentation' + } + + stages { + stage('Checkout') { + steps { + + println "Stage running on ${env.NODE_NAME}" + + script { + def (server, user, repo) = extractFromScmUrl() + env.REPO_NAME = repo + } + + dir(REPO_NAME){ + checkoutScmShallow() + } + } + } + + stage('Doc build') { + steps { + dir(REPO_NAME) { + buildDocs() + } + } + } + } + } // build doc stage('🏗️ Build and test') { agent { label 'ah05-sdram' @@ -75,14 +106,6 @@ pipeline { } } - stage('Doc build') { - steps { - dir(REPO_NAME) { - buildDocs() - } - } - } - stage('Tests') { steps { echo "TEST_LEVEL: ${params.TEST_LEVEL}" From 2d1406880a1413623a670ff7f938c1a5ee225c8c Mon Sep 17 00:00:00 2001 From: alexyiuxmos Date: Wed, 22 Jul 2026 15:19:31 +0100 Subject: [PATCH 8/9] update README.rst and CHANGLOG.rst --- CHANGELOG.rst | 5 + Jenkinsfile | 183 +++++++++++++---------- README.rst | 8 +- tests/sdram_benchmark/src/sdram_bench.xc | 20 +++ 4 files changed, 134 insertions(+), 82 deletions(-) diff --git a/CHANGELOG.rst b/CHANGELOG.rst index 56973b5..cee6320 100644 --- a/CHANGELOG.rst +++ b/CHANGELOG.rst @@ -1,6 +1,11 @@ lib_sdram change log ==================== +3.5.0 +----- + + * CHANGED: updated example and test to support AH05-SDRAM (xcore.ai) + 3.4.0 ----- diff --git a/Jenkinsfile b/Jenkinsfile index 2bd8cee..9013a5c 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -36,108 +36,135 @@ pipeline { } stages { - stage('🏗️ Build doc') { - agent { - label 'x86_64 && linux && documentation' - } + stage ('Build Docs and Test') { + parallel { + stage('🏗️ Build doc') { + agent { + label 'x86_64 && linux && documentation' + } - stages { - stage('Checkout') { - steps { + stages { + stage('Checkout') { + steps { - println "Stage running on ${env.NODE_NAME}" + println "Stage running on ${env.NODE_NAME}" - script { - def (server, user, repo) = extractFromScmUrl() - env.REPO_NAME = repo + script { + def (server, user, repo) = extractFromScmUrl() + env.REPO_NAME = repo + } + + dir(REPO_NAME){ + checkoutScmShallow() + } + } } - dir(REPO_NAME){ - checkoutScmShallow() + stage('Examples build') { + steps { + dir("${REPO_NAME}/examples") { + xcoreBuild() + } + } + } + + stage('Repo checks') { + steps { + warnError("Repo checks failed") + { + runRepoChecks("${WORKSPACE}/${REPO_NAME}") + } + } } - } - } - stage('Doc build') { - steps { - dir(REPO_NAME) { - buildDocs() + stage('Doc build') { + steps { + dir(REPO_NAME) { + buildDocs() + } + } } + + stage("Archive sandbox") { + steps { + archiveSandbox(REPO_NAME) + } + } + } + } // build doc + stage('🏗️ Build and test') { + agent { + label 'ah05-sdram' } - } - } - } // build doc - stage('🏗️ Build and test') { - agent { - label 'ah05-sdram' - } - stages { - stage('Checkout') { - steps { + stages { + stage('Checkout') { + steps { - println "Stage running on ${env.NODE_NAME}" + println "Stage running on ${env.NODE_NAME}" - script { - def (server, user, repo) = extractFromScmUrl() - env.REPO_NAME = repo - } + script { + def (server, user, repo) = extractFromScmUrl() + env.REPO_NAME = repo + } - dir(REPO_NAME){ - checkoutScmShallow() + dir(REPO_NAME){ + checkoutScmShallow() + } + } } - } - } - stage('Examples build') { - steps { - dir("${REPO_NAME}/examples") { - xcoreBuild() + stage('Examples build') { + steps { + dir("${REPO_NAME}/examples") { + xcoreBuild() + } + } } - } - } - stage('Repo checks') { - steps { - warnError("Repo checks failed") - { - runRepoChecks("${WORKSPACE}/${REPO_NAME}") + stage('Repo checks') { + steps { + warnError("Repo checks failed") + { + runRepoChecks("${WORKSPACE}/${REPO_NAME}") + } + } } - } - } - - stage('Tests') { - steps { - echo "TEST_LEVEL: ${params.TEST_LEVEL}" - dir("${REPO_NAME}/tests") { - withTools(params.TOOLS_VERSION) { - createVenv(reqFile: "requirements.txt") - withVenv { - xcoreBuild(archiveBins: false) - dir("sdram_testbench") { - sh "xrun --xscope bin/sdram_testbench.xe" - } - dir("sdram_multi_client_test") { - sh "xrun --xscope bin/sdram_multi_client_test.xe" + + stage('Tests') { + steps { + echo "TEST_LEVEL: ${params.TEST_LEVEL}" + dir("${REPO_NAME}/tests") { + withTools(params.TOOLS_VERSION) { + createVenv(reqFile: "requirements.txt") + withVenv { + xcoreBuild(archiveBins: false) + dir("sdram_testbench") { + sh "xrun --io bin/sdram_testbench.xe" + } + dir("sdram_multi_client_test") { + sh "xrun --io bin/sdram_multi_client_test.xe" + } + } } } } } - } - } - stage("Archive sandbox") { - steps { - archiveSandbox(REPO_NAME) + stage("Archive sandbox") { + steps { + archiveSandbox(REPO_NAME) + } + } + } // stages + post { + cleanup { + xcoreCleanSandbox() + } } - } - } // stages - post { - cleanup { - xcoreCleanSandbox() - } - } - } // stage 'Build and test' + } // stage 'build docs and test' + } // parallel + } stage('🚀 Release') { when { diff --git a/README.rst b/README.rst index 36d9adf..e9d11f6 100644 --- a/README.rst +++ b/README.rst @@ -5,18 +5,18 @@ lib_sdram: SDRAM library ############################## :vendor: XMOS -:version: 3.4.0 +:version: 3.5.0 :scope: General Use :description: SDRAM server and Memory address allocator components :category: General Purpose :keywords: Memory,SDRAM -:devices: xcore-200 +:devices: xcore-200, xcore-ai ******* Summary ******* -The XMOS SDRAM library is designed for read and write access of arbitrary length 32b long word buffers at up to 62.5MHz clock rates. +The XMOS SDRAM library is designed for read and write access of arbitrary length 32b long word buffers at up to 60.0MHz clock rates. It uses an optimized pinout with address and data lines overlaid along with other pinout optimizations to implement 16 bit read/writes to Single Data Rate (SDR) SDRAM devices of size up to 256Mb, while consuming a total of just 20 xCORE I/O pins. @@ -27,7 +27,7 @@ Features * Configurability of: * SDRAM capacity - * clock rate (62.5 to 25MHz steps are provided) + * clock rate (60.0 to 30MHz steps are provided) * refresh properties * Supports: * read of 32b long words diff --git a/tests/sdram_benchmark/src/sdram_bench.xc b/tests/sdram_benchmark/src/sdram_bench.xc index 04162cf..879bf8d 100644 --- a/tests/sdram_benchmark/src/sdram_bench.xc +++ b/tests/sdram_benchmark/src/sdram_bench.xc @@ -48,6 +48,12 @@ #define ROW_WORDS 128 #endif +unsigned timer_is_after(timer t, unsigned time) +{ + unsigned now; + t :> now; + return timeafter(now, time); +} #pragma unsafe arrays void application(streaming chanend c_server, s_sdram_state sdram_state) { @@ -73,6 +79,19 @@ void application(streaming chanend c_server, s_sdram_state sdram_state) { sdram_read(c_server, sdram_state, 0, BUF_WORDS, move(buffer_pointer_2)); sdram_read(c_server, sdram_state, 0, BUF_WORDS, move(buffer_pointer_3)); while(1){ +#if JTAG_IO_PRINT + // avoid slow JTAG IO results printing to + // interrupt SDRAM server reading command + sdram_complete(c_server, sdram_state, buffer_pointer_0); + words_since_timeout += BUF_WORDS; + if (timer_is_after(t, time + SECONDS*100000000)) + { + printintln(words_since_timeout*4/SECONDS); + words_since_timeout = 0; + t :> time; + } + sdram_read(c_server, sdram_state, 0, BUF_WORDS, move(buffer_pointer_0)); +#else select { case t when timerafter(time + SECONDS*100000000) :> time: printintln(words_since_timeout*4/SECONDS); @@ -84,6 +103,7 @@ void application(streaming chanend c_server, s_sdram_state sdram_state) { break; } } +#endif } } From 8f55eb5978755f5b9a1fcf30e628d22a4d665e10 Mon Sep 17 00:00:00 2001 From: alexyiuxmos Date: Wed, 22 Jul 2026 15:41:42 +0100 Subject: [PATCH 9/9] fix typo errors --- lib_sdram/lib_build_info.cmake | 4 ++-- settings.yml | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/lib_sdram/lib_build_info.cmake b/lib_sdram/lib_build_info.cmake index bb95b93..56cd56e 100644 --- a/lib_sdram/lib_build_info.cmake +++ b/lib_sdram/lib_build_info.cmake @@ -1,5 +1,5 @@ set(LIB_NAME lib_sdram) -set(LIB_VERSION 3.4.0) +set(LIB_VERSION 3.5.0) set(LIB_INCLUDES api src) set(LIB_DEPENDENT_MODULES "") @@ -10,4 +10,4 @@ set(LIB_COMPILER_FLAGS -O3 -fcomment-asm -g) -XMOS_REGISTER_MODULE() \ No newline at end of file +XMOS_REGISTER_MODULE() diff --git a/settings.yml b/settings.yml index 209236a..5fa8f75 100644 --- a/settings.yml +++ b/settings.yml @@ -3,7 +3,7 @@ lib_name: lib_sdram project: '{{lib_name}}' title: '{{lib_name}}: SDRAM library' -version: 3.4.0 +version: 3.5.0 documentation: exclude_patterns_path: doc/exclude_patterns.inc @@ -24,4 +24,4 @@ documentation: pdf_filename: '{{lib_name}}_v{{version}}_readme' pdf_short: yes software: - cognidox_part_number: XM-006978-SM \ No newline at end of file + cognidox_part_number: XM-006978-SM