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[TEST] TEST-MDIO-PHY-001: MDIO/PHY Register Access Verification #312

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[TEST] TEST-MDIO-PHY-001: MDIO/PHY Register Access Verification#312
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component:ioctlphase:07-verification-validationPhase 07: Verification & Validationpriority:p1High priority - should havestatus:closedIssue closedtest-type:integrationIntegration test - tests component interactionstype:test-caseTest case (TEST) - verification and validation

Description

@zarfld
zarfld
opened on Dec 31, 2025

Test Specification

Test ID: TEST-MDIO-PHY-001
Test Name: MDIO/PHY Register Access Verification
Component: IOCTL Handler - MDIO/PHY Access
Test Type: Integration Test
Priority: P1
Phase: 07-verification-validation
Estimated Effort: 3 days

Traceability

Objective

Verify that the MDIO/PHY register access IOCTLs (29, 30) correctly read and write PHY registers via the MDIO interface, with proper validation, error handling, and hardware interaction.

Test Environment

  • Hardware: Intel I210/I225/I226 network adapter with active PHY
  • Driver: IntelAvbFilter.sys (Debug build)
  • Test Framework: User-mode test harness with IOCTL interface
  • Tools: WinDbg, Network Monitor, PHY diagnostic tools

Prerequisites

  • Driver installed and adapter initialized
  • PHY chip detected and accessible
  • MDIO interface operational
  • Test has administrator privileges for IOCTL access
  • Hardware documentation for target PHY registers available

Test Cases

UT-MDIO-001: Basic MDIO Read Operation

Description: Verify basic MDIO read from standard PHY register
Input:

  • IOCTL: 29 (MDIO_READ)
  • PHY Address: 0x00 (internal PHY)
  • Register: 0x00 (Control Register)

Expected Output:

  • STATUS_SUCCESS
  • Valid register value returned
  • No hardware errors

Acceptance Criteria:

  • ✅ IOCTL completes successfully
  • ✅ Register value matches expected format (16-bit)
  • ✅ Read operation logged correctly

UT-MDIO-002: Basic MDIO Write Operation

Description: Verify basic MDIO write to PHY configuration register
Input:

  • IOCTL: 30 (MDIO_WRITE)
  • PHY Address: 0x00
  • Register: 0x1F (Vendor Specific Config)
  • Value: Test pattern (0xA5A5)

Expected Output:

  • STATUS_SUCCESS
  • Write confirmed via subsequent read
  • No hardware errors

Acceptance Criteria:

  • ✅ IOCTL completes successfully
  • ✅ Readback value matches written value
  • ✅ PHY state updated correctly

UT-MDIO-003: Multi-Page PHY Access

Description: Verify MDIO access across multiple PHY register pages
Input:

  • IOCTL: 29/30 (READ/WRITE)
  • PHY Address: 0x00
  • Page Selection Register: 0x1F
  • Target Registers: Various across pages 0-7

Expected Output:

  • STATUS_SUCCESS for all page transitions
  • Correct values read from each page
  • Page register restored after operation

Acceptance Criteria:

  • ✅ Page switching works correctly
  • ✅ Register access isolated per page
  • ✅ No cross-page contamination

UT-MDIO-004: Invalid PHY Address Rejection

Description: Verify rejection of invalid PHY addresses
Input:

  • IOCTL: 29 (MDIO_READ)
  • PHY Address: 0x1F (invalid/non-existent)
  • Register: 0x00

Expected Output:

  • STATUS_INVALID_PARAMETER
  • No hardware access attempted
  • Error logged

Acceptance Criteria:

  • ✅ IOCTL fails with appropriate error
  • ✅ No MDIO bus activity
  • ✅ Driver remains stable

UT-MDIO-005: Out-of-Range Register Rejection

Description: Verify rejection of invalid register addresses
Input:

  • IOCTL: 29 (MDIO_READ)
  • PHY Address: 0x00
  • Register: 0xFF (invalid for standard PHY)

Expected Output:

  • STATUS_INVALID_PARAMETER
  • No hardware access
  • Error logged

Acceptance Criteria:

  • ✅ IOCTL fails gracefully
  • ✅ PHY state unchanged
  • ✅ Proper error code returned

UT-MDIO-006: Read-Only Register Write Protection

Description: Verify protection against writes to read-only registers
Input:

  • IOCTL: 30 (MDIO_WRITE)
  • PHY Address: 0x00
  • Register: 0x01 (Status Register - read-only)
  • Value: 0xFFFF

Expected Output:

  • STATUS_ACCESS_DENIED or STATUS_INVALID_PARAMETER
  • Register value unchanged
  • Error logged

Acceptance Criteria:

  • ✅ Write rejected
  • ✅ Read-only register protected
  • ✅ Clear error message

UT-MDIO-007: MDIO Bus Timeout Handling

Description: Verify timeout handling when PHY doesn't respond
Input:

  • IOCTL: 29 (MDIO_READ)
  • PHY Address: 0x00
  • Simulated condition: PHY unresponsive

Expected Output:

  • STATUS_IO_TIMEOUT
  • Timeout after 10ms (configurable)
  • No system hang

Acceptance Criteria:

  • ✅ Operation times out gracefully
  • ✅ Driver recovers
  • ✅ Subsequent operations work

UT-MDIO-008: Concurrent MDIO Access Serialization

Description: Verify mutual exclusion for concurrent MDIO operations
Input:

  • Multiple threads issuing IOCTL 29/30 simultaneously
  • Same PHY, different registers

Expected Output:

  • All operations succeed
  • Operations serialized (no bus contention)
  • Correct values for all reads

Acceptance Criteria:

  • ✅ Spinlock protects MDIO bus
  • ✅ No data corruption
  • ✅ Fair scheduling of operations

UT-MDIO-009: Extended Register Access (Clause 45)

Description: Verify Clause 45 MDIO access for extended registers
Input:

  • IOCTL: 29/30
  • Device Type: 0x07 (Auto-negotiation)
  • Register: 0x0000-0xFFFF (extended addressing)

Expected Output:

  • STATUS_SUCCESS
  • Clause 45 addressing used
  • Extended register accessible

Acceptance Criteria:

  • ✅ Clause 45 vs Clause 22 detection
  • ✅ Correct register addressing
  • ✅ Data integrity maintained

UT-MDIO-010: PHY Reset via MDIO

Description: Verify software PHY reset via MDIO control register
Input:

  • IOCTL: 30 (MDIO_WRITE)
  • Register: 0x00 (Control Register)
  • Value: 0x8000 (Reset bit)

Expected Output:

  • STATUS_SUCCESS
  • PHY resets and re-initializes
  • Reset bit self-clears

Acceptance Criteria:

  • ✅ Reset executes successfully
  • ✅ PHY returns to known state
  • ✅ Link re-established

UT-MDIO-011: Auto-Negotiation Status Read

Description: Verify reading auto-negotiation status via MDIO
Input:

  • IOCTL: 29 (MDIO_READ)
  • Register: 0x01 (Status Register)
  • Bit 5: Auto-negotiation complete

Expected Output:

  • STATUS_SUCCESS
  • Valid status bit returned
  • Status reflects actual link state

Acceptance Criteria:

  • ✅ Correct status read
  • ✅ Bit interpretation accurate
  • ✅ Matches link state

UT-MDIO-012: Link Partner Ability Read

Description: Verify reading link partner advertisement via MDIO
Input:

  • IOCTL: 29 (MDIO_READ)
  • Register: 0x05 (Auto-Neg Link Partner Ability)

Expected Output:

  • STATUS_SUCCESS
  • Valid capability bits
  • Matches negotiated link speed

Acceptance Criteria:

  • ✅ Capabilities read correctly
  • ✅ Interpretation matches hardware
  • ✅ Data consistent with link status

UT-MDIO-013: Cable Diagnostics via MDIO

Description: Verify cable diagnostic register access
Input:

  • IOCTL: 29/30
  • Vendor-specific cable diagnostic registers

Expected Output:

  • STATUS_SUCCESS
  • Cable status information retrieved
  • No interference with normal operation

Acceptance Criteria:

  • ✅ Diagnostic data accessible
  • ✅ Results interpretable
  • ✅ Link maintained during test

UT-MDIO-014: MDIO Access During Low Power

Description: Verify MDIO access behavior during low-power states
Input:

  • Transition adapter to D3 (low power)
  • IOCTL: 29 (MDIO_READ)

Expected Output:

  • STATUS_DEVICE_NOT_READY or wake-on-access
  • No system crash
  • Proper error handling

Acceptance Criteria:

  • ✅ Power state checked before access
  • ✅ Graceful failure or wake
  • ✅ System stability maintained

UT-MDIO-015: Bulk Register Read Optimization

Description: Verify optimized bulk reading of sequential PHY registers
Input:

  • IOCTL: 29 (MDIO_READ)
  • Sequential registers 0x00-0x1F

Expected Output:

  • STATUS_SUCCESS for all reads
  • Optimized bus transactions (if supported)
  • All values correct

Acceptance Criteria:

  • ✅ All registers read successfully
  • ✅ Performance acceptable
  • ✅ No data corruption

Success Criteria

  • ✅ All 15 test cases pass
  • ✅ MDIO read/write operations work correctly
  • ✅ Error handling comprehensive and robust
  • ✅ PHY register access safe and validated
  • ✅ No hardware damage or corruption
  • ✅ Concurrent access properly serialized
  • ✅ Code coverage >90% for MDIO IOCTL handlers
  • ✅ No memory leaks or resource issues

Test Execution Notes

Setup

  1. Verify PHY chip documentation available
  2. Configure test PHY address and register map
  3. Enable MDIO debug logging if needed
  4. Prepare oscilloscope/logic analyzer for bus monitoring (optional)

Execution

  • Run tests in sequence (dependencies exist)
  • Monitor MDIO bus activity during critical tests
  • Check PHY state before/after destructive operations
  • Log all register values for analysis

Cleanup

  • Restore PHY to default configuration
  • Clear any diagnostic modes enabled
  • Verify link re-established
  • Document any anomalies

Dependencies

  • Hardware: Functional PHY chip with MDIO interface
  • Driver: IOCTL handlers for codes 29, 30 implemented
  • Documentation: PHY register map and specifications
  • Tools: PHY diagnostic utilities for verification

Risk Assessment

  • Medium Risk: PHY register writes can affect link stability
  • Mitigation: Use non-critical registers for write tests
  • Mitigation: Implement rollback/restore mechanisms
  • Low Risk: Read operations are non-destructive

Notes

  • Some PHY registers are vendor-specific - test with actual hardware
  • MDIO bus speed varies by hardware (typically 2.5 MHz)
  • Extended registers (Clause 45) may not be available on all PHYs
  • Cable diagnostics may require specific PHY features

Created: 2025-12-31
Last Updated: 2025-12-31
Status: 🟡 Pending Implementation

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    component:ioctlphase:07-verification-validationPhase 07: Verification & Validationpriority:p1High priority - should havestatus:closedIssue closedtest-type:integrationIntegration test - tests component interactionstype:test-caseTest case (TEST) - verification and validation

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