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1031bb7
[Kernel] Generalize H3 FP16 preparation and residual sharding
yangzhuxinyzx Sep 8, 2026
9623a9a
[Kernel] Preserve H3 reduction order during residual sharding
yangzhuxinyzx Sep 8, 2026
895b4c2
[Doc] Record exact H3 four-step quality controls
yangzhuxinyzx Sep 8, 2026
25a14d6
[Video] Allow pageable H3 weight masters for original checkpoints
yangzhuxinyzx Sep 9, 2026
82362a4
[Video] Measure H3 workflows with actual denoise schedules
yangzhuxinyzx Sep 9, 2026
9bcde29
[Video] Exclude replicated LoRA projections from useful work
yangzhuxinyzx Sep 9, 2026
5195f31
[Video] Integrate prepared H3 execution with workflow measurements
yangzhuxinyzx Sep 9, 2026
7ea8908
[Kernel] Fuse SM70 adapter projection epilogues
yangzhuxinyzx Sep 9, 2026
90f1fcc
[Doc] Record complete SM70 epilogue quality and timing controls
yangzhuxinyzx Sep 9, 2026
6b39f1c
[Kernel] Add explicit SM70 attention query geometry
yangzhuxinyzx Sep 9, 2026
61c57e3
[Video] Execute official FastH3 VSA with native SM70 sparse attention
yangzhuxinyzx Sep 9, 2026
bd5e189
[Doc] Record complete query tiling quality and performance results
yangzhuxinyzx Sep 9, 2026
fa92991
[Doc] Record full native FastH3 VSA bringup and actual sparse work
yangzhuxinyzx Sep 9, 2026
64995e4
[Doc] Record full VSA sparse math quality control failure
yangzhuxinyzx Sep 9, 2026
324f246
[Core] Share checked immutable H3 VAE host storage across TP
yangzhuxinyzx Sep 9, 2026
4ccd454
[Doc] Record eight-step H3 numerical preservation
yangzhuxinyzx Sep 9, 2026
1325511
[Doc] Record TP4 shared H3 host weights and exact media
yangzhuxinyzx Sep 9, 2026
4a1707f
[Doc] Refresh H3 campaign evidence and corrected FLOP budget
yangzhuxinyzx Sep 9, 2026
474fc2b
[Core] Integrate checked shared H3 host storage into metrics
yangzhuxinyzx Sep 9, 2026
2063b09
[Core] Integrate H3 shared host storage into kernel workflow
yangzhuxinyzx Sep 9, 2026
e855f70
[Core] Integrate checked H3 host sharing into native variants
yangzhuxinyzx Sep 9, 2026
9d2489f
[Doc] Record exact mixed-reference H3 eight-step control
yangzhuxinyzx Sep 9, 2026
3367704
[Doc] Audit original H3 FP16 conversion and all Turbo artifacts
yangzhuxinyzx Sep 9, 2026
aea5a0f
[Core] Stage H3 DiT and encoder layers within GPU capacity
yangzhuxinyzx Sep 9, 2026
e8d0185
[Doc] Record full H3 243-frame and 15-second compatibility
yangzhuxinyzx Sep 9, 2026
c7182b5
[Doc] Record original H3 single-card capacity check
yangzhuxinyzx Sep 9, 2026
93bc5b2
[Doc] Verify H3 pinned layer-staging output parity
yangzhuxinyzx Sep 9, 2026
5ad95bd
[Core] Integrate H3 layer residency with workflow accounting
yangzhuxinyzx Sep 9, 2026
1f4f7fd
[Core] Integrate layer residency with H3 kernel options
yangzhuxinyzx Sep 9, 2026
fcbfbcd
[Core] Integrate layer residency with H3 sparse workflows
yangzhuxinyzx Sep 9, 2026
6509fb1
[Core] Share H3 projection epilogues across sparse variants
yangzhuxinyzx Sep 9, 2026
be89a26
[Core] Expose shared SM70 noncausal attention operators
yangzhuxinyzx Sep 9, 2026
980e543
[Core] Integrate shared SM70 attention with H3 VSA
yangzhuxinyzx Sep 9, 2026
ebc1813
[Doc] Record complete TP2 H3 sharding parity and capacity
yangzhuxinyzx Sep 9, 2026
3217459
[Doc] Record full quality controls for all FL2V Turbo artifacts
yangzhuxinyzx Sep 9, 2026
4eea74e
[Core] Track shared SM70 operators in benchmark provenance
yangzhuxinyzx Sep 9, 2026
f62eff3
[Core] Integrate shared operator provenance into H3 kernels
yangzhuxinyzx Sep 9, 2026
f8b85c6
[Kernel] Keep SM70 attention probabilities in registers
yangzhuxinyzx Sep 9, 2026
3f79a56
[Model] Integrate dense SM70 kernel and shared provenance updates
yangzhuxinyzx Sep 9, 2026
c69cfc7
[Doc] Record complete FI register-kernel media preservation
yangzhuxinyzx Sep 9, 2026
4ed7041
[Doc] Record formal FI results and all eight H3 Turbo controls
yangzhuxinyzx Sep 9, 2026
ef18c81
[Doc] Record full H3 first and last frame parity controls
yangzhuxinyzx Sep 9, 2026
3280edb
[Doc] Record H3 workflow controls and remaining performance gates
yangzhuxinyzx Sep 9, 2026
6d2a44b
[Kernel] Add explicit calibrated SM70 local-row reduction
yangzhuxinyzx Sep 9, 2026
437c02d
[Merge] Share calibrated SM70 collectives with H3 variants
yangzhuxinyzx Sep 9, 2026
6951ff5
[Doc] Record native media preservation for shared row reduction
yangzhuxinyzx Sep 9, 2026
ca82c27
[Core] Expose budgeted native H3 residual reduction
yangzhuxinyzx Sep 9, 2026
7a21b73
[Merge] Expose native peer reduction to H3 variants
yangzhuxinyzx Sep 9, 2026
58cafcd
[Doc] Record formal native H3 peer reduction results
yangzhuxinyzx Sep 9, 2026
f12803d
[Doc] Record native peer backend and workload controls
yangzhuxinyzx Sep 9, 2026
44679e8
[Doc] Focus H3 attention optimization on FlashAttention
yangzhuxinyzx Sep 9, 2026
dcaad0c
[Doc] Record FA bottlenecks and rejected operator candidates
yangzhuxinyzx Sep 9, 2026
570be8d
[Doc] Close FA staging resource experiment
yangzhuxinyzx Sep 9, 2026
e9dea12
[Doc] Align H3 control record with FA development focus
yangzhuxinyzx Sep 9, 2026
692dd34
[Test] Record complete original H3 sampling preservation
yangzhuxinyzx Sep 9, 2026
9f220dc
[Doc] Consolidate retained FA workflow delivery
yangzhuxinyzx Sep 9, 2026
970c5fb
Merge branch 'codex/v100-h3-sm70-kernels-20260909-040520' into codex/…
yangzhuxinyzx Sep 9, 2026
56e8847
[Core] Defer H3 sparse work counters and internal validation
yangzhuxinyzx Sep 9, 2026
1865903
[Core] Fuse H3 VSA tiling and request-owned layout buffers
yangzhuxinyzx Sep 9, 2026
450f9b9
[Benchmark] Check the primary H3 VSA timing stage against Dense
yangzhuxinyzx Sep 9, 2026
92b4f30
[Benchmark] Preserve the H3 VSA FP32 quality diagnostic and stage res…
yangzhuxinyzx Sep 9, 2026
3ae9087
[Benchmark] Batch independent H3 FP32 sparse queries
yangzhuxinyzx Sep 9, 2026
b202c2b
[Doc] Record the H3 VSA precision timing failure and review scope
yangzhuxinyzx Sep 9, 2026
d6669c4
[Merge] Integrate H3 SM70 and VSA work with main
yangzhuxinyzx Sep 10, 2026
1c39c17
[Merge] Include the H3 TP2 dependency evidence
yangzhuxinyzx Sep 10, 2026
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10 changes: 10 additions & 0 deletions CMakeLists.txt
Original file line number Diff line number Diff line change
Expand Up @@ -782,6 +782,16 @@ if(VLLM_GPU_LANG STREQUAL "CUDA" AND SM70_TURBOMIND_ARCHS)
ARCHITECTURES "70"
LIBRARIES "${TORCH_INSTALL_PREFIX}/lib/libtorch_python.so"
WITH_SOABI)
define_extension_target(
_sm70_sparse_attention_C DESTINATION vllm LANGUAGE CUDA
SOURCES "flash-attention-v100/kernel/h3/forward_sparse.cu"
INCLUDE_DIRECTORIES
"${CUTLASS_INCLUDE_DIR}"
"${cutlass_SOURCE_DIR}/examples/41_fused_multi_head_attention"
COMPILE_FLAGS ${VLLM_GPU_FLAGS}
ARCHITECTURES "70"
LIBRARIES "${TORCH_INSTALL_PREFIX}/lib/libtorch_python.so"
WITH_SOABI)
endif()

if(VLLM_GPU_LANG STREQUAL "CUDA" OR VLLM_GPU_LANG STREQUAL "HIP")
Expand Down
173 changes: 173 additions & 0 deletions benchmarks/kernels/benchmark_h3_vsa_fp32.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,173 @@
# SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
"""Acceptance-only sparse FP32 CUDA probe; never registers a runtime backend.

Run on an externally leased SM70 GPU. An optional captured attention input is
compared with independent gathered FP32 QK/global softmax/PV. Operator timings
are diagnostic and cannot satisfy the complete-denoise performance gate.
"""

import argparse
import hashlib
import importlib.util
import json
import statistics
from pathlib import Path

import torch


def load_binary(path: Path):
path = path.resolve(strict=True)
spec = importlib.util.spec_from_file_location(path.stem, path)
module = importlib.util.module_from_spec(spec)
spec.loader.exec_module(module)
return module


def fp32_reference(q, k, v, block_map, sizes, scale):
"""Independent mathematical oracle, with physical padding masked explicitly.

Match the frozen oracle's grouping (at most eight queries and 256 MiB per
gathered operand). No production sparse kernel or geometry helper is used.
This is an engineering FP32 reference, not the official GPU implementation.
"""
if torch.is_autocast_enabled("cuda"):
raise ValueError("FP32 reference requires CUDA autocast to be disabled")
batch, rows, heads, dim = q.shape
blocks = rows // 64
flat = [x.permute(0, 2, 1, 3).reshape(batch * heads, rows, dim) for x in (q, k, v)]
maps = block_map.reshape(batch * heads, blocks, blocks)
order = torch.arange(blocks, device=q.device).view(1, 1, blocks).expand_as(maps)
selected = order.masked_fill(~maps, blocks).sort(dim=-1).values
counts = maps.sum(-1).amax(0).tolist()
lanes = torch.arange(64, device=q.device)
bh = torch.arange(batch * heads, device=q.device)[:, None, None]
output = torch.zeros_like(flat[0])
pos = 0
while pos < blocks:
keep = int(counts[pos])
if keep == 0:
raise ValueError("reference requires nonempty selected rows")
chunk = max(1, min(8, 256 * 1024**2 // (batch * heads * keep * 64 * dim * 4)))
end = pos + 1
while end < min(blocks, pos + chunk) and counts[end] == keep:
end += 1
index = selected[:, pos:end, :keep]
safe = index.clamp_max(blocks - 1)
tokens = (safe[..., None] * 64 + lanes).flatten(-2)
valid = (
(index < blocks)[..., None] & (lanes < sizes[safe][..., None])
).flatten(-2)
keys, values = [flat[i][bh, tokens].float() for i in (1, 2)]
keys.masked_fill_(~valid[..., None], 0)
values.masked_fill_(~valid[..., None], 0)
queries = flat[0][:, pos * 64 : end * 64].reshape(-1, 64, dim).float()
shape = (batch * heads * (end - pos), keep * 64, dim)
scores = torch.bmm(queries, keys.reshape(shape).transpose(1, 2)) * scale
scores.masked_fill_(~valid.reshape(-1, 1, keep * 64), -float("inf"))
answer = torch.bmm(scores.softmax(-1), values.reshape(shape))
output[:, pos * 64 : end * 64] = answer.reshape(batch * heads, -1, dim).to(
q.dtype
)
pos = end
return output.reshape(batch, heads, rows, dim).permute(0, 2, 1, 3).contiguous()


def prepare_capture(path):
from vllm.model_executor.models.minimax_h3 import vsa

data = torch.load(path, weights_only=True, map_location="cpu", mmap=True)
q, k, v = [data[name].cuda() for name in ("q", "k", "v")]
part, sizes, nonpad, _, prefix, video = vsa._get_h3_tile_metadata(
tuple(data["prefix_segments"]), tuple(data["video_shape"]), q.device
)
tiled = []
for tensor in (q, k, v):
out = torch.zeros(
q.size(0), len(sizes) * 64, q.size(2), 128, device=q.device, dtype=q.dtype
)
out[:, nonpad] = tensor[:, part]
tiled.append(out)
q, k, v = tiled
scores = (
torch.matmul(
vsa._pool_h3_tiles(q, sizes), vsa._pool_h3_tiles(k, sizes).transpose(-2, -1)
)
* data["scale"]
)
mask = vsa._build_h3_block_map(scores, prefix, video, data["topk"])
return (q, k, v, mask, sizes, data["scale"], prefix, data["topk"]), nonpad


def main():
parser = argparse.ArgumentParser(description=__doc__)
parser.add_argument("--binary", type=Path)
parser.add_argument("--build-directory", type=Path)
parser.add_argument("--cutlass-root", type=Path)
parser.add_argument("--capture", type=Path)
parser.add_argument("--output", type=Path, required=True)
args = parser.parse_args()
if args.binary:
if args.build_directory or args.cutlass_root:
parser.error("choose an existing binary or a build directory/CUTLASS root")
binary = args.binary.resolve(strict=True)
ops = load_binary(binary)
else:
if not args.build_directory or not args.cutlass_root:
parser.error("building requires --build-directory and --cutlass-root")
from torch.utils.cpp_extension import load

args.build_directory.mkdir(parents=True, exist_ok=True)
ops = load(
name="h3_vsa_cutlass_fp32",
sources=[str(Path(__file__).with_name("h3_vsa_fp32.cu"))],
extra_include_paths=[str(args.cutlass_root / "include")],
extra_cuda_cflags=["-O3", "--ptxas-options=-v"],
build_directory=str(args.build_directory),
verbose=True,
)
binary = Path(ops.__file__)
record = {
"binary": str(binary),
"binary_sha256": hashlib.sha256(binary.read_bytes()).hexdigest(),
"source_sha256": hashlib.sha256(
Path(__file__).with_name("h3_vsa_fp32.cu").read_bytes()
).hexdigest(),
"built_from_reported_source": not bool(args.binary),
"torch_version": torch.__version__,
"cuda_version": torch.version.cuda,
"performance_eligible": False,
"scope": "operator diagnostic only",
}
if args.capture:
with torch.inference_mode():
values, valid = prepare_capture(args.capture)
q, k, v, mask, sizes, scale, _, _ = values
actual = ops.forward(*values)
expected = fp32_reference(q, k, v, mask, sizes, scale)
record["bitwise"] = torch.equal(
actual[:, valid].view(torch.int16), expected[:, valid].view(torch.int16)
)
if record["bitwise"]:
for _ in range(2):
ops._forward_prevalidated(*values)
times = []
for _ in range(4):
start, end = [
torch.cuda.Event(enable_timing=True) for _ in range(2)
]
start.record()
ops._forward_prevalidated(*values)
end.record()
end.synchronize()
times.append(start.elapsed_time(end))
record.update(times_ms=times, median_ms=statistics.median(times))
args.output.write_text(json.dumps(record, indent=2))
print(json.dumps(record))
if record.get("bitwise") is False:
raise SystemExit("FP32 comparison failed; candidate is not admitted")


if __name__ == "__main__":
main()
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