[Perf][SM70] Pace chunked prefill and unpin the D256 BM32 page size (#490)

[areslp]

Rebased onto main and narrowed.

The kernel half of the original PR — running the small-query rows of a mixed prefill+decode batch on the paged decode kernels instead of the per-sequence paged prefill kernel — has since landed on main in 8a10215d6, where the flag is on by default. That part is dropped here. What remains is the two pieces that are not in main, both default-off:

1. VLLM_1CAT_PREFILL_PACE_STEPS=N (default 0) — while any running request is decoding, a request still in prompt prefill is given a chunk only every N engine steps, through the existing Request.next_decode_eligible_step gate; the other N-1 steps are decode-only. A prefill with nothing else decoding keeps its full budget. This is the GPU-time-sharing half of #490, which the kernel fix does not address: the resident decoder's own row is now cheap, but it still shares each step with the prefill chunk.

2. VLLM_FLASH_V100_PREFILL_D256_BM32_ANY_PAGE=1 (default off) — with MTP the Mamba page gains num_spec conv slots, the align-mode attention block becomes 816 instead of 784, and every paged-prefill chunk call fell off the BM32 phase kernel's page-784-only fast path (104 ms instead of 44 ms per 784-token chunk at 104K context). The kernel only used 784 to map each 16-token page slot, so the gate now accepts any multiple of 16 when the flag is set. Page 784 keeps its existing gate and code path.

Measurements

Pacing, on 2x V100-PCIE-32GB TP2, Qwen3.8-27B-QUASAR-NVFP4, fp16 KV, MTP4, a decoder resident at 240,000 tokens, fixed prompts, zero preemptions:

pacing N	resident decode during a 16K prefill	16K prefill wait
0	4.2 tok/s	21.3 s
4	11.1 tok/s	31.9 s
8	14.6 tok/s	45.6 s

@Leonccaa measured the same trade-off independently on a different config (4x V100-PCIE-32GB TP4, Qwen3.8 Flash-Next AWQ, MTP3, FP16 KV, two residents at ~170K/175K, a cold 14,023-token prefill injected):

arm	resident decode while the 14K prefill runs	14K TTFT
all off	12.7 tok/s	20.8 s
+ pacing 4	30.0 tok/s	23.0 s

That is 2.35x for the resident decoder at +10.8% TTFT for the injected prefill, on a model and quantization this branch was never tuned against.

Any-page: page 816/896 go from 104.4 ms to 43.99 ms standalone, bit-identical to the page-784 path and to a dense reference. End to end (MTP4, resident decoder at 240,000 tokens): a partner 131K prefill drops from 314.7 s to 207.9 s; with pacing 4 it drops from 400.1 s to 293.8 s while the resident decoder runs 9.86 tok/s, up from 7.38.

Tests

• tests/v1/core/test_prefill_pacing.py (new): chunk cadence at N = 0/2/4, the decoder keeping its slot in every step, and a lone prefill staying unpaced.
• tests/kernels/attention/test_sm70_flash_v100_paged_prefill_any_page.py: pages 784/816/896 against the dense reference, with the flag off and on.

With both flags unset the scheduler and the kernel dispatch are unchanged.

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[Leonccaa]

I replaced my earlier comment because it used the wrong workload for evaluating #616. The relevant test is a mixed phase: two resident long-context requests (A/B, about 170K/175K tokens) are decoding, then a third cold 14,023-token prefill (C) is injected. This directly measures the prefill/decode trade-off.

Test setup: CT252, 4x Tesla V100-PCIE-32GB, Qwen3.8 Flash-Next AWQ, TP4, MTP3, FP16 KV, 493,491-token KV capacity, max_num_batched_tokens=8192. The four arms used the same rebuilt native extension and passed the cache/output audit.

Arm	A decode before C, paired with B (tok/s)	A decode while C prefills (tok/s)	C TTFT	C admission to first token
#616 flags off	69.185	12.736	20.799 s	6.083 s
PREFIX_DECODE_ROWS=1	68.972	12.748	22.491 s	6.706 s
PREFIX_DECODE_ROWS=1 + BM32_ANY_PAGE=1	69.064	12.237	22.477 s	6.903 s
+ PACE_STEPS=4	69.000	29.983	23.048 s	8.704 s

The result is a clear trade-off. In this QSA/Flash-Next workload, the rows and any-page flags did not improve the active decoder by themselves. The pacing knob was the effective part: it raised A's decode rate during C's prefill by about 2.35x versus the all-off control (2.45x versus the rows+any-page arm), while increasing C's TTFT by 2.25 s (+10.8%) and admission-to-first-token by 2.62 s (+43.1%). The normal A+B decode rate before C stayed about 69 tok/s in every arm, so the change protects an existing decode stream during prefill rather than increasing steady-state decode throughput.

This is the evidence I should have reported for #616. It supports the mixed-prefill/decode fix and makes the latency cost explicit; it is separate from the prefix-cache retention issue addressed by #617. Raw logs and the analysis are in staging/ct252-c2-decode-20260912/gpu-validation/ (plus616-*-impact*.log) in our fork.

[areslp]

Thanks — that's the arm that matters, and it confirms the split. The rows fix landed on main in 8a10215d6 (now default on), so I've rebased this PR down to the two pieces main doesn't have: the pacing knob and the BM32 any-page gate. Your TP4/AWQ/MTP3 numbers are now quoted in the description as independent validation of the pacing trade-off.