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Update submodule: adn_uart
CICD
#209:
Commit
9722fe7
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main
main
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Update submodule: adn_uart
CICD
#208:
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1854638
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main
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Update submodule: adn_uart
CICD
#207:
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Merge branch 'main' into 27-fix-the-parity-generator-updated-port-nam…
CICD
#206:
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27-fix-the-parity-generator-updated-port-name-in-my-instantiation
27-fix-the-parity-generator-updated-port-name-in-my-instantiation
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Merge pull request #24 from ADN-VLSI/9-adn-uart-tx-rx-testbench1
CICD
#205:
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Merge branch 'main' into 9-adn-uart-tx-rx-testbench1
CICD
#204:
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9-adn-uart-tx-rx-testbench1
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Add UART TX RX testbench
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deleted: documenter
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parity generator port name updated
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Merge pull request #27 from ADN-VLSI/26-fix-the-parity-generator-upda…
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Update submodule: adn_uart
CICD
#199:
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fixed the parity generator updated port name in my instantiation
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27-fix-the-parity-generator-updated-port-name-in-my-instantiation
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fixed the parity generator updated port name in my instantiation
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Merge pull request #25 from ADN-VLSI/17-create-uart-register-interfac…
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27-fix-the-parity-generator-updated-port-name-in-my-instantiation
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parity generator port name updated
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26-fix-the-parity-generator-updated-port-name-in-my-instantiation
26-fix-the-parity-generator-updated-port-name-in-my-instantiation
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Merge pull request #25 from ADN-VLSI/17-create-uart-register-interfac…
CICD
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fix the parity generator updated port name in my instantiation
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#11:
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Merge branch 'main' into 9-adn-uart-tx-rx-testbench1
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#193:
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Merge pull request #25 from ADN-VLSI/17-create-uart-register-interfac…
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auto-update
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17-create-uart-register-interface-based-on-pmi
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Merge branch '17-create-uart-register-interface-based-on-pmi' of http…
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auto-update
CICD
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17-create-uart-register-interface-based-on-pmi
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modified: source/adn_uart_register_interface.sv
CICD
#188:
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17-create-uart-register-interface-based-on-pmi
17-create-uart-register-interface-based-on-pmi
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modified: source/adn_uart_register_interface.sv
CICD
#187:
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17-create-uart-register-interface-based-on-pmi
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Merge branch '17-create-uart-register-interface-based-on-pmi' of http…
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#186:
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