smmu: Add negative test for SMMU_02

apps/uefi/Bsa.inf

@@ -217,11 +217,11 @@
   ../../test_pool/smmu/i017.c
   ../../test_pool/smmu/i018.c
   ../../test_pool/smmu/i019.c
-  ../../test_pool/smmu/i020.c
   ../../test_pool/smmu/i021.c
   ../../test_pool/smmu/i022.c
   ../../test_pool/smmu/i024.c
   ../../test_pool/smmu/i025.c
+  ../../test_pool/smmu/i026.c
   ../../test_pool/memory_map/m005.c
   ../../test_pool/pcie/p004.c
   ../../test_pool/pcie/p005.c

apps/uefi/Sbsa.inf

@@ -218,11 +218,11 @@
   ../../test_pool/smmu/i017.c
   ../../test_pool/smmu/i018.c
   ../../test_pool/smmu/i019.c
-  ../../test_pool/smmu/i020.c
   ../../test_pool/smmu/i021.c
   ../../test_pool/smmu/i022.c
   ../../test_pool/smmu/i024.c
   ../../test_pool/smmu/i025.c
+  ../../test_pool/smmu/i026.c
   ../../test_pool/memory_map/m005.c
   ../../test_pool/pcie/p004.c
   ../../test_pool/pcie/p005.c

apps/uefi/SbsaNist.inf

@@ -83,6 +83,7 @@
   ../../test_pool/gic/g016.c
   ../../test_pool/timer/t006.c
   ../../test_pool/watchdog/w003.c
+  ../../test_pool/smmu/i007.c
   ../../test_pool/smmu/i008.c
   ../../test_pool/smmu/i009.c
   ../../test_pool/smmu/i010.c
@@ -94,11 +95,11 @@
   ../../test_pool/smmu/i017.c
   ../../test_pool/smmu/i018.c
   ../../test_pool/smmu/i019.c
-  ../../test_pool/smmu/i020.c
   ../../test_pool/smmu/i021.c
   ../../test_pool/smmu/i022.c
   ../../test_pool/smmu/i024.c
   ../../test_pool/smmu/i025.c
+  ../../test_pool/smmu/i026.c
   ../../test_pool/memory_map/m001.c
   ../../test_pool/memory_map/m005.c
   ../../test_pool/pcie/p001.c

apps/uefi/Vbsa.inf

@@ -220,11 +220,11 @@
   ../../test_pool/smmu/i017.c
   ../../test_pool/smmu/i018.c
   ../../test_pool/smmu/i019.c
-  ../../test_pool/smmu/i020.c
   ../../test_pool/smmu/i021.c
   ../../test_pool/smmu/i022.c
   ../../test_pool/smmu/i024.c
   ../../test_pool/smmu/i025.c
+  ../../test_pool/smmu/i026.c
   ../../test_pool/memory_map/m005.c
   ../../test_pool/pcie/p004.c
   ../../test_pool/pcie/p005.c

apps/uefi/pc_bsa.inf

@@ -218,11 +218,11 @@
   ../../test_pool/smmu/i017.c
   ../../test_pool/smmu/i018.c
   ../../test_pool/smmu/i019.c
-  ../../test_pool/smmu/i020.c
   ../../test_pool/smmu/i021.c
   ../../test_pool/smmu/i022.c
   ../../test_pool/smmu/i024.c
   ../../test_pool/smmu/i025.c
+  ../../test_pool/smmu/i026.c
   ../../test_pool/memory_map/m005.c
   ../../test_pool/pcie/p004.c
   ../../test_pool/pcie/p005.c

apps/uefi/xbsa_acpi.inf

@@ -214,11 +214,11 @@
   ../../test_pool/smmu/i017.c
   ../../test_pool/smmu/i018.c
   ../../test_pool/smmu/i019.c
-  ../../test_pool/smmu/i020.c
   ../../test_pool/smmu/i021.c
   ../../test_pool/smmu/i022.c
   ../../test_pool/smmu/i024.c
   ../../test_pool/smmu/i025.c
+  ../../test_pool/smmu/i026.c
   ../../test_pool/memory_map/m005.c
   ../../test_pool/pcie/p004.c
   ../../test_pool/pcie/p005.c

docs/bsa/arm_bsa_testcase_checklist.md

@@ -681,7 +681,7 @@ The checklist provides information about:
       <td></td>
       <td></td>
       <td></td>
-      <td></td>
+      <td>ACS detects advertised stall support through IDR0.STALL_MODEL only; rule compliance requires integration/DV evidence.</td>
       <td></td>
     </tr>
     <tr>

docs/pc_bsa/arm_pc-bsa_testcase_checklist.md

@@ -236,15 +236,23 @@ The checklist provides information about:
       <td>No</td>
     </tr>
     <tr>
-      <td>320</td>
-      <td>Check SMMU Coherent Access Support</td>
-      <td>1</td>
-      <td>P_L1SM_04</td>
+      <td>307</td>
+      <td>SMMU_01: SMMUv3 Integration compliance</td>
+      <td rowspan="2">1</td>
+      <td rowspan="2">P_L1SM_04</td>
       <td>Yes</td>
       <td>Yes</td>
       <td>Yes</td>
       <td>No</td>
     </tr>
+    <tr>
+      <td>Not Covered</td>
+      <td>SMMU_02: ACS detects advertised stall support through IDR0.STALL_MODEL only; rule compliance requires integration/DV evidence.</td>
+      <td>No</td>
+      <td></td>
+      <td></td>
+      <td></td>
+    </tr>
     <tr>
       <td>322</td>
       <td>Check if all DMA reqs behind SMMU</td>

docs/sbsa/arm_sbsa_testcase_checklist.md

@@ -314,17 +314,27 @@ The checklist provides information about:
       <td></td>
     </tr>
     <tr>
-      <td>L4</td>
-      <td>S_L4SM_03</td>
-      <td>S_L4SM_03</td>
-      <td>320</td>
-      <td>Check SMMU Coherent Access Support</td>
+      <td rowspan="2">L4</td>
+      <td rowspan="2">S_L4SM_03</td>
+      <td>SMMU_01</td>
+      <td>307</td>
+      <td>SMMUv3 Integration compliance</td>
       <td>Yes</td>
       <td>Yes</td>
       <td>No</td>
       <td></td>
       <td></td>
     </tr>
+    <tr>
+      <td>SMMU_02</td>
+      <td>Not Covered</td>
+      <td></td>
+      <td></td>
+      <td></td>
+      <td></td>
+      <td>ACS detects advertised stall support through IDR0.STALL_MODEL only; rule compliance requires integration/DV evidence.</td>
+      <td></td>
+    </tr>
     <tr>
       <td>L4</td>
       <td>S_L4PCI_1</td>

test_pool/smmu/i007.c

@@ -34,13 +34,6 @@ payload()
 
   index = val_pe_get_index_mpid(val_pe_get_mpid());
 
-  data = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0);
-  if (data == 0) {
-      val_print(WARN, "\n       PCIe Subsystem not  discovered   ");
-      val_set_status(index, RESULT_SKIP(1));
-      return;
-  }
-
   num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0);
 
   if (num_smmu == 0) {

test_pool/smmu/i026.c

@@ -0,0 +1,100 @@
+/** @file
+ * Copyright (c) 2025-2026, Arm Limited or its affiliates. All rights reserved.
+ * SPDX-License-Identifier : Apache-2.0
+
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ **/
+
+#include "acs_val.h"
+#include "acs_pe.h"
+#include "val_interface.h"
+#include "acs_smmu.h"
+
+#define TEST_NUM   (ACS_SMMU_TEST_NUM_BASE + 32)
+#define TEST_RULE  "SMMU_02"
+#define TEST_DESC  "Check SMMU stall flow support             "
+
+#define SMMU_STALL_MODEL_TERMINATE  0x1
+
+static
+void
+payload()
+{
+  uint32_t index;
+  uint32_t num_smmu;
+  uint32_t smmu_index;
+  uint32_t stall_model;
+  uint32_t relevant_smmu = 0;
+  uint32_t stall_supported = 0;
+
+  index = val_pe_get_index_mpid(val_pe_get_mpid());
+  num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0);
+
+  if (num_smmu == 0) {
+    val_print(DEBUG, "\n       No SMMU Controllers are discovered");
+    val_set_status(index, RESULT_SKIP(1));
+    return;
+  }
+
+  for (smmu_index = 0; smmu_index < num_smmu; smmu_index++) {
+    /* IDR0.STALL_MODEL is defined for SMMUv3 controllers. */
+    if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, smmu_index) < 3) {
+      val_print(DEBUG, "\n       SMMU %x is not an SMMUv3 controller", smmu_index);
+      continue;
+    }
+
+    relevant_smmu++;
+    stall_model = VAL_EXTRACT_BITS(
+                      val_smmu_read_cfg(SMMUv3_IDR0, smmu_index), 24, 25);
+
+    val_print(DEBUG, "\n       SMMU %x IDR0.STALL_MODEL = 0x%x",
+              smmu_index, stall_model);
+
+    if (stall_model != SMMU_STALL_MODEL_TERMINATE)
+      stall_supported = 1;
+  }
+
+  if (relevant_smmu == 0) {
+    val_print(DEBUG, "\n       SMMU_02 not applicable: No SMMUv3 controllers");
+    val_set_status(index, RESULT_SKIP(2));
+    return;
+  }
+
+  if (!stall_supported) {
+    val_print(INFO, "\n       SMMU_02 not applicable: Stall model is not supported");
+    val_set_status(index, RESULT_SKIP(3));
+    return;
+  }
+
+  val_print(WARN, "\n       Stall supported - integration/DV evidence required");
+  val_set_status(index, RESULT_WARNING(1));
+}
+
+uint32_t
+i032_entry(uint32_t num_pe)
+{
+  uint32_t status = ACS_STATUS_FAIL;
+
+  num_pe = 1;  // This test is run on a single processor
+
+  val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__);
+  status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe);
+
+  if (status != ACS_STATUS_SKIP)
+    val_run_test_payload(TEST_NUM, num_pe, payload, 0);
+
+  status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE);
+  val_report_status(0, ACS_END(TEST_NUM), TEST_RULE);
+
+  return status;
+}

tools/cmake/infra/bsa_test.txt

@@ -84,6 +84,7 @@ i017.c
 i018.c
 i019.c
 i025.c
+i026.c
 p001.c
 p002.c
 p003.c

tools/cmake/infra/pc_bsa_test.txt

@@ -45,9 +45,9 @@ i005.c
 i006.c
 i007.c
 i008.c
-i020.c
 i022.c
 i025.c
+i026.c
 m001.c
 m002.c
 m003.c

tools/cmake/infra/sbsa_test.txt

@@ -56,12 +56,12 @@ i016.c
 i017.c
 i018.c
 i019.c
-i020.c
 i021.c
 i022.c
 i023.c
 i024.c
 i025.c
+i026.c
 m005.c
 p001.c
 p002.c