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add GICv3 validation to B_GIC_02 #545

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611b4b2
gic: Add GICv3 validation for B_GIC_02
SapthagiriP Sep 16, 2026
cee36c9
bsa : consolidate B_GIC_02 tests and remove appendix metadata
SapthagiriP Sep 18, 2026
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86 changes: 40 additions & 46 deletions docs/bsa/arm_bsa_testcase_checklist.md
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Expand Up @@ -394,11 +394,47 @@ The checklist provides information about:
<td></td>
</tr>
<tr>
<td>L1</td>
<td>B_GIC_02</td>
<td>B_GIC_02</td>
<td rowspan="5">L1</td>
<td rowspan="5">B_GIC_02</td>
<td rowspan="5">B_GIC_02</td>
<td>202</td>
<td>Check GICv2 Valid Configuration</td>
<td>Check GIC Valid Configuration</td>
<td>Yes</td>
<td>Yes</td>
<td>No</td>
<td></td>
<td></td>
</tr>
<tr>
<td>229</td>
<td>Check GICv2m SPI allocated to MSI Ctrl</td>
<td>Yes</td>
<td>Yes</td>
<td>No</td>
<td></td>
<td></td>
</tr>
<tr>
<td>226</td>
<td>Check MSI SPI are Edge Triggered</td>
<td>Yes</td>
<td>Yes</td>
<td>No</td>
<td></td>
<td></td>
</tr>
<tr>
<td>228</td>
<td>Check GICv2m MSI to SPI Generation</td>
<td>Yes</td>
<td>Yes</td>
<td>No</td>
<td></td>
<td></td>
</tr>
<tr>
<td>227</td>
<td>Check GICv2m MSI Frame Register</td>
<td>Yes</td>
<td>Yes</td>
<td>No</td>
Expand Down Expand Up @@ -516,48 +552,6 @@ The checklist provides information about:
<td>No</td>
<td>Requires ACS SMC handler support in EL3 firmware</td>
</tr>
<tr>
<td rowspan="4">L1</td>
<td rowspan="4">B_GIC_02</td>
<td>Appendix I.5</td>
<td>229</td>
<td>Check GICv2m SPI allocated to MSI Ctrl</td>
<td>Yes</td>
<td>Yes</td>
<td>No</td>
<td></td>
<td></td>
</tr>
<tr>
<td>Appendix I.6</td>
<td>226</td>
<td>Check MSI SPI are Edge Triggered</td>
<td>Yes</td>
<td>Yes</td>
<td>No</td>
<td></td>
<td></td>
</tr>
<tr>
<td>Appendix I.6</td>
<td>228</td>
<td>Check GICv2m MSI to SPI Generation</td>
<td>Yes</td>
<td>Yes</td>
<td>No</td>
<td></td>
<td></td>
</tr>
<tr>
<td>Appendix I.9</td>
<td>227</td>
<td>Check GICv2m MSI Frame Register</td>
<td>Yes</td>
<td>Yes</td>
<td>No</td>
<td></td>
<td></td>
</tr>
<tr>
<td>L1</td>
<td>B_SMMU_01</td>
Expand Down
49 changes: 40 additions & 9 deletions test_pool/gic/g002.c
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Expand Up @@ -23,37 +23,68 @@

#define TEST_NUM (ACS_GIC_TEST_NUM_BASE + 2)
#define TEST_RULE "B_GIC_02"
#define TEST_DESC "Check GICv2 Valid Configuration "
#define TEST_DESC "Check GIC Valid Configuration "

#define GIC_V2_MAX_PE 8U
#define GIC_V3_MAX_PE (1U << 28)

static
void
payload()
{
/* PE Limitations are covered in PE Rules */
/* GICv3 + No ITS is covered in RB_GIC_03 */

/* Check If PCIe Support and GicV2 -> Invalid Configuration */

uint32_t gic_version;
uint32_t num_msi_frame;
uint32_t num_its;
uint32_t lpi_support;
uint32_t pe_count;
uint32_t num_ecam = 0;
uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());

pe_count = val_pe_get_num();
num_ecam = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0);
gic_version = val_gic_get_info(GIC_INFO_VERSION);
num_msi_frame = val_gic_get_info(GIC_INFO_NUM_MSI_FRAME);
num_its = val_gic_get_info(GIC_INFO_NUM_ITS);

val_print(TRACE, "\n Received GIC version = %4d ", gic_version);

if (gic_version < 3) {
if (pe_count > GIC_V2_MAX_PE) {
val_print(ERROR, "\n GICv2 supports a maximum of %d PEs", GIC_V2_MAX_PE);
val_print(ERROR, ", but system has %d PEs", pe_count);
val_set_status(index, RESULT_FAIL(1));
return;
}

if ((num_ecam > 0) && (num_msi_frame == 0)) {
val_print(ERROR, "\n GICv2 with PCIe : Invalid Configuration");
val_set_status(index, RESULT_FAIL(1));
val_set_status(index, RESULT_FAIL(2));
return;
}
} else {
val_set_status(index, RESULT_SKIP(1));
return;
if (pe_count > GIC_V3_MAX_PE) {
val_print(ERROR, "\n GICv3 supports a maximum of 2^28 PEs");
val_print(ERROR, ", but system has %d PEs", pe_count);
val_set_status(index, RESULT_FAIL(3));
return;
}

if ((num_ecam > 0) && (num_its == 0)) {
val_print(ERROR, "\n GICv3 with PCIe and no ITS : Invalid Configuration");
val_set_status(index, RESULT_FAIL(4));
return;
}

if (num_its > 0) {
lpi_support = VAL_EXTRACT_BITS(
val_mmio_read(val_get_gicd_base() + GICD_TYPER),
GICV3_LPIS_BIT, GICV3_LPIS_BIT);
if (lpi_support == 0) {
val_print(ERROR, "\n GICv3 with ITS does not support LPIs");
val_set_status(index, RESULT_FAIL(5));
return;
}
}
}

val_set_status(index, RESULT_PASS);
Expand Down
3 changes: 2 additions & 1 deletion test_pool/gic/g003.c
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Expand Up @@ -47,7 +47,8 @@ payload()
return;
}

data = VAL_EXTRACT_BITS(val_mmio_read(val_get_gicd_base() + GICD_TYPER), 17, 17);
data = VAL_EXTRACT_BITS(val_mmio_read(val_get_gicd_base() + GICD_TYPER),
GICV3_LPIS_BIT, GICV3_LPIS_BIT);
if (data == 0)
{
val_print(ERROR, "\n GICv3 and PCIe : LPI Not Supported");
Expand Down
2 changes: 2 additions & 0 deletions val/include/acs_gic.h
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Expand Up @@ -50,6 +50,8 @@
#define GICv2m_MSI_SETSPI 0x040
#define GICv2m_MSI_IIDR 0xFCC

#define GICV3_LPIS_BIT 17

/**
@brief structure instance for MSI Frame Entry
**/
Expand Down
5 changes: 1 addition & 4 deletions val/include/rule_based_execution_enum.h
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Expand Up @@ -135,9 +135,6 @@ typedef enum {
S_L5GI_01,
S_L5PP_01,
S_L8GI_01,
Appendix_I_5, /* Appendix I.5 remapped to a legal identifier */
Appendix_I_6, /* Appendix I.6 remapped */
Appendix_I_9, /* Appendix I.9 remapped */
P_L1GI_01,
P_L1GI_02,
P_L1GI_03,
Expand Down Expand Up @@ -663,6 +660,7 @@ typedef enum {
PE065_ENTRY,
G001_ENTRY,
G002_ENTRY,
B_GIC_02_ENTRY,
G003_ENTRY,
G004_ENTRY,
G005_ENTRY,
Expand Down Expand Up @@ -692,7 +690,6 @@ typedef enum {
G015_ENTRY,
V2M004_ENTRY,
V2M001_ENTRY,
APPENDIX_I_6_ENTRY,
V2M002_ENTRY,
V2M003_ENTRY,
D001_ENTRY,
Expand Down
2 changes: 1 addition & 1 deletion val/include/test_wrappers.h
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Expand Up @@ -22,13 +22,13 @@
#ifndef TEST_WRAPPERS_H
#define TEST_WRAPPERS_H

uint32_t b_gic_02_entry(uint32_t num_pe);
uint32_t b_ppi_00_entry(uint32_t num_pe);
uint32_t b_ppi_01_entry(uint32_t num_pe);
uint32_t b_ppi_02_entry(uint32_t num_pe);
uint32_t b_ppi_03_entry(uint32_t num_pe);
uint32_t b_wak_03_07_entry(uint32_t num_pe);
uint32_t s_l7mp_03_entry(uint32_t num_pe);
uint32_t appendix_i_6_entry(uint32_t num_pe);
uint32_t ie_reg_1_entry(uint32_t num_pe);
uint32_t pci_ic_11_entry(uint32_t num_pe);
uint32_t pci_in_04_entry(uint32_t num_pe);
Expand Down
1 change: 1 addition & 0 deletions val/include/val_interface.h
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Expand Up @@ -210,6 +210,7 @@ typedef enum {
V2M_MSI_FLAGS
} V2M_MSI_INFO_e;

uint32_t val_gic_is_v2m(void);
uint32_t val_gic_v2m_parse_info(void);
uint64_t val_gic_v2m_get_info(V2M_MSI_INFO_e type, uint32_t instance);
void val_gic_free_info_table(void);
Expand Down
7 changes: 7 additions & 0 deletions val/src/acs_gic_v2m.c
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Expand Up @@ -25,6 +25,13 @@
extern GIC_INFO_TABLE * g_gic_info_table;
GICv2m_MSI_FRAME_INFO *g_v2m_msi_info;

uint32_t
val_gic_is_v2m(void)
{
return ((val_gic_get_info(GIC_INFO_VERSION) == 2) &&
(val_gic_get_info(GIC_INFO_NUM_MSI_FRAME) > 0));
}

/**
@brief This function parses the V2M MSI Information from gic info table
1. Caller - Validation Layer
Expand Down
10 changes: 3 additions & 7 deletions val/src/bsa_execute_test.c
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Expand Up @@ -195,7 +195,7 @@ val_bsa_gic_execute_tests(uint32_t num_pe, uint32_t *g_sw_view)
{

uint32_t status, i;
uint32_t gic_version, num_msi_frame;
uint32_t gic_version;

if (!(g_bsa_level >= 1 || g_bsa_only_level == 1))
return ACS_STATUS_SKIP;
Expand Down Expand Up @@ -229,9 +229,7 @@ val_bsa_gic_execute_tests(uint32_t num_pe, uint32_t *g_sw_view)
/* B_GIC_01 and B_GIC_02 only for BSA */
if (!g_build_sbsa) {
status |= g001_entry(num_pe);
/* Run B_GIC_02 test only if system has GICv2 */
if (gic_version == 2)
status |= g002_entry(num_pe);
status |= g002_entry(num_pe);
}
if (gic_version > 2) {
status |= g003_entry(num_pe);
Expand Down Expand Up @@ -262,9 +260,7 @@ val_bsa_gic_execute_tests(uint32_t num_pe, uint32_t *g_sw_view)
if (g_bsa_level >= 1 || g_bsa_only_level == 1) {

/* Run GICv2m only if GIC Version is v2m. */
num_msi_frame = val_gic_get_info(GIC_INFO_NUM_MSI_FRAME);

if ((gic_version != 2) || (num_msi_frame == 0)) {
if (!val_gic_is_v2m()) {
val_print(TRACE, "\n No GICv2m, Skipping all GICv2m tests\n");
goto its_test;
}
Expand Down
4 changes: 0 additions & 4 deletions val/src/rule_enum_string_map.c
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Expand Up @@ -117,10 +117,6 @@ char *rule_id_string[RULE_ID_SENTINEL] = {
[S_L5GI_01] = "S_L5GI_01",
[S_L5PP_01] = "S_L5PP_01",
[S_L8GI_01] = "S_L8GI_01",
[Appendix_I_5] = "Appendix_I_5",
[Appendix_I_6] = "Appendix_I_6",
[Appendix_I_9] = "Appendix_I_9",

/* PERIPHERAL rules */
[B_PER_01] = "B_PER_01",
[B_PER_02] = "B_PER_02",
Expand Down
32 changes: 5 additions & 27 deletions val/src/rule_metadata.c
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Expand Up @@ -602,9 +602,9 @@ rule_test_map_t rule_test_map[RULE_ID_SENTINEL] = {
.test_num = ACS_GIC_TEST_NUM_BASE + 1,
},
[B_GIC_02] = {
.test_entry_id = G002_ENTRY,
.test_entry_id = B_GIC_02_ENTRY,
.module_id = GIC,
.rule_desc = "Check GICv2 Valid Configuration",
.rule_desc = "Check GIC Valid Configuration",
.platform_bitmask = PLATFORM_BAREMETAL | PLATFORM_UEFI,
.flag = BASE_RULE,
.test_num = ACS_GIC_TEST_NUM_BASE + 2,
Expand Down Expand Up @@ -757,29 +757,6 @@ rule_test_map_t rule_test_map[RULE_ID_SENTINEL] = {
.flag = BASE_RULE,
.test_num = ACS_GIC_TEST_NUM_BASE + 15,
},
[Appendix_I_5] = {
.test_entry_id = V2M004_ENTRY,
.module_id = GIC,
.rule_desc = "Check GICv2m SPI allocated to MSI Ctrl",
.platform_bitmask = PLATFORM_BAREMETAL | PLATFORM_UEFI,
.flag = BASE_RULE,
.test_num = ACS_GIC_V2M_TEST_NUM_BASE + 4,
},
[Appendix_I_6] = {
.test_entry_id = APPENDIX_I_6_ENTRY,
.module_id = GIC,
.rule_desc = "",
.platform_bitmask = PLATFORM_BAREMETAL | PLATFORM_UEFI,
.flag = BASE_RULE,
},
[Appendix_I_9] = {
.test_entry_id = V2M002_ENTRY,
.module_id = GIC,
.rule_desc = "Check GICv2m MSI Frame Register",
.platform_bitmask = PLATFORM_BAREMETAL | PLATFORM_UEFI,
.flag = BASE_RULE,
.test_num = ACS_GIC_V2M_TEST_NUM_BASE + 2,
},
/* PERIPHERAL */
[B_PER_01] = {
.test_entry_id = D001_ENTRY,
Expand Down Expand Up @@ -3594,6 +3571,7 @@ test_entry_fn_t test_entry_func_table[TEST_ENTRY_SENTINEL] = {
[ETE009_ENTRY] = ete009_entry,
[G001_ENTRY] = g001_entry,
[G002_ENTRY] = g002_entry,
[B_GIC_02_ENTRY] = b_gic_02_entry,
[G003_ENTRY] = g003_entry,
[G004_ENTRY] = g004_entry,
[G005_ENTRY] = g005_entry,
Expand All @@ -3614,7 +3592,6 @@ test_entry_fn_t test_entry_func_table[TEST_ENTRY_SENTINEL] = {
[B_WAK_03_07_ENTRY] = b_wak_03_07_entry,
[GPU_04_ENTRY] = gpu_04_entry,
[S_L7MP_03_ENTRY] = s_l7mp_03_entry,
[APPENDIX_I_6_ENTRY] = appendix_i_6_entry,
[IE_REG_1_ENTRY] = ie_reg_1_entry,
[IE_REG_2_ENTRY] = ie_reg_2_entry,
[IE_REG_3_ENTRY] = ie_reg_3_entry,
Expand Down Expand Up @@ -3987,6 +3964,7 @@ test_entry_fn_t test_entry_func_table[TEST_ENTRY_SENTINEL] = {
[PE070_ENTRY] = pe070_entry,
[G001_ENTRY] = g001_entry,
[G002_ENTRY] = g002_entry,
[B_GIC_02_ENTRY] = b_gic_02_entry,
[G003_ENTRY] = g003_entry,
[G004_ENTRY] = g004_entry,
[G005_ENTRY] = g005_entry,
Expand Down Expand Up @@ -4325,7 +4303,6 @@ test_entry_fn_t test_entry_func_table[TEST_ENTRY_SENTINEL] = {
[B_PPI_03_ENTRY] = b_ppi_03_entry,
[B_WAK_03_07_ENTRY] = b_wak_03_07_entry,
[S_L7MP_03_ENTRY] = s_l7mp_03_entry,
[APPENDIX_I_6_ENTRY] = appendix_i_6_entry,
[IE_REG_1_ENTRY] = ie_reg_1_entry,
[IE_REG_2_ENTRY] = ie_reg_2_entry,
[IE_REG_3_ENTRY] = ie_reg_3_entry,
Expand All @@ -4351,6 +4328,7 @@ test_entry_fn_t test_entry_func_table[TEST_ENTRY_SENTINEL] = {
[CXL_11_ENTRY] = cxl_11_entry,
[CXL_12_ENTRY] = cxl_12_entry,
[G002_ENTRY] = g002_entry,
[B_GIC_02_ENTRY] = b_gic_02_entry,
[ITS002_ENTRY] = its002_entry,
[ITS005_ENTRY] = its005_entry,
[ITS006_ENTRY] = its006_entry,
Expand Down
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