Skip to content
View Adnan259's full-sized avatar

Block or report Adnan259

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. SV-ALU-DV-Environment SV-ALU-DV-Environment Public

    SystemVerilog-based design verification environment for an 8-bit ALU with transaction-level stimulus, scoreboard checking, and asynchronous reset support.

    SystemVerilog

  2. SV-uart-with-tb SV-uart-with-tb Public

    RTL design and verification of a UART module in SystemVerilog, including transmitter, receiver, and testbench.

    SystemVerilog

  3. ALU ALU Public

  4. Adnan259 Adnan259 Public

    Personal portfolio and professional profile of an RTL Design & Verification Intern @ ADN Semiconductor.

  5. Practice-RTL-DV Practice-RTL-DV Public

    simulate my thought

    SystemVerilog

  6. WISHBONE-MEMORY WISHBONE-MEMORY Public

    WISHBONE B3 compliant memory slave IP core β€” learning project implementing the FASM synchronous RAM model with a two-module architecture (controller + memory array).

    SystemVerilog