This project is incomplete!
Designing, testing, and implementing the Full-Adder for use in digital logic circuits
This repository documents the complete design, simulation, and analysis of a 1-bit full-adder circuit. The project focuses on implementation using Transistor-level CMOS, focusing on metrics like propagation delay (speed indication) and power consumption, and Verilog HDL for digital modeling and verification.
- To design, simulate, and implement a 1-bit full-adder circuit using CMOS technology.
- Verify functionality through testbench and simulation
The full adder computes the sum of three inputs: A, B, and Carry-In (Cin). It produces two outputs: Sum and Carry-Out (Cout).
| A | B | Cin | Sum | Cout |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 | 1 |
| 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 | 1 |
-
Sum =
$A \oplus B \oplus C_{in}$ -
Cout =
$(A \cdot B) + (C_{in} \cdot (A \oplus B))$
Verilog will be used to model the function of an ideal full-adder.
- Style: Behavioral & Structural Dataflow modeling.
- Testbench: A self-checking testbench that cycles through all 8 input vectors.
LTspice will be used to model the circuits with CMOS technology
- Technology: CMOS uses Complementary Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs).
- Structure: Logic gates constructed using PMOS (pull-up network) and NMOS (pull-down network) transistors.
- Simulation: Transient analysis performed to verify signal propagation and voltage levels.
- How it Works: In a steady state (Logic 0 or 1), one of the transistors in the pair is always "OFF." This prevents a direct path from power to ground.
- Key Characteristic: It consumes almost zero static power. Power is only consumed during the switching moment (dynamic power).
- It dissipates very little heat and can be made microscopic, it allows us to pack billions of transistors onto modern CPUs and GPUs.
- A basic CMOS inverted is shown below:
What will actually be implemented in LTspice is as shown below. The AND gate consists of a NAND gate and an inverter, the OR gate is constructed with a similar manner. This is because the NOR and NAND gates are universal gates and the CMOS structure with the pull-up and pull-down networks do not provide AND gates or OR gates directly.
