Traffic Light Controller (Verilog)

This project implements a clock-driven finite state machine (FSM)–based Traffic Light Controller using Verilog HDL, along with a testbench and waveform-based verification.

The controller cycles through the traffic lights in the following order:

RED → GREEN → YELLOW → RED

Each transition occurs on the positive edge of the clock.

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Repository Structure

TRAFFIC-LIGHT-CONTROLLER/
├── images/
│   └── traffic_light_controller_waveform.png
├── traffic_light_controller.v
├── traffic_light_controller_tb.v
└── README.md

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Design Overview

FSM Type

• Moore Machine
• Outputs depend only on the current state
• Fully synchronous design

State Encoding

State	Binary Encoding
RED	2'b00
GREEN	2'b01
YELLOW	2'b10

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Module Description

Interface

module traffic_light_controller(
    input  clk,
    output reg red,
    output reg green,
    output reg yellow
);

Functional Behavior

• A 2-bit state register holds the current traffic light state
• On every posedge of clk, the state advances to the next light
• Exactly one output is asserted HIGH at any time
• Outputs are registered, ensuring glitch-free behavior

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State Transition Logic

always @(posedge clk) begin
    case(state)
        RED:    state <= GREEN;
        GREEN:  state <= YELLOW;
        YELLOW: state <= RED;
        default: state <= RED;
    endcase
end

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Output Logic

always @(posedge clk) begin
    red    <= (state == RED);
    yellow <= (state == YELLOW);
    green  <= (state == GREEN);
end

• Outputs change only on clock edges
• No combinational glitches
• Clean Moore-style output mapping

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Testbench Overview

Features

• Generates a continuous clock
• Instantiates the DUT
• Enables waveform observation for verification

Clock Generation

always begin
    clk = ~clk;
    #10000;
end

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Waveform Analysis

Observations from the Simulation

• clk toggles continuously and drives the FSM
• Outputs (red, green, yellow) assert one at a time
• Each output remains HIGH for exactly one clock cycle
• The sequence observed in the waveform is:

RED → GREEN → YELLOW → RED → ...

• No overlap between signals
• Output transitions occur strictly on posedge clk

This confirms correct FSM sequencing and synchronous behavior.

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Key Design Highlights

• Simple and readable FSM implementation

• Fully synchronous RTL

• Registered outputs (Moore machine)

• Ideal for:

  • FSM fundamentals
  • RTL design practice
  • Interview demonstrations

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Tools Used

• Verilog HDL
• ModelSim / Questa / Vivado / Icarus Verilog (any standard simulator)

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Author

Mohd Arhaan