UART (Universal Asynchronous Receiver Transmitter)

This repository contains a simple and complete Verilog implementation of a UART transmitter (TX) and receiver (RX), along with self-checking testbenches and simulation results. The design is implemented and verified using EDA Playground.

The UART supports 8-bit data transmission, 1 start bit, 1 stop bit, no parity, and operates using a 50 MHz system clock.

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Repository Structure

UART/
├── rtl/
│   ├── uart_rx.v        # UART Receiver RTL
│   └── uart_tx.v        # UART Transmitter RTL
├── tb/
│   ├── uart_rx_tb.v     # UART RX Testbench
│   ├── uart_tx_tb.v     # UART TX Testbench
│   └── uart_tb.v        # Integrated TX–RX Testbench
├── images/
│   ├── uart_rx_fsm.png
│   ├── uart_rx_waveform.png
│   ├── uart_tx_fsm.png
│   ├── uart_tx_waveform.png
│   └── uart_waveform.png
└── README.md

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UART Configuration

Parameter	Value
Clock	50 MHz
Baud Rate	115200
Data Bits	8
Parity	None
Stop Bits	1
Frame Format	1 Start + 8 Data + 1 Stop

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Design Overview

UART is an asynchronous serial communication protocol that converts:

• Parallel → Serial at the transmitter
• Serial → Parallel at the receiver

This design uses finite state machines (FSMs) for both TX and RX to manage bit-level timing and protocol sequencing.

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UART Receiver (RX)

Description

The receiver continuously monitors the rx line. When a start bit (logic 0) is detected, it samples incoming data bits at the baud-rate interval, reconstructs the 8-bit data, checks the stop bit, and asserts rx_complete when a valid byte is received.

RX FSM States

• IDLE – Waits for start bit
• START_BIT – Validates start bit
• DATA_BITS – Samples 8 data bits (LSB first)
• STOP_BIT – Validates stop bit and completes reception

RX FSM Diagram

RX Waveform

RX Module Interface

module uart_rx(
    input        clk_50M,     // 50 MHz system clock
    input        rx,           // Serial input
    output reg [7:0] rx_msg,   // Received data byte
    output reg   rx_complete   // High when byte is received
);

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UART Transmitter (TX)

Description

The transmitter sends data when tx_en is asserted. It frames the byte with a start bit, transmits 8 data bits (LSB first), appends a stop bit, and asserts tx_done after completion.

TX FSM States

• IDLE – Line held high, waiting for enable
• START_BIT – Sends start bit
• DATA_BITS – Sends 8 data bits
• STOP_BIT – Sends stop bit and completes transmission

TX FSM Diagram

TX Waveform

TX Module Interface

module uart_tx(
    input        clk_50M,   // 50 MHz system clock
    input        tx_en,      // Enable transmission
    input  [7:0] data,       // Data byte to transmit
    output reg   tx,         // Serial output
    output reg   tx_done     // High when transmission completes
);

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Integrated UART (TX → RX)

An integrated testbench connects the TX output directly to RX input, validating:

• Correct bit timing
• Proper framing
• Accurate data reconstruction

Combined TX–RX Waveform

The simulation log confirms successful operation:

# correct byte received
# correct byte received
# correct byte received

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Verification Strategy

• Self-checking testbenches
• Multiple data patterns transmitted
• Automatic pass/fail reporting
• FSM state visibility in simulation
• Full waveform inspection in ModelSim

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Tools Used

• EDA Playground

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Key Learning Outcomes

• UART protocol fundamentals
• FSM-based serial design
• Baud-rate timing from high-frequency clocks
• Bit-level data sampling and shifting
• Testbench-driven verification

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Future Improvements

• Configurable baud rate
• Parity bit support
• Multiple stop bits
• Oversampling for noise immunity
• FIFO-based buffering