32-bit non-pipelined RISC-V processor

This is an implementation of the computational, memory access and control flow instructions of the RV32I instruction set.

Name		Name	Last commit message	Last commit date
incremental_db		incremental_db
output_files		output_files
simulation		simulation
.gitignore		.gitignore
ALU.sv		ALU.sv
README.md		README.md
alu.sv.bak		alu.sv.bak
binary_to_7seg.sv		binary_to_7seg.sv
binary_to_7seg.sv.bak		binary_to_7seg.sv.bak
controller.sv		controller.sv
controller.sv.bak		controller.sv.bak
controls.sv		controls.sv
controls.sv.bak		controls.sv.bak
counter.sv		counter.sv
counter.sv.bak		counter.sv.bak
data_memory.sv		data_memory.sv
data_memory.sv.bak		data_memory.sv.bak
datapath.sv		datapath.sv
datapath.sv.bak		datapath.sv.bak
datapath_mem.sv		datapath_mem.sv
datapath_mem.sv.bak		datapath_mem.sv.bak
immgen.sv		immgen.sv
immgen.sv.bak		immgen.sv.bak
inst_memory.sv		inst_memory.sv
inst_memory.sv.bak		inst_memory.sv.bak
mux2.sv		mux2.sv
mux3.sv		mux3.sv
mux3.sv.bak		mux3.sv.bak
pccalc.sv		pccalc.sv
pccalc.sv.bak		pccalc.sv.bak
processor_fpga.sv		processor_fpga.sv
processor_fpga.sv.bak		processor_fpga.sv.bak
regfile.sv		regfile.sv
regfile.sv.bak		regfile.sv.bak
riscv_single_cycle_processor.qpf		riscv_single_cycle_processor.qpf
riscv_single_cycle_processor.qsf		riscv_single_cycle_processor.qsf
riscv_single_cycle_processor.qws		riscv_single_cycle_processor.qws
riscv_single_cycle_processor.sv		riscv_single_cycle_processor.sv
riscv_single_cycle_processor.sv.bak		riscv_single_cycle_processor.sv.bak
riscv_single_cycle_processor_nativelink_simulation.rpt		riscv_single_cycle_processor_nativelink_simulation.rpt
serv_req_info.txt		serv_req_info.txt

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