UART Transceiver implementation for FPGA

This is a project done for the EN2111 Electronic Circuit Design module in the Department of Electronic and Telecommunication Engineering, University of Moratuwa.

A UART communication link was implemented between two FPGA boards, and it was tested by giving binary numbers as inputs and displaying them on a 7-segment display in the receiver FPGA board.

Name		Name	Last commit message	Last commit date
DE2		DE2
output_files		output_files
simulation/modelsim		simulation/modelsim
.gitignore		.gitignore
README.md		README.md
binary_to_7seg.sv		binary_to_7seg.sv
binary_to_7seg.sv.bak		binary_to_7seg.sv.bak
receiver.sv		receiver.sv
receiver.sv.bak		receiver.sv.bak
testbench.sv		testbench.sv
testbench.sv.bak		testbench.sv.bak
trans_rec_tb.sv		trans_rec_tb.sv
trans_rec_tb.sv.bak		trans_rec_tb.sv.bak
transmitter.sv		transmitter.sv
transmitter.sv.bak		transmitter.sv.bak
transmitter_tb.sv		transmitter_tb.sv
transmitter_tb.sv.bak		transmitter_tb.sv.bak
uart.qpf		uart.qpf
uart.qsf		uart.qsf
uart.sv		uart.sv
uart.sv.bak		uart.sv.bak
uart_nativelink_simulation.rpt		uart_nativelink_simulation.rpt

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UART Transceiver implementation for FPGA

Timing Diagram in ModelSim simulation

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UART Transceiver implementation for FPGA

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