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Writing Bugs
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Writing Bugs

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@SEU-MSLab

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ataraxiaz/README.md

๐Ÿ’ซ About Me:

๐Ÿ”ญ Iโ€™m currently working on FPGA hardware and software co-design
๐Ÿ‘ฏ Iโ€™m looking to collaborate on anything about FPGA
๐ŸŒฑ Iโ€™m currently learning Linux, Chisel, SystemVerilog
๐Ÿ’ฌ Ask me about anything related to FPGA

๐Ÿ’ป Tech Stack:

Python C++ Scala PyTorch NumPy Pandas LINUX Trello

๐Ÿ“Š GitHub Stats:




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  1. SEU-MSLab/MP SEU-MSLab/MP Public

    The software and hardware implementation of Memory Polynomial algorithm

    SystemVerilog 9 5

  2. SEU-MSLab/PRVTDNN SEU-MSLab/PRVTDNN Public

    The Chisel design of Polyphase Real-Value Time-Delay Neural Network (PRVTDNN).

    Scala 2 1