dsp clean fault#3
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t32_misc_reverse keyed only on op2 (hw2[7:4]), ignoring op1 (hw1[7:4]). Its case-0x8 REV.W path accepted any op1, so ARMv7E-M DSP encodings (SXTAH/UXTAH/SXTB16/UXTB16/QADD/QSUB/QDADD/QDSUB/SEL) — UndefinedInstruction on Cortex-M3 — silently executed as reverse ops. Add an op1 gate: CLZ is op1==0xB & op2==8; the REV/REV16/RBIT/REVSH family is op1==0x9. Verified authoritative via -mcpu=cortex-m4 objdump (the M3 assembler rejects these instructions). Add V7emDspInstructionsCleanFault regression covering all 18 §4 DSP encodings. ctest 272/272 green, no regression.
…g sweep (T4) Add test_cortex_m3_loadstore.cpp: LDRD/STRD across the P/U/W/L matrix (imm offset / pre / post / negative) and single load/store .W imm8 modes (op B/9/F/D = post+/post-/pre+/pre-), asserting concrete values and writeback rather than round-trip. Add shifted-reg flag sweep to test_cortex_m3_advanced: ADD carry/overflow, SUB borrow, ROR operand — the arithmetic flag path after a shifter operand (T1a's shifter-carry→C fix), read via MRS APSR. Pure test additions, zero src change. ctest 286/286.
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