SystemVerilog Essentials

This repository contains a comprehensive collection of SystemVerilog practice codes, testbench architectures, and verification environments. It serves as a practical sandbox for mastering SystemVerilog fundamentals, Object-Oriented Programming (OOP) concepts, and robust testbench development.

📌 Overview

The code here ranges from foundational OOP principles to complete testbench architectures, including Interprocess Communication (IPC), randomization, constraints, and error injection techniques.

📂 Repository Structure & Topics

The repository files are categorized into the following key SystemVerilog domains:

1. Object-Oriented Programming (OOP)

Core concepts for building scalable and reusable verification components.

• inheritance_polymorphism.sv - Demonstrates class inheritance and virtual methods.
• deep_copy.sv & shallow_copy.sv - Explores object copying mechanisms.
• scope_extern.sv - Using external method declarations for cleaner class definitions.
• super_command.sv - Accessing parent class properties and methods.

2. Interprocess Communication (IPC)

Techniques for synchronizing concurrent processes within a testbench.

• Events: event_ipc.sv, event_with_class.sv, only_event_with_class.sv
• Mailboxes: mailbox_with_custom_constructor.sv, mailbox_with_parameter.sv, mailbox_with_transaction_class.sv
• Semaphores: semaphore.sv

3. Randomization & Constraints

Stimulus generation using SystemVerilog's constrained-random features.

• constraint_assertion.sv - Basic constraints and assertions.
• weighted_distribution.sv - Using dist for weighted random generation.
• implication_equivalence_ifelse.sv - Conditional constraints using ->, if-else, and equivalence.

4. Testbench Components & Architecture

Modular blocks of a standard verification environment.

• sv_testbench_architecture/ - Top-level testbench wiring.
• interface/ & driver_interface/ - Defining virtual interfaces and connecting them to drivers.
• monitor_scoreboard/ - Passive components for observing and verifying DUT behavior.
• generator_driver_monitor_scoreboard/ - Integration of standard verification IP components.
• generator_driver_deepcopy/ - Handling deep copies between generator and driver components.

5. Advanced Verification Scenarios

• error_injection_in_generator/ - Techniques for introducing deliberate errors at the generation stage.
• error_injection_in_transaction/ - Corrupting transaction items to verify DUT error handling.