Team Report RISC-V-T15

Group Members:

• Alix Le Coguic
• Selime Ozyurt
• Benjamin Clemente (Repo Master, Team Report Writer)
• Augustin Briens (Team Report Writer)

Personal Statements

• Personal Statement Augustin Briens
• Personal Statement Benjamin Clemente
• Personal Statement Selime Ozyurt
• Personal Statement Alix Le Coguic

Table of Contemts

• Single Cycle
  • Program-Counter (Selime Nur Ozyurt)
  • Register-File
  • F1 Program (Benjamin Clemente, Alix Le Coguic)
  • Instruction Memory (Selime Ozyurt, Augustin Briens)
  • ALU (Augustin Briens)
  • Data Memory (Alix Le Coguic)
• Pipeline
  • 4 Stages of Pipeline (Alix Le Coguic, Selime Ozyurt)
  • Hazard Unit (Benjamin Clemente)
• Caches
  • Data Cache (Augustin Briens, Benjamin Clemente)
  • Top Memory (Augustin Briens)
  • Instruction Memory Cache (Augustin Briens)
• Top Level
  • Top file CPU (Benjamin Clemente, Augustin Briens)
  • Testbenches (Benjamin Clemente, Augustin Briens)
  • CPU Tests (Benjamin Clemente, Augustin Briens)
• Branch Prediction (Benjamin Clemente)

Important Notes

Critical Points:

• Ensure to draw attention to significant points such as tests and debugging information.

Quick Start

Prerequisite:

First, make your way to the testbench folder, using cd tb.
The main script is doit.sh which runs all the tests within the tests folder.

For simplicity, the unit tests are by default within the unit_tests folder, if you want to use these tests, simply move them to the test folder.

Below is a table listing the different shell scripts, and their use:

Command	Behaviour
./doit.sh	Runs all the test benches within tb/tests
./f1.sh	Runs the f1-lights program
./gaussian.sh	Plots the gaussian graph
./triangle.sh	Plots the triangle graph
./noisy.sh	Plots the noisy graph

Overview

Contribution Table

		Selime	Alix	Ben	Augustin
Lab 4	Program Counter	X
	ALU		X
	Register File	X	X
	Instruction Memory				X
	Control Unit			X	X
	Sign Extend				X
	Testbench			X
	Topfile/implementation			X
Single Cycle	Data Memory		X
	Program Counter (refactor)	X
	ALU (refactor)				X
	Register File (refactor)	X	X
	Instruction Memory (refactor)	X
	Control Unit (refactor)			X
	Sign Extend (refactor)				X
	Topfile/implementation			X	x
Pipeline	Fetch-Decode pipeline	X
	Decode-Execute pipeline	X
	Execture-Memory pipeline		X
	Memory-WriteBack pipeline		X
	Hazard unit			X
Cache	Memory (refactor)				X
	Direct mapped cache				X
	Two-way set associative cache				X
Branch Prediction				X
Other	F1			X
	Vbuddy			X

Proof Of Working CPU on Vbuddy:

F1

noise.mov

Gaussian

WhatsApp.Video.2024-12-13.at.12.46.24.1.mp4

Noisy

WhatsApp.Video.2024-12-13.at.12.46.24.mp4

Triangle

WhatsApp.Video.2024-12-13.at.12.46.23.mp4

FPGA

FPGA_compressed.mp4

Components

• Single Cycle

  • F1 Program
    Initial implementation of a single-cycle CPU program.
  • Pipeline
    Design and implementation of pipeline functionality in the CPU.
  • Instruction Memory
    Development of instruction memory for single-cycle execution.
  • ALU
    Arithmetic Logic Unit creation for computation in the CPU.
  • Data Memory
    Implementation of data memory handling for the CPU.

• Pipeline

  • 4 Stages of Pipeline
    Design and breakdown of the CPU pipeline into 4 functional stages.
  • Hazard Unit
    Hazard detection and resolution unit implementation for pipeline safety.

• Caches

  • Data Cache
    Creation of a cache for optimized data memory access.
  • Top Memory
    Integration of memory hierarchy at the top level of the CPU.
  • Instruction Memory Cache
    Development of an instruction cache for faster access to instruction memory.

• Top Level

  • Top file CPU
    Integration of CPU components at the top level and harmonisation of Inputs and Outputs

  • Testbenches
    Creation of testbenches for unit-testing CPU functionality:

  • CPU Tests Creation of Assembly codes and test benches for integration testing of the CPU

• Branch Prediction Implementation of a two-bit predictor to improve the efficiency of conditional branch execution by reducing pipeline stalls and misprediction penalties.

FPGA

For all the information about the FPGA work, refer to: FPGA.md