see plans/use_case_spiking_transformers.md — goal, reference architecture (encode → spiking sequence session → head → spikeforge-serve control → clients → throughput/memory /metrics; NIR export gate), rate/delta coding, sequence_attn (simulation-only) + sequence_mlp control, acceptance (quality within 5% of dense baseline or honest statement; throughput/memory reported; typed UnsupportedStageError), MVP phases P0–P4, dependencies PT-W1/W2/W3/W6.
Spec: plans/use_case_spiking_transformers.md
Refs #12 (umbrella tracking the ten chip-less production use cases).
see
plans/use_case_spiking_transformers.md— goal, reference architecture (encode → spiking sequence session → head →spikeforge-servecontrol → clients → throughput/memory/metrics; NIR export gate), rate/delta coding,sequence_attn(simulation-only) +sequence_mlpcontrol, acceptance (quality within 5% of dense baseline or honest statement; throughput/memory reported; typedUnsupportedStageError), MVP phases P0–P4, dependencies PT-W1/W2/W3/W6.Spec:
plans/use_case_spiking_transformers.mdRefs #12 (umbrella tracking the ten chip-less production use cases).