GitHub - Capynetics/RTL-PROJECT-EXAMPLE: https://capynetics.github.io/general/2019/08/15/RTL-project-example-with-FPGA.html

Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
db		db
incremental_db		incremental_db
output_files		output_files
simulation/modelsim		simulation/modelsim
AULA15.qpf		AULA15.qpf
AULA15.qsf		AULA15.qsf
AULA15.qws		AULA15.qws
AULA15_nativelink_simulation.rpt		AULA15_nativelink_simulation.rpt
BancoRegistradores.vhd		BancoRegistradores.vhd
BancoRegistradores.vhd.bak		BancoRegistradores.vhd.bak
Comparador.vhd		Comparador.vhd
Comparador.vhd.bak		Comparador.vhd.bak
Deslocador.vhd		Deslocador.vhd
Deslocador.vhd.bak		Deslocador.vhd.bak
FSM.vhd		FSM.vhd
FSM.vhd.bak		FSM.vhd.bak
Final.vhd		Final.vhd
Final.vhd.bak		Final.vhd.bak
RegistradorCargaParalela.vhd		RegistradorCargaParalela.vhd
RegistradorCargaParalela.vhd.bak		RegistradorCargaParalela.vhd.bak
Somador.vhd		Somador.vhd
Somador.vhd.bak		Somador.vhd.bak
datapath.vhd		datapath.vhd
datapath.vhd.bak		datapath.vhd.bak
output_file_AULA15.map		output_file_AULA15.map
output_file_Novo_AULA15.jic		output_file_Novo_AULA15.jic
output_file_Novo_AULA15.map		output_file_Novo_AULA15.map
output_files113.jic		output_files113.jic
output_files113.map		output_files113.map
tb_FSM.vhd		tb_FSM.vhd
tb_FSM.vhd.bak		tb_FSM.vhd.bak
tb_Final.vhd		tb_Final.vhd
tb_Final.vhd.bak		tb_Final.vhd.bak