This project implements a Least Mean Squares (LMS) adaptive filter in Verilog, designed with full parameterization for maximum flexibility. The user can configure:
Number of input samples
Tap length (filter order)
Desired signal
Step size (μ)
The design supports easy experimentation with adaptive filtering concepts and can be used for noise cancellation, channel equalization, and real-time signal processing .
Features :
Parameterized inputs for reusability
Supports dynamic selection of tap length and step size
IEEE 754 based Modules foe internal operations: MUL,ADD,SUB etc
Testbench included for verification