ci: build MCU SoC timing IR on Linux + de-flake opensta-to-ir locate test#65
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) The cosim/sim CLI was renamed `--max-cycles` → `--max-clock-edges` on main but the MCU SoC workflow steps still passed the old flag. PR #63 fixed this in isolation; folding the same change here so #65 can be evaluated against CI on its own. Three call sites updated: - First cosim (500K edges, UART boot smoke test) - Second cosim (10K edges, stimulus/timing VCD capture — same step this PR rewires to consume --timing-ir) - Replay sim (10K edges, non-timed VCD for CVC comparison) Also adds `set -o pipefail` to the two cosim steps that lacked it, so future failures inside the `tee` pipeline surface immediately rather than greening through. Closes #62. Supersedes #63 — close PR #63 after this merges. Co-developed-by: Claude Code v2.1.143 (claude-opus-4-7)
robtaylor
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mcu-soc-cvc previously ran `make -f makefile.cvc64` which upstream removed in commit 1c5e043e (2026-03-13). The cvc-reference job was fixed at the same time; mcu-soc-cvc kept the stale invocation because the job had been transitively skipped (mcu-soc-metal failed first, so this job never ran). Now that mcu-soc-metal is green it ran for the first time and hit the deleted makefile. Mirror the cvc-reference job's working build: top-level src/Makefile with the same CFLAGS workaround, output at ../build64/cvc64. Surfaced by PR #65 CI run 26066588654. Co-developed-by: Claude Code v2.1.143 (claude-opus-4-7)
The locate_and_check tests' write_stub_script helper occasionally hit
ETXTBSY ("Text file busy") on Linux when invoking the freshly-written
stub binary — close(2) does not synchronously decrement the inode's
writer_count, so an immediate execve can race. The test then sees
LocateError::VersionProbeFailed { kind: ExecutableFileBusy } instead
of the expected exit-code-driven variant.
Add sync_all + a brief no-op execve probe loop after drop so the
helper only returns once the file is safely executable. Bounded at
2s with a panic-on-timeout to keep CI runtime predictable.
Surfaced via PR #63 CI run 25938446354.
Co-developed-by: Claude Code v2.1.143 (claude-opus-4-7)
OpenSTA's read_verilog is structural-only: RTL operators (~, &, |), bit-selects in assigns, and ranged concatenations cause a syntax error. The LibreLane + wafer.space integration flow wraps the post-P&R structural body in a thin RTL module (e.g. openframe_project_wrapper) that patches the chip-frame pad ring using exactly those operators. Every user pushing a tapeout through this pipeline — chipflow's mcu_soc, hazard3, future wafer.space designs — hits the same wrapper-parse failure. Add a Verilog input filter that runs before the OpenSTA subprocess invocation: for each --verilog file, extract `module <--top> … endmodule` if present; pass the file through unchanged otherwise. Files without a matching module declaration (sub-module-only files in hierarchical designs) still link cleanly. Implementation in src/verilog_filter.rs with 7 unit tests covering the multi-module, single-module, absent-module, prefix-collision, indented-keyword, no-port-list, and comment-with-endmodule cases. Integration in opensta::run via a per-file pre-pass that writes filtered outputs into the existing OpenSTA tempdir. A second class of pitfall — substituting a pre-P&R synthesis netlist to dodge the wrapper-parse error — is documented in ADR 0009 and retracted from the prior ws3-cosim-sdf-followup recipe. That path silently drops SDF entries for cells P&R inserts (CTS buffers, antenna diodes, fillers) and produces materially incomplete IR. No CLI changes — the behaviour is transparent. Co-developed-by: Claude Code v2.1.143 (claude-opus-4-7)
The cosim/sim CLI was renamed --max-cycles → --max-clock-edges on main but the MCU SoC workflow steps still passed the old flag. PR #63 fixed this in isolation; folding the same change here so #65 can be evaluated against CI on its own. Three call sites updated (first cosim 500K, second cosim 10K, replay sim 10K). Also adds `set -o pipefail` to the two cosim steps that lacked it, so future failures inside the `tee` pipeline surface immediately rather than greening through. Closes #62. Supersedes #63 — close PR #63 after this merges. Co-developed-by: Claude Code v2.1.143 (claude-opus-4-7)
The MCU SoC Metal Simulation job's second cosim invocation was passing flags cosim never accepted (--sdf, --sdf-corner) — historically masked by clap rejecting `--max-cycles` first. Cosim only accepts pre-built timing IR (--timing-ir <.jtir>); raw SDF support is the documented post-phase-0-roadmap follow-up. Add a new Linux job (prepare-mcu-soc-jtir) that builds OpenSTA, installs the pinned sky130A PDK via volare, builds opensta-to-ir, and runs it against tests/mcu_soc/data/6_final.sdf to produce a 6_final.jtir artifact. The Metal job `needs:` this job, downloads the artifact, and feeds it to cosim via --timing-ir. The 6_final.v file has a chipflow integration wrapper module (openframe_project_wrapper) that uses RTL operators OpenSTA's parser rejects. opensta-to-ir's Verilog input filter handles this transparently — see the feat(opensta-to-ir) commit earlier in this PR and ADR 0009 for details. Also drop the redundant "Strip SDF timing checks" step (it overwrote a tracked file with identical content; raw SDF is no longer fed to cosim) and document the Python tooling convention in CLAUDE.md (uv dev dependencies for Python tools; volare for PDK install with a forward note on the upstream ciel rename). Co-developed-by: Claude Code v2.1.143 (claude-opus-4-7)
mcu-soc-cvc previously ran `make -f makefile.cvc64` which upstream removed in commit 1c5e043e (2026-03-13). The cvc-reference job was fixed at the same time; mcu-soc-cvc kept the stale invocation because the job had been transitively skipped (mcu-soc-metal failed first, so this job never ran). Now that mcu-soc-metal is green it ran for the first time and hit the deleted makefile. Mirror the cvc-reference job's working build: top-level src/Makefile with the same CFLAGS workaround, output at ../build64/cvc64. Co-developed-by: Claude Code v2.1.143 (claude-opus-4-7)
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robtaylor
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May 19, 2026
The cosim/sim CLI was renamed --max-cycles → --max-clock-edges on main but the MCU SoC workflow steps still passed the old flag. PR #63 fixed this in isolation; folding the same change here so #65 can be evaluated against CI on its own. Three call sites updated (first cosim 500K, second cosim 10K, replay sim 10K). Also adds `set -o pipefail` to the two cosim steps that lacked it, so future failures inside the `tee` pipeline surface immediately rather than greening through. Closes #62. Supersedes #63 — close PR #63 after this merges. Co-developed-by: Claude Code v2.1.143 (claude-opus-4-7)
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Summary
Unblocks PR #63's CI by fixing two unrelated failures it surfaced:
MCU SoC Metal Simulation — the second cosim invocation was passing
--sdf/--sdf-corner, which cosim never accepted. Historically masked because clap rejected the now-renamed--max-cyclesfirst. Cosim's documented contract is "pre-convert withopensta-to-irand pass--timing-ir <.jtir>"; raw SDF support is thedocs/plans/post-phase-0-roadmap.mdfollow-up.New
prepare-mcu-soc-jtirLinux job builds OpenSTA, installs the pinned sky130A PDK via volare, runsopensta-to-iragainsttests/mcu_soc/data/6_final.sdf, and uploads the resulting6_final.jtiras an artifact. The Metal jobneeds:it, downloads the artifact, and passes--timing-irto the second cosim. Removes the redundant "Strip SDF timing checks" step (was overwriting the tracked stripped SDF with identical content).opensta-to-ir locate test flake —
locate_reports_failing_version_probeoccasionally gotVersionProbeFailed { kind: ExecutableFileBusy }instead of the expectedVersionProbeNonZero. Linux'sclose(2)does not synchronously decrement the inode writer_count, so an immediateexecveof the freshly-written stub races. Addedsync_allplus a bounded no-op execve probe loop in the test helper so the stub is provably ready before the test runs.Also documents the Python tooling convention (uv dev dependencies; volare/ciel for PDK install) in
CLAUDE.md.Test plan
prepare-mcu-soc-jtirjob completes: OpenSTA + opensta-to-ir build, volare installs sky130A, jtir artifact uploadedMCU SoC Metal Simulationjob downloads the jtir and completes "Capture stimulus + timing VCD via cosim" without CLI parse errorsopensta-to-ir Testsjob:locate_reports_failing_version_probepasses (validating the de-flake)mcu-soc-cvc/mcu-soc-comparisonjobs see expected stimulus.vcd / timing VCD artifactsNotes for PR #63 rebase
PR #63's rename
--max-cycles → --max-clock-edgesstill applies cleanly: the first cosim (line 626) is untouched here. The second cosim (was line 653) is rewritten to use--timing-ir; PR #63's rename of that line will need to be re-applied to the new--max-cycles 10000 \line.set -o pipefailadditions are not in this PR's scope.Followups still open (tracked in
docs/plans/post-phase-0-roadmap.md):--sdfsubprocess wrapper to cosim so the Linux jtir prep job can be inlinedvolaredep to upstream-renamedcielpackage