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DepTyCheck / verilog-model Public

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New array rerpresentation (second draft)#236

Draft

GlebChili wants to merge 7 commits into

masterDepTyCheck/verilog-model:masterfrom

new-array-rerpresentation-2DepTyCheck/verilog-model:new-array-rerpresentation-2Copy head branch name to clipboard

Conversation Commits7 (7)Checks Files changed

Draft

New array rerpresentation (second draft)#236
GlebChili wants to merge 7 commits into
masterfrom
new-array-rerpresentation-2

Commits

Commits on May 28, 2026

Introduce array shape
GlebChili
committed
Add support for new array literals
GlebChili
committed
Update Common Design bits for array shape
GlebChili
committed
Update SystemVerilog Pretty to array shape
GlebChili
committed
Fix missing constructors error for VarOrPacked datatype
GlebChili
committed
Port simplified array representation
GlebChili
committed
Implement pretty printing on multidimensional array from the "flat" literals.
GlebChili
committed

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