Custom 5-Bit Gate-Level CPU Architecture

A custom 5-bit computer architecture and processor implemented completely manually from scratch at the gate level using the Digital logic circuit simulator. This project was built to gain a fundamental understanding of hardware execution, utilizing pure logic circuits rather than relying on hardware description languages like Verilog.

---

📸 Architecture Overview

Figure 1: Full Top-Level 5-Bit CPU Circuit Diagram

System Specifications

• Data Word Size: 5-bit datapath.
• Instruction Word Size: 18-bit fixed-length instructions.
• General Purpose Registers: 3 registers ($R_0$, $R_1$, $R_2$).
• Main Memory: 10 memory locations forming a 10x18-bit SRAM.
• ALU Operations: NOT, ADD, ROL (Rotate Left).
• Supported Instructions: Register operations, Immediate operations, JMP, and JLE.

---

📽️ Demo Execution

Watch the full, step-by-step video demonstration of the below test assembly program execution here.

---

📐 Instruction Set Architecture (ISA) Summary

The CPU uses an 18-bit instruction format categorized into three primary modes:

Mode	Type Bits	Description
Register	00	Register-to-register arithmetic and logical operations.
Immediate	01	Register operations utilizing a 5-bit constant literal.
Branching	10	Program flow control via conditional and unconditional jumps.

For full bit-level instruction field layouts, refer to docs/ISA_Spec.md.

---

💻 Verified Assembly Program

Below is the sample test program verified on the CPU hardware:

0000: JLE START         ; Machine Code: 100100010000000000
0001: START: ADD R2, 5  ; Machine Code: 010110001010000000
0010: NOT R2            ; Machine Code: 000010000000000000
0011: ROL R2, 2         ; Machine Code: 011010000100000000
0100: JMP_TO: ADD R1, 2 ; Machine Code: 010101000100000000
0101: JMP JMP_TO        ; Machine Code: 100001000000000000

---

🛠️ How to Run the Simulation

1. Download and install Digital Simulator (Compatible across Windows, Linux, and macOS).
2. Clone this repository to your local machine.
3. Open circuits/5bit_cpu.dig inside the Digital application.
4. Load the sample machine code into the SRAM module.
5. Trigger the clock signal to step through execution and observe register states.