================================================================================
Copyright © 2019 by Cryptographic Engineering Research Group (CERG),
ECE Department, George Mason University
Fairfax, VA, U.S.A.
Author: Farnoud Farahmand
================================================================================
To create a new Vivado project for Software/Hardware co-design platform perform
the following steps:
Note: this instruction has been tested using Vivado version 2018.2 and may not
work for other versions.

1. Go to the script folder and run "bash ./run_vivado.sh BOARD_NAME MODE"
command.
Available options for the BOARD_NAME argument are: ZCU104 (default) and ZCU102.
Available options for the MODE argument are: BATCH (default) and GUI.
Here is an example of running the script for the ZCU102 board in GUI mode:
$bash ./run_vivado.sh ZCU102 GUI
This script starts Vivado, creates a project, and generates the bitstream.
If you would like to see the whole process in the graphical interface, use the
GUI mode.

2. When the bitstream is generated successfully, the Xilinx SDK application
should open automatically. In the SDK application perform the following steps:
    1- Create a new application project by choosing File -> New -> Application
    Project.
    In "Project name" enter your desired name and select "Next >". Select Empty
    Application in "Available Templates:" and then click on "Finish".

    2- Right click on your project name in the "Project Explorer" tab and select
    "Generate Linker Script". Increase "Heap Size:" and "Stack Size:" to 10 MB.

    3- Copy all C codes available in c_baremetal directory into the "src"
    directory of your project.

    4- Turn on compiler optimization: right click on your project name in the
    "Project Explorer" tab and select "C/C++ Build Settings". In the opened
    window select "Optimization" and change the Optimization Level to
    "Optimize most (-O3)"

    5- Program FPGA board: connect the FPGA board to your machine and in the SDK
    click on the Program FPGA icon and select Program.

    6- Build your project and then right click on your project name and select
    Run As -> 1 Launch on Hardware (System Debugger).
    Note: To see the output of print functions on Windows machine, you can use
    SDK Terminal. However, on Linux machines you should use a 3rd party
    application, like GtkTerm, to see a serial port output.

If you would like to generate a bitstream for an accelerator core other than
NTRUEncrypt RTL polymult, you can open the Vivado project created in
vivado_project/platform_project and replace the polymult IP core with another
accelerator and generate a new bitstream.

The program is expected to print out the execution time of Key Generation,
Encapsulation, and Decapsulation (in cycles of AXI Timer set by default to 200
MHz) for software only implementation and software/hardware implementation, as
well as the achieved speed-up.

You can also set the "POLY_MUL_EXE" parameter to 1 in the DMA_Transfer_def.h to
print out the execution time of hardware accelerator only.

This platform has been used for generating results reported in the following
publications:

- F. Farahmand, V. Dang, M. Andrzejczak, K. Gaj, “Implementing and Benchmarking
  Seven Round 2 Lattice-Based Key Encapsulation Mechanisms Using a
  Software/Hardware Codesign Approach”. In NIST Second PQC Standardization
  Conference, Santa Barbara, USA, Aug 2019.
  https://csrc.nist.gov/CSRC/media/Events/Second-PQC-Standardization-Conference/
  documents/accepted-papers/gaj-implementing-benchmarking.pdf

- F. Farahmand, V. Dang, D. Nguyen, and K. Gaj, “Evaluating the Potential for
  Hardware Acceleration of Four NTRU-Based Key Encapsulation Mechanisms Using
  Software/Hardware Codesign”. In: 10th International Conference on Post-Quantum
  Cryptography, PQCrypto 2019. LNCS. Chongqing, China: Springer, May 2019.
  https://link.springer.com/chapter/10.1007/978-3-030-25510-7_2

- F. Farahmand, D. Nguyen, V. Dang, A. Ferozpuri, and K. Gaj, “Software/Hardware
  Codesign of the Post Quantum Cryptography Algorithm NTRUEncrypt Using
  High-Level Synthesis and Register-Transfer Level Design Methodologies”, In
  29th International Conference on Field Programmable Logic and Applications
  (FPL), Barcelona, Spain, Sep. 9-13, 2019.
  https://par.nsf.gov/biblio/10108524