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Roadmap
Harnesser edited this page Jun 6, 2011
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The Basics (25-AUG-07)
- Read in a fixed verilog file list
- Build the Verilog Parser: starting with a basic subset of verilog language
- Build Circuit Data Structure`
- Draw module instanciations
- Draw ratsnest connections
- Draw module ports
- Allow traversal of hierarchy
- Build basic GUI
- Unittest foundation
Circuit Drawing Enhancements
- Draw module instantiations placed in Left to Right order depending on signal flow
- Initial implementation of the Sugiyama et al layout algorithm
- Maybe layer reordering is enough for now
- Tidy up graphics a bit
Verilog Language Support Enhancements
- Consider SQLite backend
- Parse ranges
- Draw buses
- Draw bus spurs
- Parse always blocks
- Draw always blocks as blocks
- Concatenation support
- Ordered port connections - Verilog 1995
GUI Enhancements
- Net highlighting
- Bookmarking of views
- Zooming and Panning around circuit: keyboard and mousewheel support
- Cache previously viewed modules?
- Artwork: icon, splashscreen
- Search: Nets. instances
- Zoom to selected
- Mouse rollover gives a tooltip with module information
Parameter Support
- Parse module parameters
- Parameter propagation thru hierarchy
- Parameter expression calculations
Verilog Arguments and Preprocessor
- Parse Verilog Arguments
- Verilog Preprocessor: macro substitution, `ifdefs etc
- Configurations
Array Support
- Array of Instances
- generate blocks
- Can start eating own dogfood?
Debug Functionality
- Net drivers tracing
- What is done with malformed RTL?
- Display source code on demand
- 'Alt-G' Mode - Grey out everything except highlighted nets
Lower-level Circuit Drawing
- Parse and ignore specparam sections
- Detect and draw simple logic gates
- Draw instantiated logic primitives/standard cells
- Detect and draw muxes
- Draw datapath blocks: adders, comparators etc
Final Tidy-Up
- Test with real-life RTL: From OpenCores and from ADI (if legal)
- Test at work - eat own dogfood
- Debian/Ubuntu package
- Windows Installer
- Desktop integration
- About
- Help
- VHDL Support
- Printing
- Connection to SimVision etc
- Option to not route Clock or Reset nets, but instead indicate that they are connected
- HTML hitmap export option
- Look at memory footprint