FPGA UART Library

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Current Environment

• Development tool: Quartus II 13.0
• Target FPGA: EP4CE6E22N8
• Pin reference image: see pin.jpg below

⚠️ Important Warning

Do not directly reuse the pin definitions in this project.

Before using this project, you must verify all of the following against your real hardware:

• the FPGA device is really EP4CE6E22N8
• the package and pin numbering are the same
• the pin assignments in uart_top.qsf are correct
• the clock frequency is correct
• the UART baud rate is correct
• the reset polarity is correct
• the IO voltage standard is correct

If these items are not checked carefully, the design may compile successfully but still fail on hardware or cause incorrect wiring.

Overview

This project is a small UART communication library and demo design for FPGA.

It includes:

• UART receiver
• UART transmitter
• Simple application-layer frame parser
• Quartus project example
• Minimal terminal-based host tool

The protocol is designed for simple FPGA command exchange and debug.

License

This project is intended to be released under the MIT License.

File Structure

• src/uart_rx.v

  • UART receive module

• src/uart_tx.v

  • UART transmit module

• src/uart_app.v

  • Simple frame parser

• src/uart_top.v

  • Example top-level design

• quartus/

  • Quartus project files

• data_rx.py

  • Minimal terminal host tool

Protocol Format

Outer frame format:

AA ID LEN DATA... BB 02

Fields:

• AA

  • Frame header

• ID

  • Device ID

• LEN

  • Data length in bytes

• DATA

  • Payload data

• BB 02

  • Frame tail

Example Payload

This open-source version only shows generic examples.

Example 1: one-byte command

01

Example 2: three-byte user data

11 22 33

Example 3: ASCII-like debug content

41 42 43

All payloads are wrapped by the outer frame:

AA ID LEN DATA... BB 02

Modules

uart_rx.v

Receives UART serial data and outputs:

• uart_rx_done
• uart_rx_data

uart_tx.v

Transmits one byte through UART when uart_tx_en is asserted.

uart_app.v

Parses the frame:

AA ID LEN DATA... BB 02

Outputs status information such as:

• frame_done
• id_match
• id_rx
• len_rx
• data_last
• proto_ok

Host Tool

data_rx.py is a very small terminal-based test tool.

Features:

• Select serial port
• Send payload in hex
• Optional raw byte send
• Print received frame
• Parse simple response frame

Run:

python data_rx.py

Typical Usage

1. Open the serial port
2. Enter payload bytes in hex
3. The tool packs them into:

AA ID LEN DATA... BB 02

4. FPGA returns a response frame
5. The tool prints both raw hex and parsed text

Quartus Pin Definition

The current demo project pin assignments are stored in:

• quartus/uart_top.qsf

Current example assignments:

• sys_clk -> PIN_25
• sys_rst_n -> PIN_88
• uart_rxd -> PIN_23
• uart_txd -> PIN_10
• led_rx -> PIN_1
• led_tx -> PIN_2
• led_work -> PIN_3

These are only example assignments for the original board used in this project.

How To Modify Pin Definitions

Open:

• quartus/uart_top.qsf

Find lines like:

set_location_assignment PIN_25 -to sys_clk

Then replace the pin name according to your real board schematic.

Typical items you may need to modify:

• FPGA device model
• clock pin
• reset pin
• UART RX pin
• UART TX pin
• LED pins

Important Warning

It is strongly recommended to confirm the following items carefully before reusing this project:

1. FPGA device model
2. package and pinout
3. clock frequency
4. UART baud rate
5. reset polarity
6. IO voltage standard
7. board-level pin definition

Do not directly reuse the provided qsf pin assignments unless you are sure your board is identical.

If these settings do not match your hardware, the design may compile successfully but still fail on board.

Notes

• The FPGA UART parameters must match the host:

  • baud rate
  • device ID

• The Quartus project file must match your actual hardware:

  • FPGA device
  • pin definition
  • IO standard
  • clock source

• This library is intentionally small and easy to modify.

• For old Quartus versions, keep HDL comments ASCII-only if encoding causes issues.