Name		Name	Last commit message	Last commit date
AXI_UART.png		AXI_UART.png
LICENSE		LICENSE
README.md		README.md
amba_if.sv		amba_if.sv
axi2uart.sv		axi2uart.sv
axi4LiteReg.sv		axi4LiteReg.sv
bufferRx.sv		bufferRx.sv
bufferTx.sv		bufferTx.sv
syn_fifo.sv		syn_fifo.sv
testbench_buffer.sv		testbench_buffer.sv
testbench_fifo.sv		testbench_fifo.sv
testbench_uart.sv		testbench_uart.sv
uart_rx.sv		uart_rx.sv
uart_tx.sv		uart_tx.sv

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axi4lite2uart

This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.

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This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.

bridge microcontroller-bus-architecture

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