hi ,
I want to use one gated clock for the registers that can only be written by software and use always-on clock for the reigters that may be written by hardware(for example some read-only status). But in the generated rtl , all the registers use the same clk . Is there any option to achieve my aim ? Thanks .
hi ,
I want to use one gated clock for the registers that can only be written by software and use always-on clock for the reigters that may be written by hardware(for example some read-only status). But in the generated rtl , all the registers use the same clk . Is there any option to achieve my aim ? Thanks .