[codex] Add pipeline-aligned Vector architecture specification

[sheyuheng]

Summary

• add the Janus Vector Core architecture specification under Janus/Vector
• align frontend, rename, dispatch, issue, RF read, execute, and TileLSU descriptions with the pipeline diagram
• document the scalar ALU/BRU, ALU/MUL, and LD/ST address paths
• include all four images referenced by the specification

Architecture impact

• defines the SMT4 frontend stages from F0 through D2
• distinguishes four Vector scheduling domains from the three-compute-uop issue limit
• specifies shared Hetero-pipe execution resources and the VSTD path
• uses an 88-entry, 2048-bit Vector RF as the current pipeline baseline
• unifies Vector-side TileLSU buffering terminology around SCB

Validation

• verified chapters 1-3 remain identical to the reviewed Vector.md content
• verified every Markdown image reference resolves to a file included in this PR
• verified the commit contains only Vector_AS.md and its four referenced images
• ran git diff --cached --check before commit

[gemini-code-assist]

Code Review

This pull request introduces the Janus Vector Core Architecture Specification, which outlines the design, execution model, and interfaces of the vector execution engine. The review feedback identifies several key areas for improvement, including correcting a binary/hexadecimal prefix typo and expanding the enable mask to 64-bit to match the 64-lane architecture, fixing a grammatical typo in the Chinese text, correcting a mathematical inconsistency in the thread count calculation example, and standardizing the relative alias notation for consistency.

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[gemini-code-assist]

To maintain consistency with the relative alias notation ti#N / to#N described in Line 174 and used in Line 220 (to#0), it is recommended to change to0 to to#0.

Suggested change

	v.sh vt#1, [to0, lc0 << 1] // 存储 FP16 到第 0 个输出 Tile
	v.sh vt#1, [to#0, lc0 << 1] // 存储 FP16 到第 0 个输出 Tile

[sheyuheng]

The original one was correct.