Fix clipping of FST waveforms from Verilator simulation

[eszpotanski]

When using clipfst on FST waveform received from Verilator simulation, program fails with message Failed to write value change!.

This PR is a fix proposition for this error.

Example waveform: trace.zip

Example command:

$ clipfst -e 70215500 trace.fst clipped_trace.fst
Failed to write value change!

[MaxXSoft]

Thanks for your contribution!

I debugged clipfst with the example waveform, it shows that when the clipfst encounters the error, it's trying to write a 2-bit value into an 8-bit handle.

By dumping the hierarchy block:

we can see the handle is declared as 8 bits:

But when traversing the VCD data:

fstapi reports that the handle corresponds to a 2-bit value:

This made you remove the length check in fstapi.c, I guess.

But I think this check is necessary (although the code in fstapi.c is not written by me), and the mismatch of hierarchy and value data may be caused by the code that generates this waveform, or from the original Verilog/SystemVerilog code.

Could you please provide more details about this waveform? It seems that the value PERIOD is a "real parameter", but I have no idea why it's data is just 2-bit long.

[eszpotanski]

This waveform is created from Verilator simulation, which is built using Chipyard. It should simulate MegaBoom running bare-metal program (in this case the beginning of CoreMark).

So, basically MegaBoom definition is converted from Chisel to SystemVerilog, which is compiled into the simulation with Verilator.

From what I see, there are two signals named PERIOD:

• TOP.TestDriver.testHarness.source.PERIOD
• TOP.TestDriver.testHarness.source_1.PERIOD

This scopes suggest they are added by the Chipyard, but the only thing I found is this PERIOD, but I'm not really sure if they are related:
https://github.com/ucb-bar/chipyard/blob/4667f27c70a0b1e47b045518c032b234eccd7681/generators/chipyard/src/main/scala/harness/HarnessClocks.scala#L55