Current Mirror Topologies — Design, Analysis & Comparative Study

90 nm CMOS (gpdk090) · Cadence Virtuoso / Spectre · Analog IC Design

A ground-up design and simulation study of six current mirror topologies, built to isolate the effect of architecture alone on analog performance. Every circuit uses identical device sizing (W = 1 µm, L = 200 nm), the same 1.2 V supply, and the same 10 µA reference current — so every difference in the results comes from the topology, not the sizing.

📄 Full write-up with derivations and step-by-step calculations: docs/Current_Mirror_Project_Report.docx

---

Why current mirrors

Current mirrors are the backbone of analog IC design — used for biasing, active loads, current sources, and current scaling, all without the area and matching penalties of resistor-based biasing. The two things that make one mirror better than another are:

• Output resistance (Rout) — how well the mirror holds its current as output voltage changes
• Compliance voltage (Vcom) — the minimum output headroom the mirror needs to stay in saturation
• Current matching accuracy — how close Icopy tracks Iref

Every topology in this study exists to trade off between these three things.

---

Topologies studied

#	Topology	What it fixes
1	Simple Current Mirror	Baseline 2-transistor mirror
2	Cascode Current Mirror	Shields the reference drain → boosts Rout, kills most of the CLM error
3	High-Swing (Low-Voltage) Cascode	Recovers headroom lost to cascoding (trades accuracy for swing)
4	High-Swing Precision Cascode	Fixes the systematic deficit introduced by (3)
5	Precision High-Swing Regulated Cascode	Op-amp feedback actively cancels residual VDS mismatch
6	Wilson Current Mirror	Negative-feedback alternative to cascoding

---

Results — Master Comparison

Parameter	Simple	Cascode	High-Swing	HS-Precision	Reg. Cascode	Wilson
Vcom (mV)	60	305	125	140	175	450
Icopy (µA)	8.778	9.833	7.253	9.957	9.766	10.627
Current Error	12.22%	1.67%	27.47%	0.43% ⭐	2.34%	6.27%
Rout	45.4 kΩ	1.13 MΩ	761.5 kΩ	560.9 kΩ	6.52 MΩ ⭐	554 kΩ
Temp. Coeff.	469 ppm/°C	64.3 ppm/°C	820.8 ppm/°C	47.4 ppm/°C	0.62 ppm/°C ⭐	369.1 ppm/°C
Static Power	12.0 µW	12.0 µW	24.0 µW	24.0 µW	50 µW	12.0 µW
Ref. Branches	1	1	2	2	2 + op-amp	1

⭐ = best result for that metric across all six topologies

Takeaways:

• Best accuracy → High-Swing Precision Cascode — 0.43% error at only 140 mV compliance
• Best output impedance → Regulated Cascode — 6.52 MΩ, ~140× the simple mirror, via op-amp feedback
• Lowest voltage headroom → High-Swing variants — Vcom ≤ 140 mV, ideal for sub-1 V rails
• Best general-purpose balance → Conventional Cascode — 1.67% error, 1.13 MΩ Rout, 12 µW, single reference branch

---

1. Simple Current Mirror

Two-transistor baseline. Icopy inherits a channel-length-modulation (CLM) error directly from the VDS mismatch between the diode-connected reference device and the output device.

Error = 12.22% · Rout = 45.4 kΩ · Vcom = 60 mV · TC = 469 ppm/°C

---

2. Cascode Current Mirror

Adds a stacked cascode pair to shield the reference drain from output voltage swings. Zout ≈ gm·rds².

Error = 1.67% · Rout = 1.13 MΩ · Vcom = 305 mV · TC = 64.3 ppm/°C

---

3. High-Swing (Low-Voltage) Cascode Current Mirror

Recovers headroom via a wide-swing bias-generator branch, at the cost of a systematic Iref − VT/rds2 deficit.

Error = 27.47% · Rout = 761.5 kΩ · Vcom = 125 mV · TC = 820.8 ppm/°C

---

4. High-Swing Precision Cascode Current Mirror

Inserts a VT-drop element to equalize VDS between reference and output lower devices, eliminating the deficit from (3) while keeping the same low compliance voltage.

Error = 0.43% (best in study) · Rout = 560.9 kΩ · Vcom = 140 mV · TC = 47.4 ppm/°C

---

5. Precision High-Swing Regulated Cascode Current Mirror

Uses an op-amp in feedback to actively servo the cascode gate, forcing the reference and output drain nodes to the same potential regardless of load.

Error = 2.34% · Rout = 6.52 MΩ (best in study) · Vcom = 175 mV · TC = 0.62 ppm/°C (best in study)

---

6. Wilson Current Mirror

Uses negative feedback instead of cascode shielding. Produces a well-known current excess (not deficit) due to gm·rds loop asymmetry, and requires the highest compliance voltage in the study.

Error = 6.27% (excess) · Rout = 554 kΩ · Vcom = 450 mV (highest in study) · TC = 369.1 ppm/°C

---

Methodology

• Process: gpdk090 (90 nm CMOS), nmos1v / pmos1v devices, BSIM4 nominal models
• Tool: Cadence Virtuoso ADE-L, Spectre simulator
• Sizing: W = 1 µm, L = 200 nm for all devices (held constant across topologies)
• Sweeps run per topology: DC output sweep, temperature sweep (−40 °C to 120 °C), Vout compliance sweep
• Compliance voltage (Vcom): determined empirically by sweeping Vout until every transistor in the signal path reports region = 2 (saturation) in the Cadence DC operating-point annotation
• Bias point convention: Vbias = Vcom + 100 mV per topology, so every mirror is measured at a consistent, physically valid margin above its own saturation edge (not a single shared voltage that would push some topologies out of saturation)

Formulas used for every extracted parameter:

Current Matching Error (%) = |Iref − Icopy| / Iref × 100
Output Resistance (Ω)      = ΔVout / ΔIout   (two cursor points, saturation region)
Line Regulation (A/V)      = ΔIout / ΔVDD    (Vout held at Vbias)
Temp. Coefficient (ppm/°C) = (ΔIout / (Iref · ΔT)) × 10⁶
Static Power (W)           = VDD × Ibias_branch(es)

Full derivations, cursor readings, and per-topology calculation walkthroughs are in the project report.

---

Background theory notes

Hand-derived notes covering the square-law model, cascode Zout derivation, wide-swing bias generation, regulated-cascode gain boosting, and the Wilson mirror feedback mechanism:

---

Limitations & future work

• Rout is a two-point secant slope (ΔV/ΔI), not the instantaneous deriv() at Vbias — the local slope is a tighter estimate and is what's reported in the summary table
• Sub-1 ppm/°C and sub-pA/V readings are near the simulator's numerical noise floor and should be read as "below measurable threshold"
• Planned next steps: Monte Carlo mismatch analysis, PVT corner sweeps, op-amp gain optimization in the regulated cascode, physical layout with common-centroid matching, and integration into a beta-multiplier (constant-Gm) reference

---

Repo structure

CurrentMirror-Design-Analysis/
├── README.md
├── docs/
│   └── Current_Mirror_Project_Report.docx   ← full report with all derivations & calculations
└── images/
    ├── schematics/                          ← annotated Cadence schematics (DC operating points)
    ├── graphs/                              ← DC sweep / temperature sweep / compliance sweep plots
    └── notes/                               ← hand-derived background theory

---

Author: Mohit Kumar Gupta · B.Tech, Electronics and Communication Engineering · NIT Andhra Pradesh