I'm a second-year BE Computer Systems Engineering student at NED University of Engineering & Technology, Karachi. I work across the full stack — from writing RTL in SystemVerilog for FPGA targets all the way up to Angular frontends and NestJS backends.
I'm currently working on Post Quantum Cryptography algorithms, Kyber especially: optimising them for FPGAs and making a consolidated NTT core that supports both Kyber and Dilithium. Moreover, I'm working on implementing different processor architectures on Verilog such as RISC-V FPN Instruction Set and a 0-address stack-based 16-bit processor architecture that was my Complex Engineering Project for uni.
What drives me is the intersection of hardware and software — building things that work at the silicon level and understanding every layer above it.
Hardware & RTL
Languages
Frameworks & Tools
| Project | Description | Stack |
|---|---|---|
| FSM-UART-Serial-Interface | UART module built from scratch using FSM design — baud tick generator, TX/RX FSMs | SystemVerilog |
| FSM-XGA-VGA-Controller | FSM-based VGA controller for XGA (1024×768 @ 60Hz) on DE1-SoC | SystemVerilog |
| FPGA-Image-Pipeline-Simulator | FPGA-style image processing pipeline simulating hardware accelerator workflow | C++ |
| CEP-CS222 | Smart Campus Printing Management System — NestJS backend, Ionic mobile, Angular dashboard, Oracle DB | JavaScript |
- 🎓 Year 2 — BE Computer Systems Engineering @ NEDUET
- ⚡ Training at Xcelerium '25 — digital design & hardware engineering
- 🔭 Exploring RTL verification and deeper FPGA design patterns
- 📫 Reach me on LinkedIn