Mustafa Yagci Mustafa-Yagci

Mustafa Yağcı

⚡ Architectural Thesis: Dual-Track Engineering

"Bridging the Nanosecond Gap: From Precision Silicon to Low-Latency Execution."

My work converges at the intersection of physical layer electronics and computational execution systems:

Physical Layer & Silicon Architecture: Designing precision Analog Front-Ends (AFE) with CMRR >100 dB, synthesizing synthesizable FPGA RTL cores (Verilog/Vivado), architecting closed-loop power conversion topologies (Buck/Boost PI compensation), and developing virtual automated measurement instrumentation (LabVIEW / 16-bit SAR ADC).
Computational Layer & Quantitative Systems: Engineering microstructural market state classifiers, calculating high-frequency dollar bar flows, deploying convex portfolio risk engines (Hierarchical Risk Parity, CDaR), and testing extreme tail-risk protection architectures.

                           ┌───────────────────────────────────────────────┐
                           │              MUSTAFA YAĞCI                    │
                           └───────────────────────┬───────────────────────┘
                                                   │
             ┌─────────────────────────────────────┴─────────────────────────────────────┐
             ▼                                                                           ▼
┌─────────────────────────────────────────┐                         ┌─────────────────────────────────────────┐
│     PHYSICAL LAYER & HARDWARE SILICON   │                         │  COMPUTATIONAL LAYER & QUANT SYSTEMS    │
├─────────────────────────────────────────┤                         ├─────────────────────────────────────────┤
│ • Mixed-Signal PCB & Low-Noise AFE      │                         │ • Microstructure & Order Flow Imbalance │
│ • Instrumentation Amps (CMRR >100 dB)   │                         │ • Dollar/Volume Sampling & Trade Bars   │
│ • FPGA RTL (SystemVerilog, AXI4-Stream) │                         │ • Convex Portfolio Allocation (HRP/CDaR)│
│ • Switch-Mode Power Topologies & PSIM   │                         │ • EVT Value-at-Risk & Expected Shortfall│
│ • Virtual DAQ & ADC Characterization    │                         │ • Deterministic Low-Latency Execution   │
└─────────────────────────────────────────┘                         └─────────────────────────────────────────┘

🌟 Featured Engineering Pillars

🏛️ engineering-academic-portfolio

Undergraduate (B.Sc. Graduated) & Master's (M.Sc. Student, Ongoing) Practicum Archive

Complete historical archive of 92 files (~49 MB) across 6 years of laboratory research, industrial automation, and simulation models:

ESOGÜ Lisans (2019–2025, Mezun): Verilog Mealy FSM, MATLAB State-Space & Root-Locus, Siemens TIA Portal V17 PLC, Thyristor Power Electronics, RIE/SiO₂ fabrication.
UniPa M.Sc. (Kasım 2025–Günümüz, Devam Ediyor / Öğrenci): 65p Industrial Switch-Mode Power Report, 65p Virtual DAQ & 16-bit SAR ADC Suite, BioAmp Pro AFE, Applied Electronics.

🧬 unipa-bioamp-pro

Precision 4-Layer Biomedical Analog Front-End (KiCad 8)

Custom biomedical biopotential acquisition board (ECG/EMG/EEG) engineered from first principles:

CMRR >100 dB: Precision INA128 instrumentation stage with matched resistor networks.
Active Noise Suppression: Driven Right Leg (DRL) circuit suppressing 50/60 Hz common-mode mains hum.
Signal Chain: 4-stage active bandpass & twin-T notch filter with complete Gerbers and assembly BOM.

📟 fpga-axi-fir-dsp-verification

High-Throughput Parameterized AXI4-Stream DSP Filter

Synthesizable RTL architecture for streaming digital signal processing targeting Xilinx 7-Series / UltraScale+:

RTL Architecture: Parameterized systolic FIR filter core with symmetric coefficient folding.
AXI4-Stream Protocol: Full backpressure flow control (`TREADY`/`TVALID`) with zero slip.
Verification: Self-checking testbench in cocotb and Vivado XSim verifying impulse and frequency responses.

📊 hrp-cdar-portfolio-optimizer-v3

Hierarchical Risk Parity & CDaR Convex Portfolio Allocator

Institutional portfolio optimization engine eliminating instability in Markowitz quadratic inversion:

Machine Learning Tree Clustering: Quasi-diagonalization of empirical asset correlation matrices.
Drawdown Risk Control: Conditional Drawdown-at-Risk (CDaR) linear programming constraints.
Walk-Forward Validation: Tested across rolling regimes with transaction-cost friction models.

🛡️ var-risk-shield

High-Throughput Tail-Risk & Extreme Value Theory Engine

Automated quantitative risk suite calculating multivariable exposure under non-Gaussian tail behavior:

EVT Peaks-Over-Threshold: Generalized Pareto Distribution (GPD) fitting for fat-tailed drawdowns.
Parametric & Historical VaR: Cornish-Fisher expansion incorporating skewness and excess kurtosis.
Kupiec & Christoffersen: Rigorous statistical backtesting for conditional coverage.

⚡ microstructure-dollar-bars-engine

Tick-Level Flow Imbalance & Rolling Kalman Filter

Ultra-low-latency financial time series processor and market state estimation engine:

De Prado Dollar Bars: Sub-sampling tick streams by dollar volume to restore Gaussianity.
Order Flow Imbalance (OFI): Level-2 book delta tracking for short-term liquidity sweeps.
Rolling Kalman Filter: Dynamic hedge ratio and mean-reverting cointegration tracking.

🛠️ Technical Competencies & Toolchain

Domain	Technologies, Frameworks & Tooling
EDA & Hardware Design
Languages & HDL
Quantitative & Scientific
Protocols & Interfaces

📈 Activity & GitHub Metrics

📬 Contact & Collaboration

Email: mrmustafayagci@gmail.com
LinkedIn: Mustafa Yağcı
Academic Affiliation: Università degli Studi di Palermo (UniPa), M.Sc. Student in Electronic Engineering (Nov 2025 – Present / Ongoing)

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