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Fix: fix hang in FSDP UBR with symmetric registration#3565

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Fix: fix hang in FSDP UBR with symmetric registration#3565
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@youngeunkwon0405 youngeunkwon0405 commented Feb 24, 2026

Currently, nccl ubr with symmetric registration causes a hang when we have multiple optimizer instances.
This is a WAR fix to avoid that issue, targeting the release branch.

By this change, user buffer registration is done only for the DP_CP group, which is the most important target to register the buffers.

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Signed-off-by: Youngeun Kwon <youngeunk@nvidia.com>
@youngeunkwon0405 youngeunkwon0405 requested review from a team as code owners February 24, 2026 20:09
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/ok to test f5ff88b

@svcnvidia-nemo-ci svcnvidia-nemo-ci added this to the Core 0.16 milestone Feb 24, 2026
@shjwudp shjwudp changed the title Fix: fix hang in FSPD UBR with symmetric registration Fix: fix hang in FSDP UBR with symmetric registration Feb 25, 2026
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cspades commented Mar 4, 2026

This specific hang should be fixed by using UBR on every communication buffer (in HSDP/HFSDP in particular, which had unregistered communication buffers), which is a corollary of my data-type customization work in this PR: #3067

I believe it is directly caused by deallocation of temporary buffers that hangs registration after the first pass. (Or something related to that.) Properly using GlobalMemoryBuffer / FixedPoolAllocator for every communication buffer, input and output, fixed my instance of this hang.

@youngeunkwon0405 @dingqingy-nv to confirm if main works!

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I am wrong. This is NOT the same hang I experienced. It hangs post-UBR, so it is not caused by UBR directly, but indirectly!

Clearly UBR is successful:

INFO:megatron.core.distributed.fsdp.src.megatron_fsdp.param_and_grad_buffer:[MCORE][FSDP][Manual REG] Registered mem pool to group <torch.distributed.distributed_c10d.ProcessGroup object at 0xfffc02cee470>,group.group_desc:INTRA_PARTIAL_DATA_PARALLEL_GROUP_WITH_CP, group.size(): 32

INFO:megatron.core.distributed.fsdp.src.megatron_fsdp.param_and_grad_buffer:[MCORE][FSDP][Manual REG] Registered mem pool to group <torch.distributed.distributed_c10d.ProcessGroup object at 0xfffc02c4eff0>,group.group_desc:HIERARCHICAL_EXPERT_DATA_PARALLEL_GROUP_L0, group.size(): 32

INFO:megatron.core.distributed.fsdp.src.megatron_fsdp.param_and_grad_buffer:[MCORE][FSDP][Manual REG] Registered mem pool to group <torch.distributed.distributed_c10d.ProcessGroup object at 0xfffc02c4ebf0>,group.group_desc:HIERARCHICAL_EXPERT_DATA_PARALLEL_GROUP_L1, group.size(): 2

Aligned to merge this as a WAR to main branch since the DP-Outer group does not have significant performance ramifications for HSDP/HFSDP. We can reduce gradients in native precision and not use symmetric kernels for these groups.

@youngeunkwon0405 to add a FIXME(@youngeunkwon0405, @cspades) note explaining why we need the WAR (though it looks 👌🏻 already, maybe just to put our names onto the bug as a TODO), and also if you could double check if all 3 of those groups cause the hang, and not just one or two of them. (That will be the first thing I check when I investigate this.)

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