Performance improvements [2]#4
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Signed-off-by: Maxim Menshikov <maksim.menshikov@nethermind.io>
Signed-off-by: Maxim Menshikov <maksim.menshikov@nethermind.io>
Simplify the inline write-barrier patch by removing the JitRiscV64InlineWriteBarrier config knob and the out-of-line fallback paths. GC ref stores are now unconditionally emitted as plain inline stores on RISC-V64, since uGC never relocates and the helpers are already barrier-free. LSRA no longer pins addr/data to t3/t4. Signed-off-by: Maxim Menshikov <maksim.menshikov@nethermind.io>
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