feat(matrix): Support XSAI AME proposal 12

src/main/scala/xiangshan/Parameters.scala

@@ -66,7 +66,6 @@ case class XSCoreParameters
   TLEN: Int = 128 * 64 * 8,   // Expect TMMAX 128 TNMAX 128 TKMAX 64 with e8
   TRLEN: Int = 64 * 8,         // 64 * e8
   MELEN: Int = 32,
-  MTOK: Int = 32,             // 8 or 16 or 32
   MTILEXLEN: Int = 9,         // 9 bits is sufficient
   HasMExtension: Boolean = true,
   HasCExtension: Boolean = true,
@@ -170,7 +169,7 @@ case class XSCoreParameters
   V0LogicRegs: Int = 1, // V0
   VlLogicRegs: Int = 1, // Vl
   MxLogicRegs: Int = 3, // Mtilem, Mtilen, Mtilek
-  TokenRegs: Int = 32,  // 8 / 16 / 32
+  MsyncRegs: Int = 32,  // 8 / 16 / 32
   V0_IDX: Int = 0,
   Vl_IDX: Int = 0,
   Mtilem_IDX: Int = 0,
@@ -433,7 +432,7 @@ case class XSCoreParameters
       ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize),
       IssueBlockParams(Seq(
         ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2),
-        ExeUnitParams("BJU3", Seq(CsrCfg, FenceCfg, DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(0, 1)), Seq(IntRD(1, 1)))),
+        ExeUnitParams("BJU3", Seq(CsrCfg, FenceCfg, DivCfg) ++ (if (HasMatrixExtension) Seq(McfgCfg) else Nil), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(0, 1)), Seq(IntRD(1, 1)))),
       ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize),
     ) ++ (
       if (HasMatrixExtension) Seq(
@@ -673,7 +672,6 @@ trait HasXSParameter {
   def ROWNUM = TLEN / TRLEN
   def ARLEN = ROWNUM * MELEN
   def ALEN = ARLEN * ROWNUM
-  def MTOK = coreParams.MTOK
 
   def DEV_FIXED_MTYPE = false
 
@@ -827,7 +825,7 @@ trait HasXSParameter {
   def VlLogicRegs = coreParams.VlLogicRegs
   def MxLogicRegs = coreParams.MxLogicRegs
   def MaxLogicRegs = Set(IntLogicRegs, FpLogicRegs, VecLogicRegs, V0LogicRegs, VlLogicRegs).max
-  def TokenRegs = coreParams.TokenRegs
+  def MsyncRegs = coreParams.MsyncRegs
   def LogicRegsWidth = log2Ceil(MaxLogicRegs)
   def V0_IDX = coreParams.V0_IDX
   def Vl_IDX = coreParams.Vl_IDX

src/main/scala/xiangshan/backend/Backend.scala

@@ -805,9 +805,9 @@ class BackendInlinedImp(override val wrapper: BackendInlined)(implicit p: Parame
   fpExuBlock.io.vxrm.foreach(_ := csrio.vpu.vxrm)
   vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm)
   vfExuBlock.io.vxrm.foreach(_ := csrio.vpu.vxrm)
-  mfExuBlock.foreach(_.io.xmxrm.foreach(_ := csrio.mpu.xmxrm))
-  mfExuBlock.foreach(_.io.xmfrm.foreach(_ := csrio.mpu.xmfrm))
-  mfExuBlock.foreach(_.io.xmsaten.foreach(_ := csrio.mpu.xmsaten))
+  mfExuBlock.foreach(_.io.mxrm.foreach(_ := csrio.mpu.mxrm))
+  mfExuBlock.foreach(_.io.mfrm.foreach(_ := csrio.mpu.mfrm))
+  mfExuBlock.foreach(_.io.msaten.foreach(_ := csrio.mpu.msaten))
 
   wbDataPath.io.flush := ctrlBlock.io.redirect
   wbDataPath.io.fromTop.hartId := io.fromTop.hartId
@@ -973,6 +973,7 @@ class BackendInlinedImp(override val wrapper: BackendInlined)(implicit p: Parame
     sink.bits.uop.vpu            := source.bits.vpu.getOrElse(0.U.asTypeOf(new VPUCtrlSignals))
     sink.bits.uop.preDecodeInfo  := source.bits.preDecode.getOrElse(0.U.asTypeOf(new PreDecodeInfo))
     sink.bits.uop.numLsElem      := source.bits.numLsElem.getOrElse(0.U) // Todo: remove this bundle, keep only the one below
+    sink.bits.uop.mcfgReadView.foreach(_.entry.raw := source.bits.mcfgReadRaw.get)
     sink.bits.flowNum.foreach(_  := source.bits.numLsElem.get)
   }
   io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch)

src/main/scala/xiangshan/backend/Bundles.scala

@@ -116,7 +116,10 @@ object Bundles {
     val uopSplitType    = UopSplitType()
     val isVset          = Bool()
     val isMsettilex     = Bool()
+    val isMsetcfg       = Bool()
     val needAmuCtrl     = Bool()
+    val mcfgReadView    = OptionWrapper(HasMatrixExtension, new xiangshan.backend.decode.McfgReadView)
+    val mmaMcfgReadRaw  = OptionWrapper(HasMatrixExtension, Vec(3, UInt(XLEN.W)))
     val firstUop        = Bool()
     val lastUop         = Bool()
     val numUops         = UInt(log2Up(MaxUopSize).W) // rob need this
@@ -218,6 +221,9 @@ object Bundles {
     val uopIdx          = UopIdx()
     val isVset          = Bool()
     val needAmuCtrl     = OptionWrapper(HasMatrixExtension, Bool())
+    val isMsetcfg       = Bool()
+    val mcfgReadView    = OptionWrapper(HasMatrixExtension, new xiangshan.backend.decode.McfgReadView)
+    val mmaMcfgReadRaw  = OptionWrapper(HasMatrixExtension, Vec(3, UInt(XLEN.W)))
     val firstUop        = Bool()
     val lastUop         = Bool()
     val numUops         = UInt(log2Up(MaxUopSize).W) // rob need this
@@ -694,6 +700,8 @@ object Bundles {
 
     val perfDebugInfo = new PerfDebugInfo()
     val debug_seqNum = InstSeqNum()
+    val mcfgReadRaw = OptionWrapper(HasMatrixExtension, UInt(XLEN.W))
+    val mmaMcfgReadRaw = OptionWrapper(HasMatrixExtension, Vec(3, UInt(XLEN.W)))
 
     def exuIdx = this.params.exuIdx
 
@@ -735,6 +743,8 @@ object Bundles {
       this.numLsElem     .foreach(_ := source.common.numLsElem.get)
       this.srcTimer      .foreach(_ := source.common.srcTimer.get)
       this.loadDependency.foreach(_ := source.common.loadDependency.get.map(_ << 1))
+      this.mcfgReadRaw.foreach(_ := source.common.mcfgReadRaw.get)
+      this.mmaMcfgReadRaw.foreach(_ := source.common.mmaMcfgReadRaw.get)
     }
   }
 

src/main/scala/xiangshan/backend/CtrlBlock.scala

@@ -399,6 +399,10 @@ class CtrlBlockImp(
   decode.io.fromRob.walkToArchVType := rob.io.toDecode.walkToArchVType
   decode.io.fromRob.commitVType := rob.io.toDecode.commitVType
   decode.io.fromRob.walkVType := rob.io.toDecode.walkVType
+  decode.io.fromRob.isResumeMcfg := rob.io.toDecode.isResumeMcfg
+  decode.io.fromRob.walkToArchMcfg := rob.io.toDecode.walkToArchMcfg
+  decode.io.fromRob.commitMcfg := rob.io.toDecode.commitMcfg
+  decode.io.fromRob.walkMcfg := rob.io.toDecode.walkMcfg
 
   decode.io.redirect := s1_s3_redirect.valid || s2_s4_pendingRedirectValid
 
@@ -805,6 +809,7 @@ class CtrlBlockImp(
 
   // rob to backend
   io.robio.commitVType := rob.io.toDecode.commitVType
+  io.robio.commitMcfg := rob.io.toDecode.commitMcfg
   // exu block to decode
   decode.io.vsetvlVType := io.toDecode.vsetvlVType
   // backend to decode
@@ -964,6 +969,7 @@ class CtrlBlockIO()(implicit p: Parameters, params: BackendParams) extends XSBun
       val vtype = Output(ValidIO(VType()))
       val hasVsetvl = Output(Bool())
     }
+    val commitMcfg = Output(Vec(CommitWidth, ValidIO(new xiangshan.backend.decode.McfgCommit)))
 
     // store event difftest information
     val storeDebugInfo = Vec(EnsbufferWidth, new Bundle {

src/main/scala/xiangshan/backend/decode/DecodeStage.scala

@@ -67,6 +67,10 @@ class DecodeStageIO(implicit p: Parameters) extends XSBundle {
       val hasVsetvl = Input(Bool())
     }
     val walkVType = Flipped(Valid(new VType))
+    val isResumeMcfg = Input(Bool())
+    val walkToArchMcfg = Input(Bool())
+    val commitMcfg = Flipped(Vec(CommitWidth, Valid(new McfgCommit)))
+    val walkMcfg = Flipped(Vec(CommitWidth, Valid(new McfgCommit)))
   }
   val stallReason = new Bundle {
     val in = Flipped(new StallReasonIO(DecodeWidth))
@@ -106,6 +110,8 @@ class DecodeStage(implicit p: Parameters) extends XSModule
   val decoders = Seq.fill(DecodeWidth)(Module(new DecodeUnit))
   /** vtype generation module */
   val vtypeGen = Module(new VTypeGen)
+  /** mcfg generation module */
+  val mcfgGen = Module(new McfgGen)
 
   val debug_globalCounter = RegInit(0.U(XLEN.W))
 
@@ -119,6 +125,7 @@ class DecodeStage(implicit p: Parameters) extends XSModule
     dst.io.fromCSR := io.fromCSR
     dst.io.enq.vtype := vtypeGen.io.vtype
     dst.io.enq.vstart := io.vstart
+    dst.io.enq.mcfg := mcfgGen.io.mcfg
   }
 
   /** whether instructions decoded by simple decoders require complex decoding */
@@ -164,13 +171,17 @@ class DecodeStage(implicit p: Parameters) extends XSModule
   vtypeGen.io.walkVType := io.fromRob.walkVType
   vtypeGen.io.vsetvlVType := io.vsetvlVType
 
+  mcfgGen.io.walkToArchMcfg := io.fromRob.walkToArchMcfg
+  mcfgGen.io.walkMcfg := io.fromRob.walkMcfg
+  mcfgGen.io.commitMcfg := io.fromRob.commitMcfg
+
   //Comp 1
   decoderComp.io.redirect := io.redirect
   decoderComp.io.csrCtrl := io.csrCtrl
   decoderComp.io.vtypeBypass := vtypeGen.io.vtype
   // The input inst of decoderComp is latched last cycle.
   // Set input empty, if there is no complex inst latched last cycle.
-  decoderComp.io.in.valid := complexValid && !io.fromRob.isResumeVType
+  decoderComp.io.in.valid := complexValid && !io.fromRob.isResumeVType && !io.fromRob.isResumeMcfg
   decoderComp.io.in.bits.simpleDecodedInst := complexInst
   decoderComp.io.in.bits.uopInfo := complexUopInfo
   decoderComp.io.out.complexDecodedInsts.zipWithIndex.foreach { case (out, i) => out.ready := io.out(i).ready }
@@ -196,7 +207,8 @@ class DecodeStage(implicit p: Parameters) extends XSModule
   val hasMatrixInst = false.B
 
   /** condition of acceptation: no redirection, ready from rename/complex decoder, no resumeVType/resumeMType */
-  canAccept := !io.redirect && (io.out.head.ready || decoderComp.io.in.ready) && !io.fromRob.isResumeVType
+  canAccept := !io.redirect && (io.out.head.ready || decoderComp.io.in.ready) &&
+    !io.fromRob.isResumeVType && !io.fromRob.isResumeMcfg
 
   io.canAccept := canAccept
 
@@ -213,7 +225,7 @@ class DecodeStage(implicit p: Parameters) extends XSModule
     in.ready := !io.redirect && (
       simplePrefixVec(i) && (i.U +& complexNum) < readyCounter ||
       firstComplexOH(i) && (i.U +& complexNum) <= readyCounter && decoderComp.io.in.ready
-    ) && !io.fromRob.isResumeVType
+    ) && !io.fromRob.isResumeVType && !io.fromRob.isResumeMcfg
   }
 
   /** final instruction decoding result */
@@ -235,7 +247,7 @@ class DecodeStage(implicit p: Parameters) extends XSModule
    * Note that finalDecodedInst is generated in order.
    */
   io.out.zipWithIndex.foreach { case (inst, i) =>
-    inst.valid := finalDecodedInstValid(i) && !io.fromRob.isResumeVType
+    inst.valid := finalDecodedInstValid(i) && !io.fromRob.isResumeVType && !io.fromRob.isResumeMcfg
     inst.bits := finalDecodedInst(i)
     inst.bits.lsrc(0) := Mux(finalDecodedInst(i).vpu.isReverse, finalDecodedInst(i).lsrc(1), finalDecodedInst(i).lsrc(0))
     inst.bits.lsrc(1) := Mux(finalDecodedInst(i).vpu.isReverse, finalDecodedInst(i).lsrc(0), finalDecodedInst(i).lsrc(1))

src/main/scala/xiangshan/backend/decode/DecodeUnit.scala

@@ -827,6 +827,7 @@ class DecodeUnitEnqIO(implicit p: Parameters) extends XSBundle {
   val ctrlFlow = Input(new StaticInst)
   val vtype = Input(new VType)
   val vstart = Input(Vl())
+  val mcfg = Input(new McfgState)
 }
 
 class DecodeUnitDeqIO(implicit p: Parameters) extends XSBundle {
@@ -921,6 +922,9 @@ class DecodeUnit(implicit p: Parameters) extends XSModule with DecodeUnitConstan
   decodedInst.vlWen := false.B
   // init mxWen
   decodedInst.mxWen.foreach(_ := false.B)
+  decodedInst.isMsetcfg := false.B
+  decodedInst.mcfgReadView.foreach(_ := 0.U.asTypeOf(decodedInst.mcfgReadView.get))
+  decodedInst.mmaMcfgReadRaw.foreach(_ := 0.U.asTypeOf(decodedInst.mmaMcfgReadRaw.get))
 
   val isCsr = inst.OPCODE5Bit === OPCODE5Bit.SYSTEM && inst.FUNCT3(1, 0) =/= 0.U
   val isCsrr = isCsr && inst.FUNCT3 === BitPat("b?1?") && inst.RS1 === 0.U
@@ -936,6 +940,7 @@ class DecodeUnit(implicit p: Parameters) extends XSModule with DecodeUnitConstan
   private val isCboFlush = CBO_FLUSH === io.enq.ctrlFlow.instr
   private val isCboInval = CBO_INVAL === io.enq.ctrlFlow.instr
   private val isCboZero  = CBO_ZERO  === io.enq.ctrlFlow.instr
+  private val isMfence   = MFENCE    === io.enq.ctrlFlow.instr
 
   // Note that rnum of aes64ks1i must be in the range 0x0..0xA. The values 0xB..0xF are reserved.
   private val isAes64ks1iIllegal =
@@ -959,7 +964,7 @@ class DecodeUnit(implicit p: Parameters) extends XSModule with DecodeUnitConstan
       inst.isOPFVF || inst.isOPFVV
     ) ||
     io.fromCSR.illegalInst.vsIsOff    && (FuType.FuTypeOrR(decodedInst.fuType, FuType.vecAll) || isCsrrVl || isCsrrVlenb) ||
-    // io.fromCSR.illegalInst.msIsOff    && FuType.FuTypeOrR(decodedInst.fuType, FuType.matrixAll) ||
+    // io.fromCSR.illegalInst.msIsOff    && (FuType.FuTypeOrR(decodedInst.fuType, FuType.matrixAll) || isMfence) ||
     io.fromCSR.illegalInst.wfi        && FuType.FuTypeOrR(decodedInst.fuType, FuType.csr)   && CSROpType.isWfi(decodedInst.fuOpType) ||
     io.fromCSR.illegalInst.wrs_nto    && FuType.FuTypeOrR(decodedInst.fuType, FuType.csr)   && CSROpType.isWrsNto(decodedInst.fuOpType) ||
     (decodedInst.needFrm.scalaNeedFrm || FuType.isScalaNeedFrm(decodedInst.fuType)) && (((decodedInst.fpu.rm === 5.U) || (decodedInst.fpu.rm === 6.U)) || ((decodedInst.fpu.rm === 7.U) && io.fromCSR.illegalInst.frm)) ||
@@ -1155,15 +1160,14 @@ class DecodeUnit(implicit p: Parameters) extends XSModule with DecodeUnitConstan
   io.deq.uopInfo.numOfWB := uopInfoGen.io.out.uopInfo.numOfWB
   io.deq.uopInfo.lmul := uopInfoGen.io.out.uopInfo.lmul
 
-  // The same as above, but for xmisa, xtlenb, xtrlenb, xalenb, mtok, mtilem, mtilen, mtilek
-  val isCsrrXmisa = isCsrr && inst.CSRIDX === CSRs.xmisa.U
-  val isCsrrXtlenb = isCsrr && inst.CSRIDX === CSRs.xtlenb.U
-  val isCsrrXtrlenb = isCsrr && inst.CSRIDX === CSRs.xtrlenb.U
-  val isCsrrXalenb = isCsrr && inst.CSRIDX === CSRs.xalenb.U
-  val isCsrrMtok   = isCsrr && inst.CSRIDX === CSRs.mtok.U
+  // The same as above, but for tlenb, trlenb, alenb, msync, mtilem, mtilen, mtilek
+  val isCsrrTlenb = isCsrr && inst.CSRIDX === CSRs.tlenb.U
+  val isCsrrTrlenb = isCsrr && inst.CSRIDX === CSRs.trlenb.U
+  val isCsrrAlenb = isCsrr && inst.CSRIDX === CSRs.alenb.U
   val isCsrrMtilem = isCsrr && inst.CSRIDX === CSRs.mtilem.U
   val isCsrrMtilen = isCsrr && inst.CSRIDX === CSRs.mtilen.U
   val isCsrrMtilek = isCsrr && inst.CSRIDX === CSRs.mtilek.U
+  val isCsrrMsync  = isCsrr && inst.CSRIDX === CSRs.msync.U
 
   // decode for SoftPrefetch instructions (prefetch.w / prefetch.r / prefetch.i)
   val isSoftPrefetch = inst.OPCODE === BitPat("b0010011") && inst.FUNCT3 === BitPat("b110") && inst.RD === 0.U
@@ -1175,6 +1179,8 @@ class DecodeUnit(implicit p: Parameters) extends XSModule with DecodeUnitConstan
   val isFLI = inst.FUNCT7 === BitPat("b11110??") && inst.RS2 === 1.U && inst.RM === 0.U && inst.OPCODE5Bit === OPCODE5Bit.OP_FP
 
   val isMsettilex = FuType.isMsettilex(decodedInst.fuType)
+  val isMcfg = MSetOpType.isMcfg(decodedInst.fuOpType)
+  val isMsetcfg = MSetOpType.isMsetcfg(decodedInst.fuOpType)
   val isMMA = FuType.isMMA(decodedInst.fuType)
   val isMls = FuType.isMls(decodedInst.fuType)
   val isMarith = FuType.isMarith(decodedInst.fuType)
@@ -1212,7 +1218,7 @@ class DecodeUnit(implicit p: Parameters) extends XSModule with DecodeUnitConstan
     decodedInst.blockBackward := false.B
     decodedInst.canRobCompress := true.B
     decodedInst.exceptionVec(illegalInstr) := io.fromCSR.illegalInst.vsIsOff
-  }.elsewhen (isCsrrXmisa || isCsrrXtlenb || isCsrrXtrlenb || isCsrrXalenb || isCsrrMtok) {
+  }.elsewhen (isCsrrTlenb || isCsrrTrlenb || isCsrrAlenb || isCsrrMsync) {
     // convert to addi instruction
     decodedInst.srcType(0) := SrcType.reg
     decodedInst.srcType(1) := SrcType.imm
@@ -1236,8 +1242,21 @@ class DecodeUnit(implicit p: Parameters) extends XSModule with DecodeUnitConstan
     decodedInst.lsrc(0) := 0.U
   }.elsewhen (isMsettilex) {
     decodedInst.mxWen.foreach(_ := true.B)
-    decodedInst.ldest      := MSETtilexOpType.toMxIdx(decodedInst.fuOpType)
+    decodedInst.ldest      := MSetOpType.toMxIdx(decodedInst.fuOpType)
+  }.elsewhen (isMcfg) {
+    decodedInst.isMsetcfg := isMsetcfg
+    decodedInst.mcfgReadView.foreach { view =>
+      val sel = Mux(isMsetcfg, inst.RD(2, 0), inst.RS1(2, 0))
+      view.sel := sel
+      view.entry := io.enq.mcfg.entries(sel)
+    }
   }.elsewhen (isMMA) {
+    val mmaMcfgSels = Seq(inst.RS1(2, 0), inst.RS2(2, 0), inst.RD(2, 0))
+    decodedInst.mmaMcfgReadRaw.foreach { raws =>
+      raws.zip(mmaMcfgSels).foreach { case (raw, sel) =>
+        raw := io.enq.mcfg.entries(sel).raw
+      }
+    }
     decodedInst.srcType(0) := SrcType.no
     decodedInst.srcType(1) := SrcType.no
     decodedInst.srcType(2) := SrcType.mx
@@ -1265,6 +1284,11 @@ class DecodeUnit(implicit p: Parameters) extends XSModule with DecodeUnitConstan
       decodedInst.fuOpType(6, 3),
       Seq(Mtilek_IDX.U, Mtilen_IDX.U, Mtilen_IDX.U, 0.U)
     )
+    decodedInst.mcfgReadView.foreach { view =>
+      val mlsMcfgSel = inst.RD(2, 0)
+      view.sel := mlsMcfgSel
+      view.entry := io.enq.mcfg.entries(mlsMcfgSel)
+    }
   }.elsewhen (isMarith) {
     decodedInst.srcType(0) := SrcType.no
     decodedInst.srcType(1) := SrcType.no
@@ -1278,18 +1302,17 @@ class DecodeUnit(implicit p: Parameters) extends XSModule with DecodeUnitConstan
   io.deq.decodedInst.fuType := Mux1H(Seq(
     // keep condition
     (!FuType.FuTypeOrR(decodedInst.fuType, FuType.vldu, FuType.vstu) && 
-      !isCsrrVl && !isCsrrVlenb && !isCsrrXmisa && !isCsrrXtlenb && !isCsrrXtrlenb && !isCsrrXalenb &&
-      !isCsrrMtok && !isCsrrMtilem && !isCsrrMtilen && !isCsrrMtilek) -> decodedInst.fuType,
+      !isCsrrVl && !isCsrrVlenb && !isCsrrTlenb && !isCsrrTrlenb && !isCsrrAlenb &&
+      !isCsrrMsync && !isCsrrMtilem && !isCsrrMtilen && !isCsrrMtilek) -> decodedInst.fuType,
     (isCsrrVl) -> FuType.vsetfwf.U,
     (isCsrrVlenb) -> FuType.alu.U,
     (isCsrrMtilem) -> FuType.msetmtilexfwf.U,
     (isCsrrMtilen) -> FuType.msetmtilexfwf.U,
     (isCsrrMtilek) -> FuType.msetmtilexfwf.U,
-    (isCsrrXmisa) -> FuType.alu.U,
-    (isCsrrXtlenb) -> FuType.alu.U,
-    (isCsrrXtrlenb) -> FuType.alu.U,
-    (isCsrrXalenb) -> FuType.alu.U,
-    (isCsrrMtok) -> FuType.alu.U,
+    (isCsrrTlenb) -> FuType.alu.U,
+    (isCsrrTrlenb) -> FuType.alu.U,
+    (isCsrrAlenb) -> FuType.alu.U,
+    (isCsrrMsync) -> FuType.alu.U,
 
     // change vlsu to vseglsu when NF =/= 0.U
     ( FuType.FuTypeOrR(decodedInst.fuType, FuType.vldu, FuType.vstu) && inst.NF === 0.U || (inst.NF =/= 0.U && (inst.MOP === "b00".U && inst.SUMOP === "b01000".U))) -> decodedInst.fuType,
@@ -1303,24 +1326,22 @@ class DecodeUnit(implicit p: Parameters) extends XSModule with DecodeUnitConstan
   io.deq.decodedInst.imm := MuxCase(decodedInst.imm, Seq(
     isCsrrVlenb  -> (VLEN / 8).U,
     isZimop      -> 0.U,
-    isCsrrXmisa  -> 0x2e6.U,
-    isCsrrXtlenb -> (TLEN / 8).U,
-    isCsrrXtrlenb -> (TRLEN / 8).U,
-    isCsrrXalenb -> ((TLEN / TRLEN) * (TLEN / TRLEN) * MELEN / 8).U,
-    isCsrrMtok   -> MTOK.U,
+    isCsrrTlenb -> (TLEN / 8).U,
+    isCsrrTrlenb -> (TRLEN / 8).U,
+    isCsrrAlenb -> ((TLEN / TRLEN) * (TLEN / TRLEN) * MELEN / 8).U,
+    isCsrrMsync   -> MsyncRegs.U,
   ))
 
   io.deq.decodedInst.fuOpType := MuxCase(decodedInst.fuOpType, Seq(
     isCsrrVl    -> VSETOpType.csrrvl,
     isCsrrVlenb -> ALUOpType.add,
-    isCsrrMtilem -> MSETtilexOpType.csrrmtilem,
-    isCsrrMtilen -> MSETtilexOpType.csrrmtilen,
-    isCsrrMtilek -> MSETtilexOpType.csrrmtilek,
-    isCsrrXmisa -> ALUOpType.add,
-    isCsrrXtlenb -> ALUOpType.add,
-    isCsrrXtrlenb -> ALUOpType.add,
-    isCsrrXalenb -> ALUOpType.add,
-    isCsrrMtok -> ALUOpType.add,
+    isCsrrMtilem -> MSetOpType.csrrmtilem,
+    isCsrrMtilen -> MSetOpType.csrrmtilen,
+    isCsrrMtilek -> MSetOpType.csrrmtilek,
+    isCsrrTlenb -> ALUOpType.add,
+    isCsrrTrlenb-> ALUOpType.add,
+    isCsrrAlenb -> ALUOpType.add,
+    isCsrrMsync  -> ALUOpType.add,
     isFLI       -> Cat(1.U, inst.FMT, inst.RS1),
     (isPreW || isPreR || isPreI) -> Mux1H(Seq(
       isPreW -> LSUOpType.prefetch_w,