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fix(rob): ExceptionGen for matrix insts #71

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Merged
yu-yake2002 merged 1 commit into from
Jun 4, 2026
Merged

fix(rob): ExceptionGen for matrix insts #71

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5 changes: 4 additions & 1 deletion src/main/scala/xiangshan/backend/rob/ExceptionGen.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -91,8 +91,11 @@ class ExceptionGen(params: BackendParams)(implicit p: Parameters) extends XSModu
val store_wb = io.wb.zip(wbExuParams).filter(_._2.fuConfigs.filter(t => t.isSta || t.fuType == FuType.mou).nonEmpty).map(_._1)
val varith_wb = io.wb.zip(wbExuParams).filter(_._2.fuConfigs.filter(_.isVecArith).nonEmpty).map(_._1)
val vls_wb = io.wb.zip(wbExuParams).filter(_._2.fuConfigs.exists(x => FuType.FuTypeOrR(x.fuType, FuType.vecMem))).map(_._1)
val matrix_wb = io.wb.zip(wbExuParams).filter(
_._2.fuConfigs.exists(x => FuType.FuTypeOrR(x.fuType, FuType.matrixAll))
).map(_._1)

val writebacks = Seq(csr_wb, load_wb, store_wb, varith_wb, vls_wb)
val writebacks = Seq(csr_wb, load_wb, store_wb, varith_wb, vls_wb, matrix_wb).filter(_.nonEmpty)
val in_wb_valids = writebacks.map(_.map(w => w.valid && w.bits.has_exception && !lastCycleFlush))
val wb_valid = in_wb_valids.zip(writebacks).map { case (valid, wb) =>
valid.zip(wb.map(_.bits)).map { case (v, bits) => v && !(bits.robIdx.needFlush(io.redirect) || io.flush) }.reduce(_ || _)
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