Welcome to the RTL Workshop, a hands-on learning series focused on Verilog RTL design, simulation, synthesis, and digital circuit optimization. This repository is structured into multiple days, each with its own practical labs, code examples, and explanations.
This workshop is intended for students, hobbyists, and engineers who want to learn about:
- Verilog RTL design and simulation
- Using Icarus Verilog and GTKWave for simulation and waveform analysis
- Logic synthesis using Yosys and the SKY130 open-source PDK
- Key digital design concepts: testbenches, timing libraries, D flip-flop coding styles, and optimization techniques
- Basic understanding of digital logic (gates, flip-flops, multiplexers, etc.)
- Familiarity with Linux shell commands
- A Linux environment (or WSL on Windows/macOS)
- Tools:
git,iverilog,gtkwave,yosys, and a text editor
The workshop is organized by day, each with a dedicated folder and README:
- Day 1: Introduction to Verilog RTL Design & Synthesis
- Day 2: Timing Libraries, Synthesis Approaches, and Efficient Flip-Flop Coding
- Day 3: Combinational and Sequential Optimization
- Day 4: Gate-Level Simulation (GLS), Blocking vs. Non-Blocking in Verilog, and Synthesis-Simulation Mismatch
- Day 5: Optimization in Synthesis
Each day’s README includes:
- Clear explanations of the day’s concepts
- Step-by-step practical labs with code and screenshots
- Tips and best practices for RTL design
This project is licensed under the Attribution 4.0 International License - see the LICENSE file for details.
- Shon Taware
- Kunal Ghosh
- Open-source tools providers like Yosys and Sky130 PDK.
