RISC-Machine/cpu_tb.sv at main · PieBeast/RISC-Machine · GitHub

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
module cpu_tb();

reg sim_clk, sim_reset, sim_s, sim_load;
reg [15:0] sim_in;
wire [15:0] sim_out;
wire sim_N, sim_V, sim_Z, sim_w;

cpu DUT(
    .clk(sim_clk),
    .reset(sim_reset),
    .s(sim_s),
    .load(sim_load),
    .in(sim_in),
    .out(sim_out),
    .N(sim_N),
    .V(sim_V),
    .Z(sim_Z),
    .w(sim_w)
);
initial begin
    sim_clk = 0; #5;
    forever begin
        sim_clk = 1; #5;
        sim_clk = 0; #5;
    end
end
initial begin
//MOV R0, #10
    sim_reset = 1;
    sim_s = 0;
    sim_load = 0;
    sim_in = 16'b0;
    #10;
    sim_reset = 0;
    #10;

    sim_in = 16'b1101000000001010;
    sim_load = 1;
    #10;
    sim_load = 0;
    sim_s = 1;
    #10
    sim_s = 0;
    @(posedge sim_w);
    #10;
    $display("Expected %d, actual %d", 10, cpu_tb.DUT.DP.REGFILE.R0);
//MOV R1, #3
    @(negedge sim_clk);
    sim_in = 16'b1101000100000011;
    sim_load = 1;
    #10;
    sim_load = 0;
    sim_s = 1;
    #10
    sim_s = 0;
    @(posedge sim_w);
    #10;
    $display("Expected %d, actual %d", 3, cpu_tb.DUT.DP.REGFILE.R1);
//MOV R2, R1
    @(negedge sim_clk);
    sim_in = 16'b1100000001000001;
    sim_load = 1;
    #10;
    sim_load = 0;
    sim_s = 1;
    #10
    sim_s = 0;
    @(posedge sim_w);
    #10;
    $display("Expected %d, actual %d", 3, cpu_tb.DUT.DP.REGFILE.R2);
//ADD R4, R1, R0, LSL#1
    @(negedge sim_clk);
    sim_in = 16'b1010000110001000;
    sim_load = 1;
    #10;
    sim_load = 0;
    sim_s = 1;
    #10
    sim_s = 0;
    @(posedge sim_w);
    #10;
    $display("Expected %d, actual %d", 23, cpu_tb.DUT.DP.REGFILE.R4);
//CMP R1, R0
    @(negedge sim_clk);
    sim_in = 16'b1010100100000000;
    sim_load = 1;
    #10;
    sim_load = 0;
    sim_s = 1;
    #10
    sim_s = 0;
    @(posedge sim_w);
    #10;
    $display("Expected %d, actual %d", 0, sim_Z);
//AND R5, R1, R0
    @(negedge sim_clk);
    sim_in = 16'b1011000110100000;
    sim_load = 1;
    #10;
    sim_load = 0;
    sim_s = 1;
    #10
    sim_s = 0;
    @(posedge sim_w);
    #10;
    $display("Expected %d, actual %d", 2, cpu_tb.DUT.DP.REGFILE.R5);
//MVN R6, R0
    @(negedge sim_clk);
    sim_in = 16'b1011100011000000;
    sim_load = 1;
    #10;
    sim_load = 0;
    sim_s = 1;
    #10
    sim_s = 0;
    @(posedge sim_w);
    #10;
    $display("Expected %d, actual %d", 16'b1111111111110101, cpu_tb.DUT.DP.REGFILE.R6);
    $stop;
end

endmodule