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M3.2: implement SDRAM timing guards - #8
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Implements the selected IS42S16320B-6TLI 100MHz/CL2 timing basis in the native controller. Adds explicit tMRD and write-recovery states, documents tRP/tRCD/tRFC/tMRD/tWR and uses a 7.80us refresh interval. Existing protocol simulation and ECP5 synthesis remain qualification gates.