M.S. Electrical Engineering candidate at Texas State University focused on VLSI, physical design, RTL-to-GDSII implementation, and static timing analysis.
I build reproducible hardware-design workflows that connect RTL development and verification to synthesis, timing analysis, physical implementation, and engineering-data automation.
| Repository | What it demonstrates |
|---|---|
| Physical Design Convergence Analytics | Python tooling for parsing OpenROAD/OpenSTA-style reports and comparing timing, area, utilization, DRC, and clock metrics across implementation runs. |
| RISC-V Datapath in Verilog | A small educational RV32I-style datapath organized into synthesizable ALU, register-file, control, program-counter, and integrated-datapath blocks with self-checking tests. |
| RTL-to-GDSII ALU & Timing Study | A two-stage 32-bit ALU, flow configuration, timing/CTS analysis utilities, and clearly separated reproducible assets versus portfolio-reported historical results. |
- HDL and automation: Verilog/SystemVerilog and Python
- Implementation workflow: OpenLane/OpenROAD configuration scaffolding and OpenSTA-style report analysis
- Design data: SDC plus synthetic timing, CTS, area, utilization, and DRC summaries
- Engineering workflow: Linux-oriented command-line tooling, Git-ready repositories, automated tests, and CI
My broader coursework and project experience also includes VHDL, Tcl, Perl,
Magic, KLayout, Netgen, GTKWave, Liberty, LEF/DEF, GDSII, SPEF, VCD, and the
SKY130A sky130_fd_sc_hd library. These items are listed as background skills;
the featured public repositories do not independently demonstrate every tool.
VLSI Design I & II · Static Timing Analysis · ASIC Design Flow · Physical Verification · Digital Integrated Circuit Design · Computer Architecture · Semiconductor Devices
These repositories are newly prepared, sanitized public portfolio implementations based on independently described educational workflows. They are not the original historical project repositories. They contain reproducible code, synthetic sample reports, and documentation, but no employer source code, proprietary PDK files, confidential reports, internal links, or restricted data. Historical metrics are identified as portfolio-reported records and are kept separate from reproducible sample outputs.